Searched refs:IGC_EIMS (Results 1 – 2 of 2) sorted by relevance
69 #define IGC_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ macro
408 IGC_WRITE_REG(hw, IGC_EIMS, 1u << IGC_MSIX_OTHER_INTR_VEC); in igc_intr_other_enable()820 IGC_WRITE_REG(hw, IGC_EIMS, mask); in igc_rxq_interrupt_setup()2130 IGC_WRITE_REG(hw, IGC_EIMS, mask); in eth_igc_rx_queue_intr_enable()