1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IGC_REGS_H_ 6 #define _IGC_REGS_H_ 7 8 /* General Register Descriptions */ 9 #define IGC_CTRL 0x00000 /* Device Control - RW */ 10 #define IGC_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 11 #define IGC_STATUS 0x00008 /* Device Status - RO */ 12 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */ 13 /* NVM Register Descriptions */ 14 #define IGC_EERD 0x12014 /* EEprom mode read - RW */ 15 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */ 16 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 17 #define IGC_MDIC 0x00020 /* MDI Control - RW */ 18 #define IGC_MDICNFG 0x00E04 /* MDI Config - RW */ 19 #define IGC_REGISTER_SET_SIZE 0x20000 /* CSR Size */ 20 #define IGC_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */ 21 #define IGC_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */ 22 #define IGC_BARCTRL 0x5BBC /* BAR ctrl reg */ 23 #define IGC_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */ 24 #define IGC_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */ 25 #define IGC_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */ 26 #define IGC_MPHY_DATA 0x0E10 /* GBE MPHY Data */ 27 #define IGC_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */ 28 #define IGC_PPHY_CTRL 0x5b48 /* PCIe PHY Control */ 29 #define IGC_I350_BARCTRL 0x5BFC /* BAR ctrl reg */ 30 #define IGC_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/ 31 #define IGC_SCTL 0x00024 /* SerDes Control - RW */ 32 #define IGC_FCAL 0x00028 /* Flow Control Address Low - RW */ 33 #define IGC_FCAH 0x0002C /* Flow Control Address High -RW */ 34 #define IGC_FEXT 0x0002C /* Future Extended - RW */ 35 #define IGC_I225_FLSWCTL 0x12048 /* FLASH control register */ 36 #define IGC_I225_FLSWDATA 0x1204C /* FLASH data register */ 37 #define IGC_I225_FLSWCNT 0x12050 /* FLASH Access Counter */ 38 #define IGC_I225_FLSECU 0x12114 /* FLASH Security */ 39 #define IGC_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 40 #define IGC_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ 41 #define IGC_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 42 #define IGC_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */ 43 #define IGC_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ 44 #define IGC_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ 45 #define IGC_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */ 46 #define IGC_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */ 47 #define IGC_PCIEANACFG 0x00F18 /* PCIE Analog Config */ 48 #define IGC_FCT 0x00030 /* Flow Control Type - RW */ 49 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ 50 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */ 51 #define IGC_ICR 0x01500 /* Intr Cause Read - RC/W1C */ 52 #define IGC_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 53 #define IGC_ICS 0x01504 /* Intr Cause Set - WO */ 54 #define IGC_IMS 0x01508 /* Intr Mask Set/Read - RW */ 55 #define IGC_IMC 0x0150C /* Intr Mask Clear - WO */ 56 #define IGC_IAM 0x01510 /* Intr Ack Auto Mask- RW */ 57 #define IGC_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ 58 #define IGC_SVCR 0x000F0 59 #define IGC_SVT 0x000F4 60 #define IGC_LPIC 0x000FC /* Low Power IDLE control */ 61 #define IGC_RCTL 0x00100 /* Rx Control - RW */ 62 #define IGC_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 63 #define IGC_TXCW 0x00178 /* Tx Configuration Word - RW */ 64 #define IGC_RXCW 0x00180 /* Rx Configuration Word - RO */ 65 #define IGC_PBA_ECC 0x01100 /* PBA ECC Register */ 66 #define IGC_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 67 #define IGC_EITR(_n) (0x01680 + (0x4 * (_n))) 68 #define IGC_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 69 #define IGC_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 70 #define IGC_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 71 #define IGC_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 72 #define IGC_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 73 #define IGC_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ 74 #define IGC_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 75 #define IGC_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 76 #define IGC_TCTL 0x00400 /* Tx Control - RW */ 77 #define IGC_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ 78 #define IGC_TIPG 0x00410 /* Tx Inter-packet gap -RW */ 79 #define IGC_TBT 0x00448 /* Tx Burst Timer - RW */ 80 #define IGC_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 81 #define IGC_LEDCTL 0x00E00 /* LED Control - RW */ 82 #define IGC_LEDMUX 0x08130 /* LED MUX Control */ 83 #define IGC_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 84 #define IGC_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 85 #define IGC_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 86 #define IGC_POEMB IGC_PHY_CTRL /* PHY OEM Bits */ 87 #define IGC_PBA 0x01000 /* Packet Buffer Allocation - RW */ 88 #define IGC_PBS 0x01008 /* Packet Buffer Size */ 89 #define IGC_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ 90 #define IGC_IOSFPC 0x00F28 /* TX corrupted data */ 91 #define IGC_EEMNGCTL 0x01010 /* MNG EEprom Control */ 92 #define IGC_EEMNGCTL_I210 0x01010 /* i210 MNG EEprom Mode Control */ 93 #define IGC_EEMNGCTL_I225 0x01010 /* i225 MNG EEprom Mode Control */ 94 #define IGC_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 95 #define IGC_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */ 96 #define IGC_EEARBC_I225 0x12024 /* EEPROM Auto Read Bus Control */ 97 #define IGC_FLASHT 0x01028 /* FLASH Timer Register */ 98 #define IGC_FLSWCTL 0x01030 /* FLASH control register */ 99 #define IGC_FLSWDATA 0x01034 /* FLASH data register */ 100 #define IGC_FLSWCNT 0x01038 /* FLASH Access Counter */ 101 #define IGC_FLOP 0x0103C /* FLASH Opcode Register */ 102 #define IGC_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ 103 #define IGC_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ 104 #define IGC_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */ 105 #define IGC_I2C_CLK_OUT 0x00000200 /* I2C- Clock */ 106 #define IGC_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */ 107 #define IGC_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */ 108 #define IGC_I2C_DATA_IN 0x00001000 /* I2C- Data In */ 109 #define IGC_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */ 110 #define IGC_I2C_CLK_IN 0x00004000 /* I2C- Clock In */ 111 #define IGC_I2C_CLK_STRETCH_DIS 0x00008000 /* I2C- Dis Clk Stretching */ 112 #define IGC_WDSTP 0x01040 /* Watchdog Setup - RW */ 113 #define IGC_SWDSTS 0x01044 /* SW Device Status - RW */ 114 #define IGC_FRTIMER 0x01048 /* Free Running Timer - RW */ 115 #define IGC_TCPTIMER 0x0104C /* TCP Timer - RW */ 116 #define IGC_VPDDIAG 0x01060 /* VPD Diagnostic - RO */ 117 #define IGC_ICR_V2 0x01500 /* Intr Cause - new location - RC */ 118 #define IGC_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */ 119 #define IGC_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */ 120 #define IGC_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */ 121 #define IGC_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */ 122 #define IGC_ERT 0x02008 /* Early Rx Threshold - RW */ 123 #define IGC_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 124 #define IGC_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 125 #define IGC_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 126 #define IGC_RDFH 0x02410 /* Rx Data FIFO Head - RW */ 127 #define IGC_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ 128 #define IGC_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ 129 #define IGC_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ 130 #define IGC_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ 131 #define IGC_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ 132 #define IGC_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ 133 /* Split and Replication Rx Control - RW */ 134 #define IGC_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ 135 #define IGC_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ 136 #define IGC_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ 137 #define IGC_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ 138 #define IGC_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ 139 #define IGC_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ 140 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ 141 #define IGC_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */ 142 #define IGC_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */ 143 #define IGC_RDTR 0x02820 /* Rx Delay Timer - RW */ 144 #define IGC_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ 145 #define IGC_EMIADD 0x10 /* Extended Memory Indirect Address */ 146 #define IGC_EMIDATA 0x11 /* Extended Memory Indirect Data */ 147 /* Shadow Ram Write Register - RW */ 148 #define IGC_SRWR 0x12018 149 #define IGC_EEC_REG 0x12010 150 151 #define IGC_I210_FLMNGCTL 0x12038 152 #define IGC_I210_FLMNGDATA 0x1203C 153 #define IGC_I210_FLMNGCNT 0x12040 154 155 #define IGC_I210_FLSWCTL 0x12048 156 #define IGC_I210_FLSWDATA 0x1204C 157 #define IGC_I210_FLSWCNT 0x12050 158 159 #define IGC_I210_FLA 0x1201C 160 161 #define IGC_SHADOWINF 0x12068 162 #define IGC_FLFWUPDATE 0x12108 163 164 #define IGC_INVM_DATA_REG(_n) (0x12120 + 4 * (_n)) 165 #define IGC_INVM_SIZE 64 /* Number of INVM Data Registers */ 166 167 /* QAV Tx mode control register */ 168 #define IGC_I210_TQAVCTRL 0x3570 169 170 /* QAV Tx mode control register bitfields masks */ 171 /* QAV enable */ 172 #define IGC_TQAVCTRL_MODE (1 << 0) 173 /* Fetching arbitration type */ 174 #define IGC_TQAVCTRL_FETCH_ARB (1 << 4) 175 /* Fetching timer enable */ 176 #define IGC_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5) 177 /* Launch arbitration type */ 178 #define IGC_TQAVCTRL_LAUNCH_ARB (1 << 8) 179 /* Launch timer enable */ 180 #define IGC_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9) 181 /* SP waits for SR enable */ 182 #define IGC_TQAVCTRL_SP_WAIT_SR (1 << 10) 183 /* Fetching timer correction */ 184 #define IGC_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET 16 185 #define IGC_TQAVCTRL_FETCH_TIMER_DELTA \ 186 (0xFFFF << IGC_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET) 187 188 /* High credit registers where _n can be 0 or 1. */ 189 #define IGC_I210_TQAVHC(_n) (0x300C + 0x40 * (_n)) 190 191 /* Queues fetch arbitration priority control register */ 192 #define IGC_I210_TQAVARBCTRL 0x3574 193 /* Queues priority masks where _n and _p can be 0-3. */ 194 #define IGC_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n))) 195 /* QAV Tx mode control registers where _n can be 0 or 1. */ 196 #define IGC_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n)) 197 198 /* QAV Tx mode control register bitfields masks */ 199 #define IGC_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ 200 #define IGC_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ 201 #define IGC_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ 202 203 /* Good transmitted packets counter registers */ 204 #define IGC_PQGPTC(_n) (0x010014 + (0x100 * (_n))) 205 206 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ 207 #define IGC_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n))) 208 209 #define IGC_MMDAC 13 /* MMD Access Control */ 210 #define IGC_MMDAAD 14 /* MMD Access Address/Data */ 211 212 /* Convenience macros 213 * 214 * Note: "_n" is the queue number of the register 215 * 216 * Example usage: 217 * IGC_RDBAL_REG(current_rx_queue) 218 */ 219 #define IGC_QUEUE_REG(n, low, high) ( \ 220 __extension__ ({ \ 221 typeof(n) _n = (n); \ 222 _n < 4 ? ((low) + _n * 0x100) : ((high) + _n * 0x40); \ 223 })) 224 225 #define IGC_RDBAL(_n) IGC_QUEUE_REG(_n, 0x02800, 0x0C000) 226 #define IGC_RDBAH(_n) IGC_QUEUE_REG(_n, 0x02804, 0x0C004) 227 #define IGC_RDLEN(_n) IGC_QUEUE_REG(_n, 0x02808, 0x0C008) 228 #define IGC_SRRCTL(_n) IGC_QUEUE_REG(_n, 0x0280C, 0x0C00C) 229 #define IGC_RDH(_n) IGC_QUEUE_REG(_n, 0x02810, 0x0C010) 230 #define IGC_RXCTL(_n) IGC_QUEUE_REG(_n, 0x02814, 0x0C014) 231 #define IGC_DCA_RXCTRL(_n) IGC_RXCTL(_n) 232 #define IGC_RDT(_n) IGC_QUEUE_REG(_n, 0x02818, 0x0C018) 233 #define IGC_RXDCTL(_n) IGC_QUEUE_REG(_n, 0x02828, 0x0C028) 234 #define IGC_RQDPC(_n) IGC_QUEUE_REG(_n, 0x02830, 0x0C030) 235 #define IGC_TDBAL(_n) IGC_QUEUE_REG(_n, 0x03800, 0x0E000) 236 #define IGC_TDBAH(_n) IGC_QUEUE_REG(_n, 0x03804, 0x0E004) 237 #define IGC_TDLEN(_n) IGC_QUEUE_REG(_n, 0x03808, 0x0E008) 238 #define IGC_TDH(_n) IGC_QUEUE_REG(_n, 0x03810, 0x0E010) 239 #define IGC_TXCTL(_n) IGC_QUEUE_REG(_n, 0x03814, 0x0E014) 240 #define IGC_DCA_TXCTRL(_n) IGC_TXCTL(_n) 241 #define IGC_TDT(_n) IGC_QUEUE_REG(_n, 0x03818, 0x0E018) 242 #define IGC_TXDCTL(_n) IGC_QUEUE_REG(_n, 0x03828, 0x0E028) 243 #define IGC_TDWBAL(_n) IGC_QUEUE_REG(_n, 0x03838, 0x0E038) 244 #define IGC_TDWBAH(_n) IGC_QUEUE_REG(_n, 0x0383C, 0x0E03C) 245 #define IGC_TARC(_n) (0x03840 + (_n) * 0x100) 246 #define IGC_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ 247 #define IGC_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 248 #define IGC_TXDMAC 0x03000 /* Tx DMA Control - RW */ 249 #define IGC_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 250 #define IGC_PSRTYPE(_i) (0x05480 + ((_i) * 4)) 251 252 #define IGC_RAL(n) ( \ 253 __extension__ ({ \ 254 typeof(n) _n = (n); \ 255 _n < 16 ? (0x05400 + _n * 8) : (0x054E0 + (_n - 16) * 8); \ 256 })) 257 258 #define IGC_RAH(_n) (IGC_RAL(_n) + 4) 259 260 #define IGC_VLAPQF 0x055B0 /* VLAN Priority Queue Filter VLAPQF */ 261 262 #define IGC_SHRAL(_i) (0x05438 + ((_i) * 8)) 263 #define IGC_SHRAH(_i) (0x0543C + ((_i) * 8)) 264 #define IGC_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) 265 #define IGC_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) 266 #define IGC_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) 267 #define IGC_FFMT_REG(_i) (0x09000 + ((_i) * 8)) 268 #define IGC_FFVT_REG(_i) (0x09800 + ((_i) * 8)) 269 #define IGC_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) 270 #define IGC_PBSLAC 0x03100 /* Pkt Buffer Slave Access Control */ 271 #define IGC_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */ 272 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ 273 /* Same as TXPBS, renamed for newer Si - RW */ 274 #define IGC_ITPBS 0x03404 275 #define IGC_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 276 #define IGC_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 277 #define IGC_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 278 #define IGC_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ 279 #define IGC_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ 280 #define IGC_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */ 281 #define IGC_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */ 282 #define IGC_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */ 283 #define IGC_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */ 284 #define IGC_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */ 285 #define IGC_DTXCTL 0x03590 /* DMA Tx Control - RW */ 286 #define IGC_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */ 287 #define IGC_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */ 288 /* DMA Tx Max Total Allow Size Reqs - RW */ 289 #define IGC_DTXMXSZRQ 0x03540 290 #define IGC_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ 291 #define IGC_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ 292 #define IGC_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 293 /* Statistics Register Descriptions */ 294 #define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 295 #define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 296 #define IGC_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 297 #define IGC_RXERRC 0x0400C /* Receive Error Count - R/clr */ 298 #define IGC_MPC 0x04010 /* Missed Packet Count - R/clr */ 299 #define IGC_SCC 0x04014 /* Single Collision Count - R/clr */ 300 #define IGC_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 301 #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */ 302 #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */ 303 #define IGC_COLC 0x04028 /* Collision Count - R/clr */ 304 #define IGC_DC 0x04030 /* Defer Count - R/clr */ 305 #define IGC_TNCRS 0x04034 /* Tx-No CRS - R/clr */ 306 #define IGC_SEC 0x04038 /* Sequence Error Count - R/clr */ 307 #define IGC_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 308 #define IGC_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 309 #define IGC_XONRXC 0x04048 /* XON Rx Count - R/clr */ 310 #define IGC_XONTXC 0x0404C /* XON Tx Count - R/clr */ 311 #define IGC_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ 312 #define IGC_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ 313 #define IGC_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ 314 #define IGC_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ 315 #define IGC_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ 316 #define IGC_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ 317 #define IGC_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ 318 #define IGC_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ 319 #define IGC_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ 320 #define IGC_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ 321 #define IGC_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ 322 #define IGC_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ 323 #define IGC_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ 324 #define IGC_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ 325 #define IGC_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ 326 #define IGC_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ 327 #define IGC_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ 328 #define IGC_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ 329 #define IGC_RUC 0x040A4 /* Rx Undersize Count - R/clr */ 330 #define IGC_RFC 0x040A8 /* Rx Fragment Count - R/clr */ 331 #define IGC_ROC 0x040AC /* Rx Oversize Count - R/clr */ 332 #define IGC_RJC 0x040B0 /* Rx Jabber Count - R/clr */ 333 #define IGC_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ 334 #define IGC_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 335 #define IGC_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ 336 #define IGC_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ 337 #define IGC_TORH 0x040C4 /* Total Octets Rx High - R/clr */ 338 #define IGC_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ 339 #define IGC_TOTH 0x040CC /* Total Octets Tx High - R/clr */ 340 #define IGC_TPR 0x040D0 /* Total Packets Rx - R/clr */ 341 #define IGC_TPT 0x040D4 /* Total Packets Tx - R/clr */ 342 #define IGC_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ 343 #define IGC_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ 344 #define IGC_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ 345 #define IGC_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ 346 #define IGC_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ 347 #define IGC_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ 348 #define IGC_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ 349 #define IGC_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ 350 #define IGC_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ 351 #define IGC_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ 352 #define IGC_IAC 0x04100 /* Interrupt Assertion Count */ 353 /* Interrupt Cause */ 354 #define IGC_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 355 #define IGC_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ 356 #define IGC_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 357 #define IGC_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 358 #define IGC_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 359 #define IGC_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 360 #define IGC_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 361 #define IGC_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 362 #define IGC_CRC_OFFSET 0x05F50 /* CRC Offset register */ 363 364 #define IGC_VFGPRC 0x00F10 365 #define IGC_VFGORC 0x00F18 366 #define IGC_VFMPRC 0x00F3C 367 #define IGC_VFGPTC 0x00F14 368 #define IGC_VFGOTC 0x00F34 369 #define IGC_VFGOTLBC 0x00F50 370 #define IGC_VFGPTLBC 0x00F44 371 #define IGC_VFGORLBC 0x00F48 372 #define IGC_VFGPRLBC 0x00F40 373 /* Virtualization statistical counters */ 374 #define IGC_PFVFGPRC(_n) (0x010010 + (0x100 * (_n))) 375 #define IGC_PFVFGPTC(_n) (0x010014 + (0x100 * (_n))) 376 #define IGC_PFVFGORC(_n) (0x010018 + (0x100 * (_n))) 377 #define IGC_PFVFGOTC(_n) (0x010034 + (0x100 * (_n))) 378 #define IGC_PFVFMPRC(_n) (0x010038 + (0x100 * (_n))) 379 #define IGC_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n))) 380 #define IGC_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n))) 381 #define IGC_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n))) 382 #define IGC_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n))) 383 384 /* LinkSec */ 385 #define IGC_LSECTXUT 0x04300 /* Tx Untagged Pkt Cnt */ 386 #define IGC_LSECTXPKTE 0x04304 /* Encrypted Tx Pkts Cnt */ 387 #define IGC_LSECTXPKTP 0x04308 /* Protected Tx Pkt Cnt */ 388 #define IGC_LSECTXOCTE 0x0430C /* Encrypted Tx Octets Cnt */ 389 #define IGC_LSECTXOCTP 0x04310 /* Protected Tx Octets Cnt */ 390 #define IGC_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */ 391 #define IGC_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */ 392 #define IGC_LSECRXOCTV 0x04320 /* Rx Octets Validated */ 393 #define IGC_LSECRXBAD 0x04324 /* Rx Bad Tag */ 394 #define IGC_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */ 395 #define IGC_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */ 396 #define IGC_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */ 397 #define IGC_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */ 398 #define IGC_LSECRXLATE 0x04350 /* Rx Late Packets Count */ 399 #define IGC_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */ 400 #define IGC_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */ 401 #define IGC_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */ 402 #define IGC_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */ 403 #define IGC_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */ 404 #define IGC_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */ 405 #define IGC_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */ 406 #define IGC_LSECTXCTRL 0x0B004 /* Tx Control - RW */ 407 #define IGC_LSECRXCTRL 0x0B304 /* Rx Control - RW */ 408 #define IGC_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */ 409 #define IGC_LSECTXSCH 0x0B00C /* Tx SCI High - RW */ 410 #define IGC_LSECTXSA 0x0B010 /* Tx SA0 - RW */ 411 #define IGC_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */ 412 #define IGC_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */ 413 #define IGC_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */ 414 #define IGC_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */ 415 /* LinkSec Tx 128-bit Key 0 - WO */ 416 #define IGC_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) 417 /* LinkSec Tx 128-bit Key 1 - WO */ 418 #define IGC_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) 419 #define IGC_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */ 420 #define IGC_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */ 421 /* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit 422 * key - RW. 423 */ 424 #define IGC_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) 425 426 #define IGC_SSVPC 0x041A0 /* Switch Security Violation Pkt Cnt */ 427 #define IGC_IPSCTRL 0xB430 /* IpSec Control Register */ 428 #define IGC_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */ 429 #define IGC_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */ 430 /* IPSec Rx IPv4/v6 Address - RW */ 431 #define IGC_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n))) 432 /* IPSec Rx 128-bit Key - RW */ 433 #define IGC_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) 434 #define IGC_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */ 435 #define IGC_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */ 436 /* IPSec Tx 128-bit Key - RW */ 437 #define IGC_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) 438 #define IGC_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */ 439 #define IGC_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */ 440 #define IGC_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ 441 #define IGC_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 442 #define IGC_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 443 #define IGC_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ 444 #define IGC_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ 445 #define IGC_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ 446 #define IGC_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ 447 #define IGC_RPTHC 0x04104 /* Rx Packets To Host */ 448 #define IGC_HGPTC 0x04118 /* Host Good Packets Tx Count */ 449 #define IGC_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ 450 #define IGC_HGORCL 0x04128 /* Host Good Octets Received Count Low */ 451 #define IGC_HGORCH 0x0412C /* Host Good Octets Received Count High */ 452 #define IGC_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ 453 #define IGC_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ 454 #define IGC_LENERRS 0x04138 /* Length Errors Count */ 455 #define IGC_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ 456 #define IGC_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ 457 #define IGC_PCS_ANADV 0x04218 /* AN advertisement - RW */ 458 #define IGC_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ 459 #define IGC_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ 460 #define IGC_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */ 461 #define IGC_RXCSUM 0x05000 /* Rx Checksum Control - RW */ 462 #define IGC_RLPML 0x05004 /* Rx Long Packet Max Length */ 463 #define IGC_RFCTL 0x05008 /* Receive Filter Control*/ 464 #define IGC_MTA 0x05200 /* Multicast Table Array - RW Array */ 465 #define IGC_RA 0x05400 /* Receive Address - RW Array */ 466 #define IGC_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */ 467 #define IGC_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 468 #define IGC_VT_CTL 0x0581C /* VMDq Control - RW */ 469 #define IGC_CIAA 0x05B88 /* Config Indirect Access Address - RW */ 470 #define IGC_CIAD 0x05B8C /* Config Indirect Access Data - RW */ 471 #define IGC_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ 472 #define IGC_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ 473 #define IGC_WUC 0x05800 /* Wakeup Control - RW */ 474 #define IGC_WUFC 0x05808 /* Wakeup Filter Control - RW */ 475 #define IGC_WUS 0x05810 /* Wakeup Status - RO */ 476 /* Management registers */ 477 #define IGC_MANC 0x05820 /* Management Control - RW */ 478 #define IGC_IPAV 0x05838 /* IP Address Valid - RW */ 479 #define IGC_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 480 #define IGC_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 481 #define IGC_WUPL 0x05900 /* Wakeup Packet Length - RW */ 482 #define IGC_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 483 #define IGC_WUPM_EXT 0x0B800 /* Wakeup Packet Memory Extended - RO Array */ 484 #define IGC_WUFC_EXT 0x0580C /* Wakeup Filter Control Extended - RW */ 485 #define IGC_WUS_EXT 0x05814 /* Wakeup Status Extended - RW1C */ 486 #define IGC_FHFTSL 0x05804 /* Flex Filter Indirect Table Select - RW */ 487 #define IGC_PROXYFCEX 0x05590 /* Proxy Filter Control Extended - RW1C */ 488 #define IGC_PROXYEXS 0x05594 /* Proxy Extended Status - RO */ 489 #define IGC_WFUTPF 0x05500 /* Wake Flex UDP TCP Port Filter - RW Array */ 490 #define IGC_RFUTPF 0x05580 /* Range Flex UDP TCP Port Filter - RW */ 491 #define IGC_RWPFC 0x05584 /* Range Wake Port Filter Control - RW */ 492 #define IGC_WFUTPS 0x05588 /* Wake Filter UDP TCP Status - RW1C */ 493 #define IGC_WCS 0x0558C /* Wake Control Status - RW1C */ 494 /* MSI-X Table Register Descriptions */ 495 #define IGC_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ 496 #define IGC_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 497 #define IGC_HOST_IF 0x08800 /* Host Interface */ 498 #define IGC_HIBBA 0x8F40 /* Host Interface Buffer Base Address */ 499 /* Flexible Host Filter Table */ 500 #define IGC_FHFT(_n) (0x09000 + ((_n) * 0x100)) 501 /* Ext Flexible Host Filter Table */ 502 #define IGC_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100)) 503 504 505 #define IGC_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 506 #define IGC_MANC2H 0x05860 /* Management Control To Host - RW */ 507 /* Management Decision Filters */ 508 #define IGC_MDEF(_n) (0x05890 + (4 * (_n))) 509 /* Semaphore registers */ 510 #define IGC_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ 511 #define IGC_CCMCTL 0x05B48 /* CCM Control Register */ 512 #define IGC_GIOCTL 0x05B44 /* GIO Analog Control Register */ 513 #define IGC_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ 514 /* PCIe Register Description */ 515 #define IGC_GCR 0x05B00 /* PCI-Ex Control */ 516 #define IGC_GCR2 0x05B64 /* PCI-Ex Control #2 */ 517 #define IGC_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 518 #define IGC_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 519 #define IGC_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 520 #define IGC_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 521 /* Function Active and Power State to MNG */ 522 #define IGC_FACTPS 0x05B30 523 #define IGC_SWSM 0x05B50 /* SW Semaphore */ 524 #define IGC_FWSM 0x05B54 /* FW Semaphore */ 525 /* Driver-only SW semaphore (not used by BOOT agents) */ 526 #define IGC_SWSM2 0x05B58 527 #define IGC_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 528 #define IGC_DCA_CTRL 0x05B74 /* DCA Control - RW */ 529 #define IGC_UFUSE 0x05B78 /* UFUSE - RO */ 530 #define IGC_FFLT_DBG 0x05F04 /* Debug Register */ 531 #define IGC_HICR 0x08F00 /* Host Interface Control */ 532 #define IGC_FWSTS 0x08F0C /* FW Status */ 533 534 /* RSS registers */ 535 #define IGC_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 536 #define IGC_MRQC 0x05818 /* Multiple Receive Control - RW */ 537 #define IGC_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ 538 #define IGC_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/ 539 #define IGC_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */ 540 #define IGC_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */ 541 /* Redirection Table - RW Array */ 542 #define IGC_RETA(_i) (0x05C00 + ((_i) * 4)) 543 /* RSS Random Key - RW Array */ 544 #define IGC_RSSRK(_i) (0x05C80 + ((_i) * 4)) 545 #define IGC_RSSIM 0x05864 /* RSS Interrupt Mask */ 546 #define IGC_RSSIR 0x05868 /* RSS Interrupt Request */ 547 #define IGC_UTA 0x0A000 /* Unicast Table Array - RW */ 548 /* VT Registers */ 549 #define IGC_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */ 550 #define IGC_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ 551 #define IGC_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */ 552 #define IGC_VFLRE 0x00C88 /* VF Register Events - RWC */ 553 #define IGC_VFRE 0x00C8C /* VF Receive Enables */ 554 #define IGC_VFTE 0x00C90 /* VF Transmit Enables */ 555 #define IGC_QDE 0x02408 /* Queue Drop Enable - RW */ 556 #define IGC_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */ 557 #define IGC_WVBR 0x03554 /* VM Wrong Behavior - RWS */ 558 #define IGC_RPLOLR 0x05AF0 /* Replication Offload - RW */ 559 #define IGC_IOVTCL 0x05BBC /* IOV Control Register */ 560 #define IGC_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */ 561 #define IGC_VMRVLAN 0x05D90 /* Virtual Mirror Rule VLAN */ 562 #define IGC_VMRVM 0x05DA0 /* Virtual Mirror Rule VM */ 563 #define IGC_MDFB 0x03558 /* Malicious Driver free block */ 564 #define IGC_LVMMC 0x03548 /* Last VM Misbehavior cause */ 565 #define IGC_TXSWC 0x05ACC /* Tx Switch Control */ 566 #define IGC_SCCRL 0x05DB0 /* Storm Control Control */ 567 #define IGC_BSCTRH 0x05DB8 /* Broadcast Storm Control Threshold */ 568 #define IGC_MSCTRH 0x05DBC /* Multicast Storm Control Threshold */ 569 /* These act per VF so an array friendly macro is used */ 570 #define IGC_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) 571 #define IGC_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) 572 #define IGC_VMBMEM(_n) (0x00800 + (64 * (_n))) 573 #define IGC_VFVMBMEM(_n) (0x00800 + (_n)) 574 #define IGC_VMOLR(_n) (0x05AD0 + (4 * (_n))) 575 /* VLAN Virtual Machine Filter - RW */ 576 #define IGC_VLVF(_n) (0x05D00 + (4 * (_n))) 577 #define IGC_VMVIR(_n) (0x03700 + (4 * (_n))) 578 #define IGC_DVMOLR(_n) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */ 579 #define IGC_VTCTRL(_n) (0x10000 + (0x100 * (_n))) /* VT Control */ 580 #define IGC_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 581 #define IGC_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 582 #define IGC_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ 583 #define IGC_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 584 #define IGC_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 585 #define IGC_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ 586 #define IGC_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ 587 #define IGC_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 588 #define IGC_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 589 #define IGC_SYSTIML 0x0B600 /* System time register Low - RO */ 590 #define IGC_SYSTIMH 0x0B604 /* System time register High - RO */ 591 #define IGC_TIMINCA 0x0B608 /* Increment attributes register - RW */ 592 #define IGC_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */ 593 #define IGC_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */ 594 #define IGC_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ 595 #define IGC_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */ 596 #define IGC_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */ 597 #define IGC_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */ 598 #define IGC_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */ 599 #define IGC_SYSTIMR 0x0B6F8 /* System time register Residue */ 600 #define IGC_TSICR 0x0B66C /* Interrupt Cause Register */ 601 #define IGC_TSIM 0x0B674 /* Interrupt Mask Register */ 602 #define IGC_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 603 #define IGC_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 604 605 /* Filtering Registers */ 606 #define IGC_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ 607 #define IGC_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ 608 #define IGC_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ 609 #define IGC_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ 610 #define IGC_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */ 611 #define IGC_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ 612 #define IGC_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ 613 614 #define IGC_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */ 615 #define IGC_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */ 616 #define IGC_RTRPCS 0x2474 /* Rx packet plane control and status */ 617 #define IGC_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */ 618 #define IGC_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ 619 /* Tx Desc plane TC Rate-scheduler config */ 620 #define IGC_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) 621 /* Tx Packet plane TC Rate-Scheduler Config */ 622 #define IGC_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) 623 /* Rx Packet plane TC Rate-Scheduler Config */ 624 #define IGC_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) 625 /* Tx Desc Plane TC Rate-Scheduler Status */ 626 #define IGC_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) 627 /* Tx Desc Plane TC Rate-Scheduler MMW */ 628 #define IGC_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) 629 /* Tx Packet plane TC Rate-Scheduler Status */ 630 #define IGC_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) 631 /* Tx Packet plane TC Rate-scheduler MMW */ 632 #define IGC_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) 633 /* Rx Packet plane TC Rate-Scheduler Status */ 634 #define IGC_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) 635 /* Rx Packet plane TC Rate-Scheduler MMW */ 636 #define IGC_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) 637 /* Tx Desc plane VM Rate-Scheduler MMW*/ 638 #define IGC_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) 639 /* Tx BCN Rate-Scheduler MMW */ 640 #define IGC_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) 641 #define IGC_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */ 642 #define IGC_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */ 643 #define IGC_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */ 644 #define IGC_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */ 645 #define IGC_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */ 646 #define IGC_RTTBCNCR 0xB200 /* Tx BCN Control Register */ 647 #define IGC_RTTBCNTG 0x35A4 /* Tx BCN Tagging */ 648 #define IGC_RTTBCNCP 0xB208 /* Tx BCN Congestion point */ 649 #define IGC_RTRBCNCR 0xB20C /* Rx BCN Control Register */ 650 #define IGC_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */ 651 #define IGC_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */ 652 #define IGC_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */ 653 #define IGC_RTTBCNACH 0x0B214 /* Tx BCN Control High */ 654 #define IGC_RTTBCNACL 0x0B210 /* Tx BCN Control Low */ 655 656 /* DMA Coalescing registers */ 657 #define IGC_DMACR 0x02508 /* Control Register */ 658 #define IGC_DMCTXTH 0x03550 /* Transmit Threshold */ 659 #define IGC_DMCTLX 0x02514 /* Time to Lx Request */ 660 #define IGC_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ 661 #define IGC_DMCCNT 0x05DD4 /* Current Rx Count */ 662 #define IGC_FCRTC 0x02170 /* Flow Control Rx high watermark */ 663 #define IGC_PCIEMISC 0x05BB8 /* PCIE misc config register */ 664 665 /* PCIe Parity Status Register */ 666 #define IGC_PCIEERRSTS 0x05BA8 667 668 #define IGC_PROXYS 0x5F64 /* Proxying Status */ 669 #define IGC_PROXYFC 0x5F60 /* Proxying Filter Control */ 670 /* Thermal sensor configuration and status registers */ 671 #define IGC_THMJT 0x08100 /* Junction Temperature */ 672 #define IGC_THLOWTC 0x08104 /* Low Threshold Control */ 673 #define IGC_THMIDTC 0x08108 /* Mid Threshold Control */ 674 #define IGC_THHIGHTC 0x0810C /* High Threshold Control */ 675 #define IGC_THSTAT 0x08110 /* Thermal Sensor Status */ 676 677 /* Energy Efficient Ethernet "EEE" registers */ 678 #define IGC_IPCNFG 0x0E38 /* Internal PHY Configuration */ 679 #define IGC_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ 680 #define IGC_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/ 681 #define IGC_EEE_SU 0x0E34 /* EEE Setup */ 682 #define IGC_EEE_SU_2P5 0x0E3C /* EEE 2.5G Setup */ 683 #define IGC_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */ 684 #define IGC_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */ 685 686 /* OS2BMC Registers */ 687 #define IGC_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ 688 #define IGC_B2OGPRC 0x04158 /* BMC2OS packets received by host */ 689 #define IGC_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ 690 #define IGC_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ 691 692 #define IGC_LTRMINV 0x5BB0 /* LTR Minimum Value */ 693 #define IGC_LTRMAXV 0x5BB4 /* LTR Maximum Value */ 694 695 696 /* IEEE 1588 TIMESYNCH */ 697 #define IGC_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */ 698 #define IGC_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */ 699 #define IGC_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */ 700 #define IGC_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */ 701 #define IGC_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */ 702 #define IGC_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */ 703 #define IGC_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */ 704 705 #define IGC_LTRC_EEEMS_EN (1 << 5) 706 #define IGC_TW_SYSTEM_100_MASK 0xff00 707 #define IGC_TW_SYSTEM_100_SHIFT 8 708 #define IGC_TW_SYSTEM_1000_MASK 0xff 709 #define IGC_LTRMINV_SCALE_1024 0x02 710 #define IGC_LTRMINV_SCALE_32768 0x03 711 #define IGC_LTRMAXV_SCALE_1024 0x02 712 #define IGC_LTRMAXV_SCALE_32768 0x03 713 #define IGC_LTRMINV_LTRV_MASK 0x1ff 714 #define IGC_LTRMINV_LSNP_REQ 0x80 715 #define IGC_LTRMINV_SCALE_SHIFT 10 716 #define IGC_LTRMAXV_LTRV_MASK 0x1ff 717 #define IGC_LTRMAXV_LSNP_REQ 0x80 718 #define IGC_LTRMAXV_SCALE_SHIFT 10 719 720 #define IGC_MRQC_ENABLE_MASK 0x00000007 721 #define IGC_MRQC_RSS_FIELD_IPV6_EX 0x00080000 722 #define IGC_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 723 724 #endif 725