1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _IAVF_TYPE_H_ 6 #define _IAVF_TYPE_H_ 7 8 #include "iavf_status.h" 9 #include "iavf_osdep.h" 10 #include "iavf_register.h" 11 #include "iavf_adminq.h" 12 #include "iavf_devids.h" 13 14 #define IAVF_RXQ_CTX_DBUFF_SHIFT 7 15 16 #define UNREFERENCED_XPARAMETER 17 #define UNREFERENCED_1PARAMETER(_p) (_p); 18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q); 19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r); 20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s); 21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t); 22 23 #define BIT(a) (1UL << (a)) 24 #define BIT_ULL(a) (1ULL << (a)) 25 26 /* IAVF_MASK is a macro used on 32 bit registers */ 27 #define IAVF_MASK(mask, shift) (mask << shift) 28 29 #define IAVF_MAX_PF 16 30 #define IAVF_MAX_PF_VSI 64 31 #define IAVF_MAX_PF_QP 128 32 #define IAVF_MAX_VSI_QP 16 33 #define IAVF_MAX_VF_VSI 4 34 #define IAVF_MAX_CHAINED_RX_BUFFERS 5 35 36 /* something less than 1 minute */ 37 #define IAVF_HEARTBEAT_TIMEOUT (HZ * 50) 38 39 40 /* Check whether address is multicast. */ 41 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 42 43 /* Check whether an address is broadcast. */ 44 #define IAVF_IS_BROADCAST(address) \ 45 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 46 (((u8 *)(address))[1] == ((u8)0xff))) 47 48 49 /* forward declaration */ 50 struct iavf_hw; 51 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *); 52 53 #define ETH_ALEN 6 54 /* Data type manipulation macros. */ 55 #define IAVF_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 56 #define IAVF_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 57 58 #define IAVF_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 59 #define IAVF_LO_WORD(x) ((u16)((x) & 0xFFFF)) 60 61 #define IAVF_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 62 #define IAVF_LO_BYTE(x) ((u8)((x) & 0xFF)) 63 64 /* Number of Transmit Descriptors must be a multiple of 8. */ 65 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8 66 /* Number of Receive Descriptors must be a multiple of 32 if 67 * the number of descriptors is greater than 32. 68 */ 69 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32 70 71 #define IAVF_DESC_UNUSED(R) \ 72 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 73 (R)->next_to_clean - (R)->next_to_use - 1) 74 75 /* bitfields for Tx queue mapping in QTX_CTL */ 76 #define IAVF_QTX_CTL_VF_QUEUE 0x0 77 #define IAVF_QTX_CTL_VM_QUEUE 0x1 78 #define IAVF_QTX_CTL_PF_QUEUE 0x2 79 80 /* debug masks - set these bits in hw->debug_mask to control output */ 81 enum iavf_debug_mask { 82 IAVF_DEBUG_INIT = 0x00000001, 83 IAVF_DEBUG_RELEASE = 0x00000002, 84 85 IAVF_DEBUG_LINK = 0x00000010, 86 IAVF_DEBUG_PHY = 0x00000020, 87 IAVF_DEBUG_HMC = 0x00000040, 88 IAVF_DEBUG_NVM = 0x00000080, 89 IAVF_DEBUG_LAN = 0x00000100, 90 IAVF_DEBUG_FLOW = 0x00000200, 91 IAVF_DEBUG_DCB = 0x00000400, 92 IAVF_DEBUG_DIAG = 0x00000800, 93 IAVF_DEBUG_FD = 0x00001000, 94 IAVF_DEBUG_PACKAGE = 0x00002000, 95 96 IAVF_DEBUG_AQ_MESSAGE = 0x01000000, 97 IAVF_DEBUG_AQ_DESCRIPTOR = 0x02000000, 98 IAVF_DEBUG_AQ_DESC_BUFFER = 0x04000000, 99 IAVF_DEBUG_AQ_COMMAND = 0x06000000, 100 IAVF_DEBUG_AQ = 0x0F000000, 101 102 IAVF_DEBUG_USER = 0xF0000000, 103 104 IAVF_DEBUG_ALL = 0xFFFFFFFF 105 }; 106 107 /* PCI Bus Info */ 108 #define IAVF_PCI_LINK_STATUS 0xB2 109 #define IAVF_PCI_LINK_WIDTH 0x3F0 110 #define IAVF_PCI_LINK_WIDTH_1 0x10 111 #define IAVF_PCI_LINK_WIDTH_2 0x20 112 #define IAVF_PCI_LINK_WIDTH_4 0x40 113 #define IAVF_PCI_LINK_WIDTH_8 0x80 114 #define IAVF_PCI_LINK_SPEED 0xF 115 #define IAVF_PCI_LINK_SPEED_2500 0x1 116 #define IAVF_PCI_LINK_SPEED_5000 0x2 117 #define IAVF_PCI_LINK_SPEED_8000 0x3 118 119 #define IAVF_MDIO_CLAUSE22_STCODE_MASK IAVF_MASK(1, \ 120 IAVF_GLGEN_MSCA_STCODE_SHIFT) 121 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK IAVF_MASK(1, \ 122 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 123 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK IAVF_MASK(2, \ 124 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 125 126 #define IAVF_MDIO_CLAUSE45_STCODE_MASK IAVF_MASK(0, \ 127 IAVF_GLGEN_MSCA_STCODE_SHIFT) 128 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK IAVF_MASK(0, \ 129 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 130 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK IAVF_MASK(1, \ 131 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 132 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK IAVF_MASK(2, \ 133 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 134 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK IAVF_MASK(3, \ 135 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 136 137 #define IAVF_PHY_COM_REG_PAGE 0x1E 138 #define IAVF_PHY_LED_LINK_MODE_MASK 0xF0 139 #define IAVF_PHY_LED_MANUAL_ON 0x100 140 #define IAVF_PHY_LED_PROV_REG_1 0xC430 141 #define IAVF_PHY_LED_MODE_MASK 0xFFFF 142 #define IAVF_PHY_LED_MODE_ORIG 0x80000000 143 144 /* Memory types */ 145 enum iavf_memset_type { 146 IAVF_NONDMA_MEM = 0, 147 IAVF_DMA_MEM 148 }; 149 150 /* Memcpy types */ 151 enum iavf_memcpy_type { 152 IAVF_NONDMA_TO_NONDMA = 0, 153 IAVF_NONDMA_TO_DMA, 154 IAVF_DMA_TO_DMA, 155 IAVF_DMA_TO_NONDMA 156 }; 157 158 /* These are structs for managing the hardware information and the operations. 159 * The structures of function pointers are filled out at init time when we 160 * know for sure exactly which hardware we're working with. This gives us the 161 * flexibility of using the same main driver code but adapting to slightly 162 * different hardware needs as new parts are developed. For this architecture, 163 * the Firmware and AdminQ are intended to insulate the driver from most of the 164 * future changes, but these structures will also do part of the job. 165 */ 166 enum iavf_mac_type { 167 IAVF_MAC_UNKNOWN = 0, 168 IAVF_MAC_XL710, 169 IAVF_MAC_VF, 170 IAVF_MAC_X722, 171 IAVF_MAC_X722_VF, 172 IAVF_MAC_GENERIC, 173 }; 174 175 enum iavf_vsi_type { 176 IAVF_VSI_MAIN = 0, 177 IAVF_VSI_VMDQ1 = 1, 178 IAVF_VSI_VMDQ2 = 2, 179 IAVF_VSI_CTRL = 3, 180 IAVF_VSI_FCOE = 4, 181 IAVF_VSI_MIRROR = 5, 182 IAVF_VSI_SRIOV = 6, 183 IAVF_VSI_FDIR = 7, 184 IAVF_VSI_TYPE_UNKNOWN 185 }; 186 187 enum iavf_queue_type { 188 IAVF_QUEUE_TYPE_RX = 0, 189 IAVF_QUEUE_TYPE_TX, 190 IAVF_QUEUE_TYPE_PE_CEQ, 191 IAVF_QUEUE_TYPE_UNKNOWN 192 }; 193 194 #define IAVF_HW_CAP_MAX_GPIO 30 195 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO 0 196 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C 1 197 198 enum iavf_acpi_programming_method { 199 IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 200 IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 201 }; 202 203 #define IAVF_WOL_SUPPORT_MASK 0x1 204 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK 0x2 205 #define IAVF_PROXY_SUPPORT_MASK 0x4 206 207 /* Capabilities of a PF or a VF or the whole device */ 208 struct iavf_hw_capabilities { 209 /* Cloud filter modes: 210 * Mode1: Filter on L4 port only 211 * Mode2: Filter for non-tunneled traffic 212 * Mode3: Filter for tunnel traffic 213 */ 214 #define IAVF_CLOUD_FILTER_MODE1 0x6 215 #define IAVF_CLOUD_FILTER_MODE2 0x7 216 #define IAVF_CLOUD_FILTER_MODE3 0x8 217 #define IAVF_SWITCH_MODE_MASK 0xF 218 219 bool dcb; 220 bool fcoe; 221 bool iwarp; 222 u32 num_vsis; 223 u32 num_rx_qp; 224 u32 num_tx_qp; 225 u32 base_queue; 226 u32 num_msix_vectors_vf; 227 u32 max_mtu; 228 bool apm_wol_support; 229 enum iavf_acpi_programming_method acpi_prog_method; 230 bool proxy_support; 231 }; 232 233 struct iavf_mac_info { 234 enum iavf_mac_type type; 235 u8 addr[ETH_ALEN]; 236 u8 perm_addr[ETH_ALEN]; 237 u8 san_addr[ETH_ALEN]; 238 u8 port_addr[ETH_ALEN]; 239 u16 max_fcoeq; 240 }; 241 242 #define IAVF_NVM_EXEC_GET_AQ_RESULT 0x0 243 #define IAVF_NVM_EXEC_FEATURES 0xe 244 #define IAVF_NVM_EXEC_STATUS 0xf 245 246 /* NVMUpdate features API */ 247 #define IAVF_NVMUPD_FEATURES_API_VER_MAJOR 0 248 #define IAVF_NVMUPD_FEATURES_API_VER_MINOR 14 249 #define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 250 251 #define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) 252 253 struct iavf_nvmupd_features { 254 u8 major; 255 u8 minor; 256 u16 size; 257 u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; 258 }; 259 260 #define IAVF_MODULE_SFF_DIAG_CAPAB 0x40 261 /* PCI bus types */ 262 enum iavf_bus_type { 263 iavf_bus_type_unknown = 0, 264 iavf_bus_type_pci, 265 iavf_bus_type_pcix, 266 iavf_bus_type_pci_express, 267 iavf_bus_type_reserved 268 }; 269 270 /* PCI bus speeds */ 271 enum iavf_bus_speed { 272 iavf_bus_speed_unknown = 0, 273 iavf_bus_speed_33 = 33, 274 iavf_bus_speed_66 = 66, 275 iavf_bus_speed_100 = 100, 276 iavf_bus_speed_120 = 120, 277 iavf_bus_speed_133 = 133, 278 iavf_bus_speed_2500 = 2500, 279 iavf_bus_speed_5000 = 5000, 280 iavf_bus_speed_8000 = 8000, 281 iavf_bus_speed_reserved 282 }; 283 284 /* PCI bus widths */ 285 enum iavf_bus_width { 286 iavf_bus_width_unknown = 0, 287 iavf_bus_width_pcie_x1 = 1, 288 iavf_bus_width_pcie_x2 = 2, 289 iavf_bus_width_pcie_x4 = 4, 290 iavf_bus_width_pcie_x8 = 8, 291 iavf_bus_width_32 = 32, 292 iavf_bus_width_64 = 64, 293 iavf_bus_width_reserved 294 }; 295 296 /* Bus parameters */ 297 struct iavf_bus_info { 298 enum iavf_bus_speed speed; 299 enum iavf_bus_width width; 300 enum iavf_bus_type type; 301 302 u16 func; 303 u16 device; 304 u16 lan_id; 305 u16 bus_id; 306 }; 307 308 #define IAVF_MAX_USER_PRIORITY 8 309 #define IAVF_TLV_STATUS_OPER 0x1 310 #define IAVF_TLV_STATUS_SYNC 0x2 311 #define IAVF_TLV_STATUS_ERR 0x4 312 #define IAVF_CEE_OPER_MAX_APPS 3 313 #define IAVF_APP_PROTOID_FCOE 0x8906 314 #define IAVF_APP_PROTOID_ISCSI 0x0cbc 315 #define IAVF_APP_PROTOID_FIP 0x8914 316 #define IAVF_APP_SEL_ETHTYPE 0x1 317 #define IAVF_APP_SEL_TCPIP 0x2 318 #define IAVF_CEE_APP_SEL_ETHTYPE 0x0 319 #define IAVF_CEE_APP_SEL_TCPIP 0x1 320 321 /* Port hardware description */ 322 struct iavf_hw { 323 u8 *hw_addr; 324 void *back; 325 326 /* subsystem structs */ 327 struct iavf_mac_info mac; 328 struct iavf_bus_info bus; 329 330 /* pci info */ 331 u16 device_id; 332 u16 vendor_id; 333 u16 subsystem_device_id; 334 u16 subsystem_vendor_id; 335 u8 revision_id; 336 337 /* capabilities for entire device and PCI func */ 338 struct iavf_hw_capabilities dev_caps; 339 340 /* Admin Queue info */ 341 struct iavf_adminq_info aq; 342 343 /* WoL and proxy support */ 344 u16 num_wol_proxy_filters; 345 u16 wol_proxy_vsi_seid; 346 347 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 348 #define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 349 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 350 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 351 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) 352 u64 flags; 353 354 /* NVMUpdate features */ 355 struct iavf_nvmupd_features nvmupd_features; 356 357 /* debug mask */ 358 u32 debug_mask; 359 char err_str[16]; 360 }; 361 362 struct iavf_driver_version { 363 u8 major_version; 364 u8 minor_version; 365 u8 build_version; 366 u8 subbuild_version; 367 u8 driver_string[32]; 368 }; 369 370 /* RX Descriptors */ 371 union iavf_16byte_rx_desc { 372 struct { 373 __le64 pkt_addr; /* Packet buffer address */ 374 __le64 hdr_addr; /* Header buffer address */ 375 } read; 376 struct { 377 struct { 378 struct { 379 union { 380 __le16 mirroring_status; 381 __le16 fcoe_ctx_id; 382 } mirr_fcoe; 383 __le16 l2tag1; 384 } lo_dword; 385 union { 386 __le32 rss; /* RSS Hash */ 387 __le32 fd_id; /* Flow director filter id */ 388 __le32 fcoe_param; /* FCoE DDP Context id */ 389 } hi_dword; 390 } qword0; 391 struct { 392 /* ext status/error/pktype/length */ 393 __le64 status_error_len; 394 } qword1; 395 } wb; /* writeback */ 396 }; 397 398 union iavf_32byte_rx_desc { 399 struct { 400 __le64 pkt_addr; /* Packet buffer address */ 401 __le64 hdr_addr; /* Header buffer address */ 402 /* bit 0 of hdr_buffer_addr is DD bit */ 403 __le64 rsvd1; 404 __le64 rsvd2; 405 } read; 406 struct { 407 struct { 408 struct { 409 union { 410 __le16 mirroring_status; 411 __le16 fcoe_ctx_id; 412 } mirr_fcoe; 413 __le16 l2tag1; 414 } lo_dword; 415 union { 416 __le32 rss; /* RSS Hash */ 417 __le32 fcoe_param; /* FCoE DDP Context id */ 418 /* Flow director filter id in case of 419 * Programming status desc WB 420 */ 421 __le32 fd_id; 422 } hi_dword; 423 } qword0; 424 struct { 425 /* status/error/pktype/length */ 426 __le64 status_error_len; 427 } qword1; 428 struct { 429 __le16 ext_status; /* extended status */ 430 __le16 rsvd; 431 __le16 l2tag2_1; 432 __le16 l2tag2_2; 433 } qword2; 434 struct { 435 union { 436 __le32 flex_bytes_lo; 437 __le32 pe_status; 438 } lo_dword; 439 union { 440 __le32 flex_bytes_hi; 441 __le32 fd_id; 442 } hi_dword; 443 } qword3; 444 } wb; /* writeback */ 445 }; 446 447 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT 8 448 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 449 IAVF_RXD_QW0_MIRROR_STATUS_SHIFT) 450 #define IAVF_RXD_QW0_FCOEINDX_SHIFT 0 451 #define IAVF_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 452 IAVF_RXD_QW0_FCOEINDX_SHIFT) 453 454 enum iavf_rx_desc_status_bits { 455 /* Note: These are predefined bit offsets */ 456 IAVF_RX_DESC_STATUS_DD_SHIFT = 0, 457 IAVF_RX_DESC_STATUS_EOF_SHIFT = 1, 458 IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 459 IAVF_RX_DESC_STATUS_L3L4P_SHIFT = 3, 460 IAVF_RX_DESC_STATUS_CRCP_SHIFT = 4, 461 IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 462 IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 463 IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 464 465 IAVF_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 466 IAVF_RX_DESC_STATUS_FLM_SHIFT = 11, 467 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 468 IAVF_RX_DESC_STATUS_LPBK_SHIFT = 14, 469 IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 470 IAVF_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 471 IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 472 IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 473 }; 474 475 #define IAVF_RXD_QW1_STATUS_SHIFT 0 476 #define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \ 477 << IAVF_RXD_QW1_STATUS_SHIFT) 478 479 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT 480 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 481 IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT) 482 483 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT 484 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT) 485 486 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT IAVF_RX_DESC_STATUS_UMBCAST 487 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 488 IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT) 489 490 enum iavf_rx_desc_fltstat_values { 491 IAVF_RX_DESC_FLTSTAT_NO_DATA = 0, 492 IAVF_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 493 IAVF_RX_DESC_FLTSTAT_RSV = 2, 494 IAVF_RX_DESC_FLTSTAT_RSS_HASH = 3, 495 }; 496 497 #define IAVF_RXD_PACKET_TYPE_UNICAST 0 498 #define IAVF_RXD_PACKET_TYPE_MULTICAST 1 499 #define IAVF_RXD_PACKET_TYPE_BROADCAST 2 500 #define IAVF_RXD_PACKET_TYPE_MIRRORED 3 501 502 #define IAVF_RXD_QW1_ERROR_SHIFT 19 503 #define IAVF_RXD_QW1_ERROR_MASK (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT) 504 505 enum iavf_rx_desc_error_bits { 506 /* Note: These are predefined bit offsets */ 507 IAVF_RX_DESC_ERROR_RXE_SHIFT = 0, 508 IAVF_RX_DESC_ERROR_RECIPE_SHIFT = 1, 509 IAVF_RX_DESC_ERROR_HBO_SHIFT = 2, 510 IAVF_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 511 IAVF_RX_DESC_ERROR_IPE_SHIFT = 3, 512 IAVF_RX_DESC_ERROR_L4E_SHIFT = 4, 513 IAVF_RX_DESC_ERROR_EIPE_SHIFT = 5, 514 IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 515 IAVF_RX_DESC_ERROR_PPRS_SHIFT = 7 516 }; 517 518 enum iavf_rx_desc_error_l3l4e_fcoe_masks { 519 IAVF_RX_DESC_ERROR_L3L4E_NONE = 0, 520 IAVF_RX_DESC_ERROR_L3L4E_PROT = 1, 521 IAVF_RX_DESC_ERROR_L3L4E_FC = 2, 522 IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 523 IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 524 }; 525 526 #define IAVF_RXD_QW1_PTYPE_SHIFT 30 527 #define IAVF_RXD_QW1_PTYPE_MASK (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT) 528 529 /* Packet type non-ip values */ 530 enum iavf_rx_l2_ptype { 531 IAVF_RX_PTYPE_L2_RESERVED = 0, 532 IAVF_RX_PTYPE_L2_MAC_PAY2 = 1, 533 IAVF_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 534 IAVF_RX_PTYPE_L2_FIP_PAY2 = 3, 535 IAVF_RX_PTYPE_L2_OUI_PAY2 = 4, 536 IAVF_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 537 IAVF_RX_PTYPE_L2_LLDP_PAY2 = 6, 538 IAVF_RX_PTYPE_L2_ECP_PAY2 = 7, 539 IAVF_RX_PTYPE_L2_EVB_PAY2 = 8, 540 IAVF_RX_PTYPE_L2_QCN_PAY2 = 9, 541 IAVF_RX_PTYPE_L2_EAPOL_PAY2 = 10, 542 IAVF_RX_PTYPE_L2_ARP = 11, 543 IAVF_RX_PTYPE_L2_FCOE_PAY3 = 12, 544 IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 545 IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 546 IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 547 IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 548 IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 549 IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 550 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 551 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 552 IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 553 IAVF_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 554 IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 555 IAVF_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 556 IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153, 557 IAVF_RX_PTYPE_PARSER_ABORTED = 255 558 }; 559 560 struct iavf_rx_ptype_decoded { 561 u32 ptype:8; 562 u32 known:1; 563 u32 outer_ip:1; 564 u32 outer_ip_ver:1; 565 u32 outer_frag:1; 566 u32 tunnel_type:3; 567 u32 tunnel_end_prot:2; 568 u32 tunnel_end_frag:1; 569 u32 inner_prot:4; 570 u32 payload_layer:3; 571 }; 572 573 enum iavf_rx_ptype_outer_ip { 574 IAVF_RX_PTYPE_OUTER_L2 = 0, 575 IAVF_RX_PTYPE_OUTER_IP = 1 576 }; 577 578 enum iavf_rx_ptype_outer_ip_ver { 579 IAVF_RX_PTYPE_OUTER_NONE = 0, 580 IAVF_RX_PTYPE_OUTER_IPV4 = 0, 581 IAVF_RX_PTYPE_OUTER_IPV6 = 1 582 }; 583 584 enum iavf_rx_ptype_outer_fragmented { 585 IAVF_RX_PTYPE_NOT_FRAG = 0, 586 IAVF_RX_PTYPE_FRAG = 1 587 }; 588 589 enum iavf_rx_ptype_tunnel_type { 590 IAVF_RX_PTYPE_TUNNEL_NONE = 0, 591 IAVF_RX_PTYPE_TUNNEL_IP_IP = 1, 592 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 593 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 594 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 595 }; 596 597 enum iavf_rx_ptype_tunnel_end_prot { 598 IAVF_RX_PTYPE_TUNNEL_END_NONE = 0, 599 IAVF_RX_PTYPE_TUNNEL_END_IPV4 = 1, 600 IAVF_RX_PTYPE_TUNNEL_END_IPV6 = 2, 601 }; 602 603 enum iavf_rx_ptype_inner_prot { 604 IAVF_RX_PTYPE_INNER_PROT_NONE = 0, 605 IAVF_RX_PTYPE_INNER_PROT_UDP = 1, 606 IAVF_RX_PTYPE_INNER_PROT_TCP = 2, 607 IAVF_RX_PTYPE_INNER_PROT_SCTP = 3, 608 IAVF_RX_PTYPE_INNER_PROT_ICMP = 4, 609 IAVF_RX_PTYPE_INNER_PROT_TIMESYNC = 5 610 }; 611 612 enum iavf_rx_ptype_payload_layer { 613 IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 614 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 615 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 616 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 617 }; 618 619 #define IAVF_RX_PTYPE_BIT_MASK 0x0FFFFFFF 620 #define IAVF_RX_PTYPE_SHIFT 56 621 622 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT 38 623 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 624 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) 625 626 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT 52 627 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 628 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT) 629 630 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT 63 631 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT) 632 633 #define IAVF_RXD_QW1_NEXTP_SHIFT 38 634 #define IAVF_RXD_QW1_NEXTP_MASK (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT) 635 636 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT 0 637 #define IAVF_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 638 IAVF_RXD_QW2_EXT_STATUS_SHIFT) 639 640 enum iavf_rx_desc_ext_status_bits { 641 /* Note: These are predefined bit offsets */ 642 IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 643 IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 644 IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 645 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 646 IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 647 IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 648 IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 649 }; 650 651 #define IAVF_RXD_QW2_L2TAG2_SHIFT 0 652 #define IAVF_RXD_QW2_L2TAG2_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT) 653 654 #define IAVF_RXD_QW2_L2TAG3_SHIFT 16 655 #define IAVF_RXD_QW2_L2TAG3_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT) 656 657 enum iavf_rx_desc_pe_status_bits { 658 /* Note: These are predefined bit offsets */ 659 IAVF_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 660 IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 661 IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 662 IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 663 IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 664 IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 665 IAVF_RX_DESC_PE_STATUS_URG_SHIFT = 27, 666 IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 667 IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 668 }; 669 670 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 671 #define IAVF_RX_PROG_STATUS_DESC_LENGTH 0x2000000 672 673 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 674 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 675 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 676 677 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 678 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 679 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 680 681 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 682 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 683 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 684 685 enum iavf_rx_prog_status_desc_status_bits { 686 /* Note: These are predefined bit offsets */ 687 IAVF_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 688 IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 689 }; 690 691 enum iavf_rx_prog_status_desc_prog_id_masks { 692 IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 693 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 694 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 695 }; 696 697 enum iavf_rx_prog_status_desc_error_bits { 698 /* Note: These are predefined bit offsets */ 699 IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 700 IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 701 IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 702 IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 703 }; 704 705 #define IAVF_TWO_BIT_MASK 0x3 706 #define IAVF_THREE_BIT_MASK 0x7 707 #define IAVF_FOUR_BIT_MASK 0xF 708 #define IAVF_EIGHTEEN_BIT_MASK 0x3FFFF 709 710 /* TX Descriptor */ 711 struct iavf_tx_desc { 712 __le64 buffer_addr; /* Address of descriptor's data buf */ 713 __le64 cmd_type_offset_bsz; 714 }; 715 716 #define IAVF_TXD_QW1_DTYPE_SHIFT 0 717 #define IAVF_TXD_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT) 718 719 enum iavf_tx_desc_dtype_value { 720 IAVF_TX_DESC_DTYPE_DATA = 0x0, 721 IAVF_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 722 IAVF_TX_DESC_DTYPE_CONTEXT = 0x1, 723 IAVF_TX_DESC_DTYPE_FCOE_CTX = 0x2, 724 IAVF_TX_DESC_DTYPE_FILTER_PROG = 0x8, 725 IAVF_TX_DESC_DTYPE_DDP_CTX = 0x9, 726 IAVF_TX_DESC_DTYPE_FLEX_DATA = 0xB, 727 IAVF_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 728 IAVF_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 729 IAVF_TX_DESC_DTYPE_DESC_DONE = 0xF 730 }; 731 732 #define IAVF_TXD_QW1_CMD_SHIFT 4 733 #define IAVF_TXD_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT) 734 735 enum iavf_tx_desc_cmd_bits { 736 IAVF_TX_DESC_CMD_EOP = 0x0001, 737 IAVF_TX_DESC_CMD_RS = 0x0002, 738 IAVF_TX_DESC_CMD_ICRC = 0x0004, 739 IAVF_TX_DESC_CMD_IL2TAG1 = 0x0008, 740 IAVF_TX_DESC_CMD_DUMMY = 0x0010, 741 IAVF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 742 IAVF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 743 IAVF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 744 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 745 IAVF_TX_DESC_CMD_FCOET = 0x0080, 746 IAVF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 747 IAVF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 748 IAVF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 749 IAVF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 750 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 751 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 752 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 753 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 754 }; 755 756 #define IAVF_TXD_QW1_OFFSET_SHIFT 16 757 #define IAVF_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 758 IAVF_TXD_QW1_OFFSET_SHIFT) 759 760 enum iavf_tx_desc_length_fields { 761 /* Note: These are predefined bit offsets */ 762 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 763 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 764 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 765 }; 766 767 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT) 768 #define IAVF_TXD_QW1_IPLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT) 769 #define IAVF_TXD_QW1_L4LEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 770 #define IAVF_TXD_QW1_FCLEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 771 772 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT 34 773 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 774 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) 775 776 #define IAVF_TXD_QW1_L2TAG1_SHIFT 48 777 #define IAVF_TXD_QW1_L2TAG1_MASK (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT) 778 779 /* Context descriptors */ 780 struct iavf_tx_context_desc { 781 __le32 tunneling_params; 782 __le16 l2tag2; 783 __le16 rsvd; 784 __le64 type_cmd_tso_mss; 785 }; 786 787 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT 0 788 #define IAVF_TXD_CTX_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT) 789 790 #define IAVF_TXD_CTX_QW1_CMD_SHIFT 4 791 #define IAVF_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT) 792 793 enum iavf_tx_ctx_desc_cmd_bits { 794 IAVF_TX_CTX_DESC_TSO = 0x01, 795 IAVF_TX_CTX_DESC_TSYN = 0x02, 796 IAVF_TX_CTX_DESC_IL2TAG2 = 0x04, 797 IAVF_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 798 IAVF_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 799 IAVF_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 800 IAVF_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 801 IAVF_TX_CTX_DESC_SWTCH_VSI = 0x30, 802 IAVF_TX_CTX_DESC_SWPE = 0x40 803 }; 804 805 struct iavf_nop_desc { 806 __le64 rsvd; 807 __le64 dtype_cmd; 808 }; 809 810 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT 0 811 #define IAVF_TXD_NOP_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT) 812 813 #define IAVF_TXD_NOP_QW1_CMD_SHIFT 4 814 #define IAVF_TXD_NOP_QW1_CMD_MASK (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT) 815 816 enum iavf_tx_nop_desc_cmd_bits { 817 /* Note: These are predefined bit offsets */ 818 IAVF_TX_NOP_DESC_EOP_SHIFT = 0, 819 IAVF_TX_NOP_DESC_RS_SHIFT = 1, 820 IAVF_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 821 }; 822 823 /* Packet Classifier Types for filters */ 824 enum iavf_filter_pctype { 825 /* Note: Values 0-28 are reserved for future use. 826 * Value 29, 30, 32 are not supported on XL710 and X710. 827 */ 828 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 829 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 830 IAVF_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 831 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 832 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 833 IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 834 IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 835 IAVF_FILTER_PCTYPE_FRAG_IPV4 = 36, 836 /* Note: Values 37-38 are reserved for future use. 837 * Value 39, 40, 42 are not supported on XL710 and X710. 838 */ 839 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 840 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 841 IAVF_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 842 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 843 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 844 IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 845 IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 846 IAVF_FILTER_PCTYPE_FRAG_IPV6 = 46, 847 /* Note: Value 47 is reserved for future use */ 848 IAVF_FILTER_PCTYPE_FCOE_OX = 48, 849 IAVF_FILTER_PCTYPE_FCOE_RX = 49, 850 IAVF_FILTER_PCTYPE_FCOE_OTHER = 50, 851 /* Note: Values 51-62 are reserved for future use */ 852 IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63, 853 }; 854 855 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT 0 856 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT) 857 858 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 859 IAVF_TXD_FLTR_QW1_CMD_SHIFT) 860 #define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT) 861 862 863 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30 864 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 865 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) 866 867 #define IAVF_TXD_CTX_QW1_MSS_SHIFT 50 868 #define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 869 IAVF_TXD_CTX_QW1_MSS_SHIFT) 870 871 #define IAVF_TXD_CTX_QW1_VSI_SHIFT 50 872 #define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT) 873 874 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0 875 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 876 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT) 877 878 enum iavf_tx_ctx_desc_eipt_offload { 879 IAVF_TX_CTX_EXT_IP_NONE = 0x0, 880 IAVF_TX_CTX_EXT_IP_IPV6 = 0x1, 881 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 882 IAVF_TX_CTX_EXT_IP_IPV4 = 0x3 883 }; 884 885 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 886 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 887 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 888 889 #define IAVF_TXD_CTX_QW0_NATT_SHIFT 9 890 #define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 891 892 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT) 893 #define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 894 895 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 896 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \ 897 BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT) 898 899 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK 900 901 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12 902 #define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 903 IAVF_TXD_CTX_QW0_NATLEN_SHIFT) 904 905 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19 906 #define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 907 IAVF_TXD_CTX_QW0_DECTTL_SHIFT) 908 909 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23 910 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT) 911 912 /* Statistics collected by each port, VSI, VEB, and S-channel */ 913 struct iavf_eth_stats { 914 u64 rx_bytes; /* gorc */ 915 u64 rx_unicast; /* uprc */ 916 u64 rx_multicast; /* mprc */ 917 u64 rx_broadcast; /* bprc */ 918 u64 rx_discards; /* rdpc */ 919 u64 rx_unknown_protocol; /* rupp */ 920 u64 tx_bytes; /* gotc */ 921 u64 tx_unicast; /* uptc */ 922 u64 tx_multicast; /* mptc */ 923 u64 tx_broadcast; /* bptc */ 924 u64 tx_discards; /* tdpc */ 925 u64 tx_errors; /* tepc */ 926 }; 927 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR 0x03 928 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR 0x04 929 #define IAVF_SR_OPTION_ROM_PTR 0x05 930 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 931 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR 0x07 932 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 933 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR 0x09 934 #define IAVF_SR_RO_PCIE_LCB_PTR 0x0A 935 #define IAVF_SR_EMP_IMAGE_PTR 0x0B 936 #define IAVF_SR_PE_IMAGE_PTR 0x0C 937 #define IAVF_SR_CSR_PROTECTED_LIST_PTR 0x0D 938 #define IAVF_SR_MNG_CONFIG_PTR 0x0E 939 #define IAVF_SR_PBA_FLAGS 0x15 940 #define IAVF_SR_PBA_BLOCK_PTR 0x16 941 #define IAVF_SR_BOOT_CONFIG_PTR 0x17 942 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 943 #define IAVF_SR_NVM_MAP_VERSION 0x29 944 #define IAVF_SR_NVM_IMAGE_VERSION 0x2A 945 #define IAVF_SR_NVM_STRUCTURE_VERSION 0x2B 946 #define IAVF_SR_PXE_SETUP_PTR 0x30 947 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 948 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO 0x34 949 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI 0x35 950 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 951 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR 0x38 952 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 953 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 954 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 955 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR 0x3D 956 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 957 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 958 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 959 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 960 #define IAVF_SR_EMP_SR_SETTINGS_PTR 0x48 961 #define IAVF_SR_FEATURE_CONFIGURATION_PTR 0x49 962 #define IAVF_SR_CONFIGURATION_METADATA_PTR 0x4D 963 #define IAVF_SR_IMMEDIATE_VALUES_PTR 0x4E 964 #define IAVF_SR_OCP_CFG_WORD0 0x2B 965 #define IAVF_SR_OCP_ENABLED BIT(15) 966 #define IAVF_SR_BUF_ALIGNMENT 4096 967 968 969 struct iavf_lldp_variables { 970 u16 length; 971 u16 adminstatus; 972 u16 msgfasttx; 973 u16 msgtxinterval; 974 u16 txparams; 975 u16 timers; 976 u16 crc8; 977 }; 978 979 /* Offsets into Alternate Ram */ 980 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 981 #define IAVF_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 982 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 983 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 984 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 985 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 986 987 /* Alternate Ram Bandwidth Masks */ 988 #define IAVF_ALT_BW_VALUE_MASK 0xFF 989 #define IAVF_ALT_BW_RELATIVE_MASK 0x40000000 990 #define IAVF_ALT_BW_VALID_MASK 0x80000000 991 992 #define IAVF_DDP_TRACKID_RDONLY 0 993 #define IAVF_DDP_TRACKID_INVALID 0xFFFFFFFF 994 #define SECTION_TYPE_RB_MMIO 0x00001800 995 #define SECTION_TYPE_RB_AQ 0x00001801 996 #define SECTION_TYPE_PROTO 0x80000002 997 #define SECTION_TYPE_PCTYPE 0x80000003 998 #define SECTION_TYPE_PTYPE 0x80000004 999 struct iavf_profile_tlv_section_record { 1000 u8 rtype; 1001 u8 type; 1002 u16 len; 1003 u8 data[12]; 1004 }; 1005 1006 /* Generic AQ section in proflie */ 1007 struct iavf_profile_aq_section { 1008 u16 opcode; 1009 u16 flags; 1010 u8 param[16]; 1011 u16 datalen; 1012 u8 data[1]; 1013 }; 1014 1015 #endif /* _IAVF_TYPE_H_ */ 1016