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Searched refs:GG82563_REG (Results 1 – 3 of 3) sorted by relevance

/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_defines.h1357 #define GG82563_REG(page, reg) \ macro
1362 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1363 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1364 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1365 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1368 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1370 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1374 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1375 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1378 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
H A De1000_80003es2lan.c1176 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), in e1000_setup_copper_link_80003es2lan()
1180 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), in e1000_setup_copper_link_80003es2lan()
1185 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), in e1000_setup_copper_link_80003es2lan()
/f-stack/dpdk/drivers/net/igc/base/
H A Digc_defines.h1452 #define GG82563_REG(page, reg) \ macro
1457 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1458 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1459 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1460 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1463 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1465 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1469 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1470 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1473 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */