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Searched refs:GENMASK (Results 1 – 25 of 30) sorted by relevance

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/f-stack/dpdk/drivers/net/hns3/
H A Dhns3_intr.h42 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
43 #define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
44 #define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
50 #define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
52 #define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
53 #define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
55 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
56 #define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
57 #define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
61 #define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0)
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H A Dhns3_cmd.h383 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
401 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
420 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
427 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
429 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
538 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
666 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
768 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
773 #define HNS3_INT_TYPE_M GENMASK(1, 0)
775 #define HNS3_TQP_ID_M GENMASK(12, 2)
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H A Dhns3_dcb.h59 #define HNS3_DCB_QS_ID_L_MSK GENMASK(9, 0)
61 #define HNS3_DCB_QS_ID_H_MSK GENMASK(14, 10)
64 #define HNS3_DCB_QS_ID_H_EXT_MSK GENMASK(15, 11)
77 #define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
79 #define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
81 #define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
83 #define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
85 #define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
132 #define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
134 #define HNS3_BP_GRP_ID_M GENMASK(9, 5)
H A Dhns3_fdir.c20 #define HNS3_PF_ID_M GENMASK(2, 0)
22 #define HNS3_VF_ID_M GENMASK(10, 3)
25 #define HNS3_NETWORK_PORT_ID_M GENMASK(3, 0)
33 #define HNS3_FD_AD_QID_M GENMASK(11, 2)
36 #define HNS3_FD_AD_COUNTER_NUM_M GENMASK(19, 13)
39 #define HNS3_FD_AD_NXT_KEY_M GENMASK(25, 21)
42 #define HNS3_FD_AD_RULE_ID_M GENMASK(12, 1)
45 #define HNS3_FD_AD_QUEUE_REGION_SIZE_M GENMASK(20, 17)
674 GENMASK(cur_pos + tuple_size, in hns3_fd_convert_meta_data()
680 GENMASK(cur_pos + tuple_size, cur_pos), in hns3_fd_convert_meta_data()
/f-stack/dpdk/drivers/raw/ifpga/base/
H A Dopae_intel_max10.h91 #define MAX10_MAC_BYTE4 GENMASK(7, 0)
92 #define MAX10_MAC_BYTE3 GENMASK(15, 8)
93 #define MAX10_MAC_BYTE2 GENMASK(23, 16)
96 #define MAX10_MAC_BYTE6 GENMASK(7, 0)
97 #define MAX10_MAC_BYTE5 GENMASK(15, 8)
100 #define FPGA_RECONF_PAGE GENMASK(2, 0)
113 #define PCB_INFO GENMASK(31, 24)
120 #define SEC_PROGRESS GENMASK(7, 4)
121 #define HOST_STATUS GENMASK(11, 8)
122 #define SEC_STATUS GENMASK(23, 16)
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H A Dopae_spi.h160 #define REQ_FEC_MODE GENMASK(23, 8)
169 #define NIOS_VERSION_MAJOR GENMASK(31, 28)
170 #define NIOS_VERSION_MINOR GENMASK(27, 24)
171 #define NIOS_VERSION_PATCH GENMASK(23, 20)
H A Dopae_osdep.h44 #ifndef GENMASK
45 #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) macro
H A Dopae_ifpga_hw_api.h46 #define PROP_TOP GENMASK(31, 24)
48 #define PROP_SUB GENMASK(23, 16)
50 #define PROP_ID GENMASK(15, 0)
H A Dopae_eth_group.h51 #define MAC_RESET_MASK GENMASK(2, 0)
/f-stack/freebsd/contrib/ena-com/ena_defs/
H A Dena_eth_io_defs.h306 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
319 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
325 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
336 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
341 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
360 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
361 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
363 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
382 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
384 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
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H A Dena_admin_defs.h1136 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1145 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1153 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1154 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1156 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1162 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1165 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1197 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1211 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1218 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
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/f-stack/freebsd/contrib/ena-com/
H A Dena_eth_io_defs.h308 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
310 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
321 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
327 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
337 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
338 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
343 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
347 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
362 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
369 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
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H A Dena_admin_defs.h933 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
942 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
945 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
950 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
951 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
953 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
959 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
962 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1008 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1010 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
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/f-stack/dpdk/drivers/net/ena/base/ena_defs/
H A Dena_eth_io_defs.h278 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
291 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
297 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
308 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
313 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
332 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
333 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
335 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
354 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
356 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
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H A Dena_admin_defs.h1108 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1117 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1125 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1126 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1128 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1134 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1137 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1169 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1183 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1190 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
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/f-stack/dpdk/drivers/common/octeontx2/
H A Dotx2_common.h44 #ifndef GENMASK
45 #define GENMASK(h, l) \ macro
/f-stack/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_nsp.h65 #define NSP_CODE_MAJOR GENMASK(15, 12)
66 #define NSP_CODE_MINOR GENMASK(11, 0)
/f-stack/dpdk/drivers/net/dpaa2/mc/
H A Dfsl_dprtc_cmd.h45 GENMASK(DPRTC_##field##_SHIFT + DPRTC_##field##_SIZE - 1, \
H A Dfsl_dpkg.h64 GENMASK(DPKG_##field##_SHIFT + DPKG_##field##_SIZE - 1, \
H A Dfsl_dpdmux_cmd.h59 GENMASK(DPDMUX_##field##_SHIFT + DPDMUX_##field##_SIZE - 1, \
/f-stack/dpdk/drivers/bus/fslmc/mc/
H A Dfsl_dpdmai_cmd.h39 GENMASK(DPDMAI_##field##_SHIFT + DPDMAI_##field##_SIZE - 1, \
H A Dfsl_dpio_cmd.h46 GENMASK(DPIO_##field##_SHIFT + DPIO_##field##_SIZE - 1, \
H A Dfsl_mc_cmd.h33 #define GENMASK(h, l) \ macro
H A Dfsl_dpci_cmd.h43 GENMASK(DPCI_##field##_SHIFT + DPCI_##field##_SIZE - 1, \
/f-stack/dpdk/drivers/crypto/dpaa2_sec/mc/
H A Dfsl_dpseci_cmd.h52 GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1, \

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