Home
last modified time | relevance | path

Searched refs:GATE (Results 1 – 11 of 11) sorted by relevance

/f-stack/freebsd/arm64/rockchip/clk/
H A Drk3399_cru.c85 GATE(0, "npll_cs", "npll", 2, 10),
86 GATE(0, "gpll_cs", "gpll", 2, 9),
87 GATE(0, "cpll_cs", "cpll", 2, 8),
89 GATE(0, "gpll_cci_trace", "gpll", 2, 6),
90 GATE(0, "cpll_cci_trace", "cpll", 2, 5),
92 GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3),
93 GATE(0, "npll_aclk_cci_src", "npll", 2, 2),
94 GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),
95 GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0),
103 GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),
[all …]
H A Drk3288_cru.c95 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
96 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
97 GATE(0, "gpll_ddr", "gpll", 0, 9),
98 GATE(0, "dpll_ddr", "dpll", 0, 8),
103 GATE(0, "gpll_core", "gpll", 0, 2),
104 GATE(0, "apll_core", "apll", 0, 1),
146 GATE(0, "vip_src", "vip_src_s", 3, 7),
157 GATE(0, "jtag", "ext_jtag", 4, 14),
170 GATE(0, "i2s_src", "i2s_src_s", 4, 1),
285 GATE(0, "l2ram", "l2ram_s", 12, 4),
[all …]
H A Drk_cru.h48 #define GATE(_idx, _clkname, _pname, _o, _s) \ macro
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c312 GATE(ISPB, "ispb", "clk_m", L(3)),
313 GATE(RTC, "rtc", "clk_s", L(4)),
327 GATE(VI, "vi", "pc_vi", L(20)),
336 GATE(MC, "mem", "clk_m", H(0)),
340 GATE(PMC, "pmc", "clk_s", H(6)),
362 GATE(AFI, "afi", "clk_m", U(8)),
365 GATE(DTV, "dtv", "clk_m", U(15)),
410 GATE(CEC, "cec", "clk_m", W(8)),
426 GATE(MC1, "mc1", "clk_m", W(30)),
432 GATE(ETR, "etr", "clk_m", X(3)),
[all …]
H A Dtegra210_car.c125 #define GATE(_id, cname, plist, o, s) \ macro
250 GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
251 GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
252 GATE(0, "pllD_dsi_csi", "pllD_out0", PLLD_MISC, 21),
253 GATE(0, "pllP_hsio", "pllP_out0", PLLP_MISC1, 29),
254 GATE(0, "pllP_xusb", "pllP_hsio", PLLP_MISC1, 28),
H A Dtegra210_clk_pll.c211 #define GATE(_id, cname, plist, o, s) \ macro
513 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
514 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
515 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c218 GATE(ISPB, "ispb", "clk_m", L(3)),
219 GATE(RTC, "rtc", "clk_s", L(4)),
232 GATE(PWM, "pwm", "pc_pwm", L(17)),
234 GATE(VI, "vi", "pc_vi", L(20)),
236 GATE(ISP, "isp", "pc_isp", L(23)),
240 GATE(VCP, "vcp", "clk_m", L(29)),
245 GATE(MC, "mem", "clk_m", H(0)),
248 GATE(KBC, "kbc", "clk_s", H(4)),
279 GATE(OWR, "owr", "pc_owr", U(7)),
280 GATE(AFI, "afi", "clk_m", U(8)),
[all …]
H A Dtegra124_car.c124 #define GATE(_id, cname, plist, o, s) \ macro
259 GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
260 GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
/f-stack/freebsd/arm64/freescale/imx/
H A Dimx8mq_ccm.c170 GATE(IMX8MQ_ARM_PLL_OUT, "arm_pll_out", "arm_pll_bypass", 0x28, 21),
171 GATE(IMX8MQ_GPU_PLL_OUT, "gpu_pll_out", "gpu_pll_bypass", 0x18, 21),
172 GATE(IMX8MQ_VPU_PLL_OUT, "vpu_pll_out", "vpu_pll_bypass", 0x20, 21),
173 GATE(IMX8MQ_AUDIO_PLL1_OUT, "audio_pll1_out", "audio_pll1_bypass", 0x0, 21),
174 GATE(IMX8MQ_AUDIO_PLL2_OUT, "audio_pll2_out", "audio_pll2_bypass", 0x8, 21),
177 GATE(IMX8MQ_SYS1_PLL_40M_CG, "sys1_pll_40m_cg", "sys1_pll_out", 0x30, 9),
178 GATE(IMX8MQ_SYS1_PLL_80M_CG, "sys1_pll_80m_cg", "sys1_pll_out", 0x30, 11),
179 GATE(IMX8MQ_SYS1_PLL_100M_CG, "sys1_pll_100m_cg", "sys1_pll_out", 0x30, 13),
180 GATE(IMX8MQ_SYS1_PLL_133M_CG, "sys1_pll_133m_cg", "sys1_pll_out", 0x30, 15),
181 GATE(IMX8MQ_SYS1_PLL_160M_CG, "sys1_pll_160m_cg", "sys1_pll_out", 0x30, 17),
[all …]
H A Dimx_ccm_clk.h123 #define GATE(_id, _name, _pname, _o, _shift) \ macro
/f-stack/freebsd/mips/ingenic/
H A Djz4780_clock.c96 #define GATE(_id, cname, pname, bit) { \ macro
348 GATE(JZ4780_CLK_SCC, "scc", "ext", 7),
349 GATE(JZ4780_CLK_AIC, "aic", "ext", 8),
351 GATE(JZ4780_CLK_OWI, "owi", "ext", 10),
352 GATE(JZ4780_CLK_KBC, "kbc", "ext", 13),
361 GATE(JZ4780_CLK_GPS, "gps", "ext", 22),
362 GATE(JZ4780_CLK_MAC, "mac", "ext", 23),
364 GATE(JZ4780_CLK_CIM, "cim", "ext", 26),
365 GATE(JZ4780_CLK_LCD, "lcd", "ext", 28),
366 GATE(JZ4780_CLK_TVE, "tve", "lcd", 27),
[all …]