Searched refs:FPGAMGR_DCLKSTAT (Results 1 – 2 of 2) sorted by relevance
| /f-stack/freebsd/arm/altera/socfpga/ |
| H A D | socfpga_manager.c | 77 #define FPGAMGR_DCLKSTAT 0xC /* DCLK Status Register */ macro
272 if (READ4(sc, FPGAMGR_DCLKSTAT) != 0) in fpga_wait_dclk_pulses()
273 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
281 if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) { in fpga_wait_dclk_pulses()
282 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
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| H A D | socfpga_a10_manager.c | 63 #define FPGAMGR_DCLKSTAT 0xC /* DCLK Status Register */ macro
119 if (READ4(sc, FPGAMGR_DCLKSTAT) != 0) in fpga_wait_dclk_pulses()
120 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
128 if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) { in fpga_wait_dclk_pulses()
129 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
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