1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 5 * reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * NETLOGIC_BSD 31 * $FreeBSD$ 32 */ 33 34 #ifndef __NLM_FMNV2_H__ 35 #define __NLM_FMNV2_H__ 36 37 /** 38 * @file_name fmn.h 39 * @author Netlogic Microsystems 40 * @brief HAL for Fast message network V2 41 */ 42 43 /* FMN configuration registers */ 44 #define CMS_OUTPUTQ_CONFIG(i) ((i)*2) 45 #define CMS_MAX_OUTPUTQ 1024 46 #define CMS_OUTPUTQ_CREDIT_CFG (0x2000/4) 47 #define CMS_MSG_CONFIG (0x2008/4) 48 #define CMS_MSG_ERR (0x2010/4) 49 #define CMS_TRACE_CONFIG (0x2018/4) 50 #define CMS_TRACE_BASE_ADDR (0x2020/4) 51 #define CMS_TRACE_LIMIT_ADDR (0x2028/4) 52 #define CMS_TRACE_CURRENT_ADDR (0x2030/4) 53 #define CMS_MSG_ENDIAN_SWAP (0x2038/4) 54 55 #define CMS_CPU_PUSHQ(node, core, thread, vc) \ 56 (((node)<<10) | ((core)<<4) | ((thread)<<2) | ((vc)<<0)) 57 #define CMS_POPQ(node, queue) (((node)<<10) | (queue)) 58 #define CMS_IO_PUSHQ(node, queue) (((node)<<10) | (queue)) 59 60 #define CMS_POPQ_QID(i) (128+(i)) 61 62 /* FMN Level Interrupt Type */ 63 #define CMS_LVL_INTR_DISABLE 0 64 #define CMS_LVL_LOW_WATERMARK 1 65 #define CMS_LVL_HI_WATERMARK 2 66 67 /* FMN Level interrupt trigger values */ 68 #define CMS_QUEUE_NON_EMPTY 0 69 #define CMS_QUEUE_QUARTER_FULL 1 70 #define CMS_QUEUE_HALF_FULL 2 71 #define CMS_QUEUE_THREE_QUARTER_FULL 3 72 #define CMS_QUEUE_FULL 4 73 74 /* FMN Timer Interrupt Type */ 75 #define CMS_TIMER_INTR_DISABLE 0 76 #define CMS_TIMER_CONSUMER 1 77 #define CMS_TIMER_PRODUCER 1 78 79 /* FMN timer interrupt trigger values */ 80 #define CMS_TWO_POW_EIGHT_CYCLES 0 81 #define CMS_TWO_POW_TEN_CYCLES 1 82 #define CMS_TWO_POW_TWELVE_CYCLES 2 83 #define CMS_TWO_POW_FOURTEEN_CYCLES 3 84 #define CMS_TWO_POW_SIXTEEN_CYCLES 4 85 #define CMS_TWO_POW_EIGHTTEEN_CYCLES 5 86 #define CMS_TWO_POW_TWENTY_CYCLES 6 87 #define CMS_TWO_POW_TWENTYTWO_CYCLES 7 88 89 #define CMS_QUEUE_ENA 1ULL 90 #define CMS_QUEUE_DIS 0 91 #define CMS_SPILL_ENA 1ULL 92 #define CMS_SPILL_DIS 0 93 94 #define CMS_MAX_VCPU_VC 4 95 96 /* Each XLP chip can hold upto 32K messages on the chip itself */ 97 #define CMS_ON_CHIP_MESG_SPACE (32*1024) 98 #define CMS_MAX_ONCHIP_SEGMENTS 1024 99 #define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64 100 101 /* FMN Network error */ 102 #define CMS_ILLEGAL_DST_ERROR 0x100 103 #define CMS_BIU_TIMEOUT_ERROR 0x080 104 #define CMS_BIU_ERROR 0x040 105 #define CMS_SPILL_FILL_UNCORRECT_ECC_ERROR 0x020 106 #define CMS_SPILL_FILL_CORRECT_ECC_ERROR 0x010 107 #define CMS_SPILL_UNCORRECT_ECC_ERROR 0x008 108 #define CMS_SPILL_CORRECT_ECC_ERROR 0x004 109 #define CMS_OUTPUTQ_UNCORRECT_ECC_ERROR 0x002 110 #define CMS_OUTPUTQ_CORRECT_ECC_ERROR 0x001 111 112 /* worst case, a single entry message consists of a 4 byte header 113 * and an 8-byte entry = 12 bytes in total 114 */ 115 #define CMS_SINGLE_ENTRY_MSG_SIZE 12 116 /* total spill memory needed for one FMN queue */ 117 #define CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs) \ 118 ((spilltotmsgs) * (CMS_SINGLE_ENTRY_MSG_SIZE)) 119 120 /* FMN Src station id's */ 121 #define CMS_CPU0_SRC_STID (0 << 4) 122 #define CMS_CPU1_SRC_STID (1 << 4) 123 #define CMS_CPU2_SRC_STID (2 << 4) 124 #define CMS_CPU3_SRC_STID (3 << 4) 125 #define CMS_CPU4_SRC_STID (4 << 4) 126 #define CMS_CPU5_SRC_STID (5 << 4) 127 #define CMS_CPU6_SRC_STID (6 << 4) 128 #define CMS_CPU7_SRC_STID (7 << 4) 129 #define CMS_PCIE0_SRC_STID 256 130 #define CMS_PCIE1_SRC_STID 258 131 #define CMS_PCIE2_SRC_STID 260 132 #define CMS_PCIE3_SRC_STID 262 133 #define CMS_DTE_SRC_STID 264 134 #define CMS_RSA_ECC_SRC_STID 272 135 #define CMS_CRYPTO_SRC_STID 281 136 #define CMS_CMP_SRC_STID 298 137 #define CMS_POE_SRC_STID 384 138 #define CMS_NAE_SRC_STID 476 139 140 /* POPQ related defines */ 141 #define CMS_POPQID_START 128 142 #define CMS_POPQID_END 255 143 144 #define CMS_INT_RCVD 0x800000000000000ULL 145 146 #define nlm_read_cms_reg(b, r) nlm_read_reg64_xkphys(b,r) 147 #define nlm_write_cms_reg(b, r, v) nlm_write_reg64_xkphys(b,r,v) 148 #define nlm_get_cms_pcibase(node) \ 149 nlm_pcicfg_base(XLP_IO_CMS_OFFSET(node)) 150 #define nlm_get_cms_regbase(node) \ 151 nlm_xkphys_map_pcibar0(nlm_get_cms_pcibase(node)) 152 153 #define XLP_CMS_ON_CHIP_PER_QUEUE_SPACE(node) \ 154 ((XLP_CMS_ON_CHIP_MESG_SPACE)/ \ 155 (nlm_read_reg(nlm_pcibase_cms(node), \ 156 XLP_PCI_DEVINFO_REG0)) 157 /* total spill memory needed */ 158 #define XLP_CMS_TOTAL_SPILL_MEM(node, spilltotmsgs) \ 159 ((XLP_CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs)) * \ 160 (nlm_read_reg(nlm_pcibase_cms(node), \ 161 XLP_PCI_DEVINFO_REG0)) 162 #define CMS_TOTAL_QUEUE_SIZE(node, spilltotmsgs) \ 163 ((spilltotmsgs) + (CMS_ON_CHIP_PER_QUEUE_SPACE(node))) 164 165 enum fmn_swcode { 166 FMN_SWCODE_CPU0=1, 167 FMN_SWCODE_CPU1, 168 FMN_SWCODE_CPU2, 169 FMN_SWCODE_CPU3, 170 FMN_SWCODE_CPU4, 171 FMN_SWCODE_CPU5, 172 FMN_SWCODE_CPU6, 173 FMN_SWCODE_CPU7, 174 FMN_SWCODE_CPU8, 175 FMN_SWCODE_CPU9, 176 FMN_SWCODE_CPU10, 177 FMN_SWCODE_CPU11, 178 FMN_SWCODE_CPU12, 179 FMN_SWCODE_CPU13, 180 FMN_SWCODE_CPU14, 181 FMN_SWCODE_CPU15, 182 FMN_SWCODE_CPU16, 183 FMN_SWCODE_CPU17, 184 FMN_SWCODE_CPU18, 185 FMN_SWCODE_CPU19, 186 FMN_SWCODE_CPU20, 187 FMN_SWCODE_CPU21, 188 FMN_SWCODE_CPU22, 189 FMN_SWCODE_CPU23, 190 FMN_SWCODE_CPU24, 191 FMN_SWCODE_CPU25, 192 FMN_SWCODE_CPU26, 193 FMN_SWCODE_CPU27, 194 FMN_SWCODE_CPU28, 195 FMN_SWCODE_CPU29, 196 FMN_SWCODE_CPU30, 197 FMN_SWCODE_CPU31, 198 FMN_SWCODE_CPU32, 199 FMN_SWCODE_PCIE0, 200 FMN_SWCODE_PCIE1, 201 FMN_SWCODE_PCIE2, 202 FMN_SWCODE_PCIE3, 203 FMN_SWCODE_DTE, 204 FMN_SWCODE_CRYPTO, 205 FMN_SWCODE_RSA, 206 FMN_SWCODE_CMP, 207 FMN_SWCODE_POE, 208 FMN_SWCODE_NAE, 209 }; 210 211 extern uint64_t nlm_cms_spill_total_messages; 212 extern uint32_t nlm_cms_total_stations; 213 214 extern uint64_t cms_base_addr(int node); 215 extern int nlm_cms_verify_credit_config (int spill_en, int tot_credit); 216 extern int nlm_cms_get_oc_space(int qsize, int max_queues, int qid, int *ocbase, int *ocstart, int *ocend); 217 extern void nlm_cms_setup_credits (uint64_t base, int destid, int srcid, int credit); 218 extern int nlm_cms_config_onchip_queue (uint64_t base, uint64_t cms_spill_base, int qid, int spill_en); 219 extern void nlm_cms_default_setup(int node, uint64_t spill_base, int spill_en, int popq_en); 220 extern uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid); 221 extern void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val); 222 extern void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type, int intr_val); 223 extern void nlm_cms_level_intr(int node, int sub_type, int intr_val); 224 extern void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type, int intr_val); 225 extern void nlm_cms_timer_intr(int node, int en, int sub_type, int intr_val); 226 extern int nlm_cms_outputq_intr_check(uint64_t base, int qid); 227 extern void nlm_cms_outputq_clr_intr(uint64_t base, int qid); 228 extern void nlm_cms_illegal_dst_error_intr(uint64_t base, int en); 229 extern void nlm_cms_timeout_error_intr(uint64_t base, int en); 230 extern void nlm_cms_biu_error_resp_intr(uint64_t base, int en); 231 extern void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en); 232 extern void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en); 233 extern void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en); 234 extern void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en); 235 extern uint64_t nlm_cms_network_error_status(uint64_t base); 236 extern int nlm_cms_get_net_error_code(uint64_t err); 237 extern int nlm_cms_get_net_error_syndrome(uint64_t err); 238 extern int nlm_cms_get_net_error_ramindex(uint64_t err); 239 extern int nlm_cms_get_net_error_outputq(uint64_t err); 240 extern void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base, uint64_t trace_limit, int match_dstid_en, int dst_id, int match_srcid_en, int src_id, int wrap); 241 extern void nlm_cms_endian_byte_swap (uint64_t base, int en); 242 extern uint8_t xlp_msg_send(uint8_t vc, uint8_t size); 243 extern int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base, 244 int nsegs); 245 extern int nlm_cms_alloc_onchip_q(uint64_t base, int qid, int nsegs); 246 247 #endif 248