1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2015-2018 Intel Corporation 3 */ 4 #ifndef _ICP_QAT_FW_H_ 5 #define _ICP_QAT_FW_H_ 6 #include <sys/types.h> 7 #include "icp_qat_hw.h" 8 9 #define QAT_FIELD_SET(flags, val, bitpos, mask) \ 10 { (flags) = (((flags) & (~((mask) << (bitpos)))) | \ 11 (((val) & (mask)) << (bitpos))) ; } 12 13 #define QAT_FIELD_GET(flags, bitpos, mask) \ 14 (((flags) >> (bitpos)) & (mask)) 15 16 #define ICP_QAT_FW_REQ_DEFAULT_SZ 128 17 #define ICP_QAT_FW_RESP_DEFAULT_SZ 32 18 #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8 19 #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF 20 #define ICP_QAT_FW_NUM_LONGWORDS_1 1 21 #define ICP_QAT_FW_NUM_LONGWORDS_2 2 22 #define ICP_QAT_FW_NUM_LONGWORDS_3 3 23 #define ICP_QAT_FW_NUM_LONGWORDS_4 4 24 #define ICP_QAT_FW_NUM_LONGWORDS_5 5 25 #define ICP_QAT_FW_NUM_LONGWORDS_6 6 26 #define ICP_QAT_FW_NUM_LONGWORDS_7 7 27 #define ICP_QAT_FW_NUM_LONGWORDS_10 10 28 #define ICP_QAT_FW_NUM_LONGWORDS_13 13 29 #define ICP_QAT_FW_NULL_REQ_SERV_ID 1 30 31 enum icp_qat_fw_comn_resp_serv_id { 32 ICP_QAT_FW_COMN_RESP_SERV_NULL, 33 ICP_QAT_FW_COMN_RESP_SERV_CPM_FW, 34 ICP_QAT_FW_COMN_RESP_SERV_DELIMITER 35 }; 36 37 enum icp_qat_fw_comn_request_id { 38 ICP_QAT_FW_COMN_REQ_NULL = 0, 39 ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3, 40 ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4, 41 ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7, 42 ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9, 43 ICP_QAT_FW_COMN_REQ_DELIMITER 44 }; 45 46 struct icp_qat_fw_comn_req_hdr_cd_pars { 47 union { 48 struct { 49 uint64_t content_desc_addr; 50 uint16_t content_desc_resrvd1; 51 uint8_t content_desc_params_sz; 52 uint8_t content_desc_hdr_resrvd2; 53 uint32_t content_desc_resrvd3; 54 } s; 55 struct { 56 uint32_t serv_specif_fields[4]; 57 } s1; 58 } u; 59 }; 60 61 struct icp_qat_fw_comn_req_mid { 62 uint64_t opaque_data; 63 uint64_t src_data_addr; 64 uint64_t dest_data_addr; 65 uint32_t src_length; 66 uint32_t dst_length; 67 }; 68 69 struct icp_qat_fw_comn_req_cd_ctrl { 70 uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5]; 71 }; 72 73 struct icp_qat_fw_comn_req_hdr { 74 uint8_t resrvd1; 75 uint8_t service_cmd_id; 76 uint8_t service_type; 77 uint8_t hdr_flags; 78 uint16_t serv_specif_flags; 79 uint16_t comn_req_flags; 80 }; 81 82 struct icp_qat_fw_comn_req_rqpars { 83 uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13]; 84 }; 85 86 struct icp_qat_fw_comn_req { 87 struct icp_qat_fw_comn_req_hdr comn_hdr; 88 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; 89 struct icp_qat_fw_comn_req_mid comn_mid; 90 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; 91 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; 92 }; 93 94 struct icp_qat_fw_comn_error { 95 uint8_t xlat_err_code; 96 uint8_t cmp_err_code; 97 }; 98 99 struct icp_qat_fw_comn_resp_hdr { 100 uint8_t resrvd1; 101 uint8_t service_id; 102 uint8_t response_type; 103 uint8_t hdr_flags; 104 struct icp_qat_fw_comn_error comn_error; 105 uint8_t comn_status; 106 uint8_t cmd_id; 107 }; 108 109 struct icp_qat_fw_comn_resp { 110 struct icp_qat_fw_comn_resp_hdr comn_hdr; 111 uint64_t opaque_data; 112 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; 113 }; 114 115 #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1 116 #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0 117 #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7 118 #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1 119 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F 120 #define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6 121 #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1 122 #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5 123 #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1 124 #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0 125 #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1 126 127 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \ 128 icp_qat_fw_comn_req_hdr_t.service_type 129 130 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \ 131 icp_qat_fw_comn_req_hdr_t.service_type = val 132 133 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \ 134 icp_qat_fw_comn_req_hdr_t.service_cmd_id 135 136 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \ 137 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val 138 139 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \ 140 ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags) 141 142 #define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \ 143 QAT_FIELD_GET(hdr_flags, \ 144 ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \ 145 ICP_QAT_FW_COMN_CNVNR_FLAG_MASK) 146 147 #define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \ 148 QAT_FIELD_GET(hdr_flags, \ 149 ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \ 150 ICP_QAT_FW_COMN_CNV_FLAG_MASK) 151 152 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \ 153 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) 154 155 #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \ 156 QAT_FIELD_GET(hdr_flags, \ 157 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 158 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 159 160 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \ 161 (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK) 162 163 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ 164 QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ 165 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 166 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 167 168 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \ 169 (((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \ 170 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) 171 172 #define QAT_COMN_PTR_TYPE_BITPOS 0 173 #define QAT_COMN_PTR_TYPE_MASK 0x1 174 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1 175 #define QAT_COMN_CD_FLD_TYPE_MASK 0x1 176 #define QAT_COMN_PTR_TYPE_FLAT 0x0 177 #define QAT_COMN_PTR_TYPE_SGL 0x1 178 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0 179 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1 180 #define QAT_COMN_EXT_FLAGS_BITPOS 8 181 #define QAT_COMN_EXT_FLAGS_MASK 0x1 182 #define QAT_COMN_EXT_FLAGS_USED 0x1 183 184 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \ 185 ((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \ 186 | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS)) 187 188 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \ 189 QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK) 190 191 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \ 192 QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \ 193 QAT_COMN_CD_FLD_TYPE_MASK) 194 195 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ 196 QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \ 197 QAT_COMN_PTR_TYPE_MASK) 198 199 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ 200 QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \ 201 QAT_COMN_CD_FLD_TYPE_MASK) 202 203 #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4 204 #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0 205 #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0 206 #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F 207 208 #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \ 209 ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \ 210 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 211 212 #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 213 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ 214 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 215 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ 216 & ICP_QAT_FW_COMN_NEXT_ID_MASK)); } 217 218 #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \ 219 (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) 220 221 #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 222 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ 223 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 224 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); } 225 226 #define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \ 227 do { \ 228 (next_curr_id) = \ 229 (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 230 (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \ 231 ICP_QAT_FW_COMN_NEXT_ID_MASK)) \ 232 } while (0) 233 234 #define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \ 235 do { \ 236 (next_curr_id) = \ 237 (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 238 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \ 239 } while (0) 240 241 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7 242 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1 243 #define QAT_COMN_RESP_PKE_STATUS_BITPOS 6 244 #define QAT_COMN_RESP_PKE_STATUS_MASK 0x1 245 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5 246 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1 247 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4 248 #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1 249 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3 250 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1 251 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2 252 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1 253 #define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0 254 #define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1 255 256 #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \ 257 QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \ 258 QAT_COMN_RESP_CRYPTO_STATUS_MASK) 259 260 #define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \ 261 QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \ 262 QAT_COMN_RESP_PKE_STATUS_MASK) 263 264 #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \ 265 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \ 266 QAT_COMN_RESP_CMP_STATUS_MASK) 267 268 #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \ 269 QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \ 270 QAT_COMN_RESP_XLAT_STATUS_MASK) 271 272 #define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \ 273 QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \ 274 QAT_COMN_RESP_XLT_WA_APPLIED_MASK) 275 276 #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \ 277 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \ 278 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) 279 280 #define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \ 281 QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \ 282 QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK) 283 284 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0 285 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1 286 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0 287 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1 288 #define ERR_CODE_NO_ERROR 0 289 #define ERR_CODE_INVALID_BLOCK_TYPE -1 290 #define ERR_CODE_NO_MATCH_ONES_COMP -2 291 #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3 292 #define ERR_CODE_INCOMPLETE_LEN -4 293 #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5 294 #define ERR_CODE_RPT_GT_SPEC_LEN -6 295 #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7 296 #define ERR_CODE_INV_DIS_CODE_LEN -8 297 #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9 298 #define ERR_CODE_DIS_TOO_FAR_BACK -10 299 #define ERR_CODE_OVERFLOW_ERROR -11 300 #define ERR_CODE_SOFT_ERROR -12 301 #define ERR_CODE_FATAL_ERROR -13 302 #define ERR_CODE_COMP_OUTPUT_CORRUPTION -14 303 #define ERR_CODE_HW_INCOMPLETE_FILE -15 304 #define ERR_CODE_SSM_ERROR -16 305 #define ERR_CODE_ENDPOINT_ERROR -17 306 #define ERR_CODE_CNV_ERROR -18 307 #define ERR_CODE_EMPTY_DYM_BLOCK -19 308 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20 309 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21 310 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22 311 #define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23 312 313 enum icp_qat_fw_slice { 314 ICP_QAT_FW_SLICE_NULL = 0, 315 ICP_QAT_FW_SLICE_CIPHER = 1, 316 ICP_QAT_FW_SLICE_AUTH = 2, 317 ICP_QAT_FW_SLICE_DRAM_RD = 3, 318 ICP_QAT_FW_SLICE_DRAM_WR = 4, 319 ICP_QAT_FW_SLICE_COMP = 5, 320 ICP_QAT_FW_SLICE_XLAT = 6, 321 ICP_QAT_FW_SLICE_DELIMITER 322 }; 323 #endif 324