1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _E1000_REGS_H_ 6 #define _E1000_REGS_H_ 7 8 #define E1000_CTRL 0x00000 /* Device Control - RW */ 9 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 10 #define E1000_STATUS 0x00008 /* Device Status - RO */ 11 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 12 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 13 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 14 #define E1000_FLA 0x0001C /* Flash Access - RW */ 15 #define E1000_MDIC 0x00020 /* MDI Control - RW */ 16 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ 17 #define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */ 18 #define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */ 19 #define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */ 20 #define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */ 21 #define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */ 22 #define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */ 23 #define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */ 24 #define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */ 25 #define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */ 26 #define E1000_PPHY_CTRL 0x5b48 /* PCIe PHY Control */ 27 #define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */ 28 #define E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/ 29 #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 30 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 31 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 32 #define E1000_FEXT 0x0002C /* Future Extended - RW */ 33 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 34 #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ 35 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 36 #define E1000_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */ 37 #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ 38 #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ 39 #define E1000_FEXTNVM8 0x5BB0 /* Future Extended NVM 8 - RW */ 40 #define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */ 41 #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */ 42 #define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */ 43 #define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */ 44 #define E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */ 45 #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 46 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ 47 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 48 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 49 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 50 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 51 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 52 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 53 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 54 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ 55 #define E1000_SVCR 0x000F0 56 #define E1000_SVT 0x000F4 57 #define E1000_LPIC 0x000FC /* Low Power IDLE control */ 58 #define E1000_RCTL 0x00100 /* Rx Control - RW */ 59 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 60 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 61 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 62 #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 63 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 64 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 65 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 66 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 67 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 68 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 69 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 70 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ 71 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 72 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 73 #define E1000_TCTL 0x00400 /* Tx Control - RW */ 74 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ 75 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ 76 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */ 77 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 78 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 79 #define E1000_LEDMUX 0x08130 /* LED MUX Control */ 80 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 81 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 82 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 83 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ 84 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 85 #define E1000_PBS 0x01008 /* Packet Buffer Size */ 86 #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ 87 #define E1000_IOSFPC 0x00F28 /* TX corrupted data */ 88 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 89 #define E1000_EEMNGCTL_I210 0x01010 /* i210 MNG EEprom Mode Control */ 90 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 91 #define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */ 92 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 93 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 94 #define E1000_FLSWCTL 0x01030 /* FLASH control register */ 95 #define E1000_FLSWDATA 0x01034 /* FLASH data register */ 96 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 97 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 98 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ 99 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ 100 #define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */ 101 #define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */ 102 #define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */ 103 #define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */ 104 #define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */ 105 #define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */ 106 #define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */ 107 #define E1000_I2C_CLK_STRETCH_DIS 0x00008000 /* I2C- Dis Clk Stretching */ 108 #define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ 109 #define E1000_SWDSTS 0x01044 /* SW Device Status - RW */ 110 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ 111 #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ 112 #define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */ 113 #define E1000_ICR_V2 0x01500 /* Intr Cause - new location - RC */ 114 #define E1000_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */ 115 #define E1000_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */ 116 #define E1000_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */ 117 #define E1000_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */ 118 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 119 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 120 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 121 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 122 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */ 123 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ 124 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ 125 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ 126 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ 127 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ 128 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ 129 /* Split and Replication Rx Control - RW */ 130 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ 131 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ 132 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ 133 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ 134 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ 135 #define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ 136 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ 137 #define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */ 138 #define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */ 139 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 140 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ 141 #define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */ 142 #define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */ 143 /* Shadow Ram Write Register - RW */ 144 #define E1000_SRWR 0x12018 145 #define E1000_EEC_REG 0x12010 146 147 #define E1000_I210_FLMNGCTL 0x12038 148 #define E1000_I210_FLMNGDATA 0x1203C 149 #define E1000_I210_FLMNGCNT 0x12040 150 151 #define E1000_I210_FLSWCTL 0x12048 152 #define E1000_I210_FLSWDATA 0x1204C 153 #define E1000_I210_FLSWCNT 0x12050 154 155 #define E1000_I210_FLA 0x1201C 156 157 #define E1000_SHADOWINF 0x12068 158 #define E1000_FLFWUPDATE 0x12108 159 160 #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n)) 161 #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */ 162 163 /* QAV Tx mode control register */ 164 #define E1000_I210_TQAVCTRL 0x3570 165 166 /* QAV Tx mode control register bitfields masks */ 167 /* QAV enable */ 168 #define E1000_TQAVCTRL_MODE (1 << 0) 169 /* Fetching arbitration type */ 170 #define E1000_TQAVCTRL_FETCH_ARB (1 << 4) 171 /* Fetching timer enable */ 172 #define E1000_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5) 173 /* Launch arbitration type */ 174 #define E1000_TQAVCTRL_LAUNCH_ARB (1 << 8) 175 /* Launch timer enable */ 176 #define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9) 177 /* SP waits for SR enable */ 178 #define E1000_TQAVCTRL_SP_WAIT_SR (1 << 10) 179 /* Fetching timer correction */ 180 #define E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET 16 181 #define E1000_TQAVCTRL_FETCH_TIMER_DELTA \ 182 (0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET) 183 184 /* High credit registers where _n can be 0 or 1. */ 185 #define E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n)) 186 187 /* Queues fetch arbitration priority control register */ 188 #define E1000_I210_TQAVARBCTRL 0x3574 189 /* Queues priority masks where _n and _p can be 0-3. */ 190 #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n))) 191 /* QAV Tx mode control registers where _n can be 0 or 1. */ 192 #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n)) 193 194 /* QAV Tx mode control register bitfields masks */ 195 #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ 196 #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ 197 #define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ 198 199 /* Good transmitted packets counter registers */ 200 #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n))) 201 202 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ 203 #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n))) 204 205 #define E1000_MMDAC 13 /* MMD Access Control */ 206 #define E1000_MMDAAD 14 /* MMD Access Address/Data */ 207 208 /* Convenience macros 209 * 210 * Note: "_n" is the queue number of the register to be written to. 211 * 212 * Example usage: 213 * E1000_RDBAL_REG(current_rx_queue) 214 */ 215 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ 216 (0x0C000 + ((_n) * 0x40))) 217 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 218 (0x0C004 + ((_n) * 0x40))) 219 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 220 (0x0C008 + ((_n) * 0x40))) 221 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ 222 (0x0C00C + ((_n) * 0x40))) 223 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 224 (0x0C010 + ((_n) * 0x40))) 225 #define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \ 226 (0x0C014 + ((_n) * 0x40))) 227 #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n) 228 #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 229 (0x0C018 + ((_n) * 0x40))) 230 #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 231 (0x0C028 + ((_n) * 0x40))) 232 #define E1000_RQDPC(_n) ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \ 233 (0x0C030 + ((_n) * 0x40))) 234 #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 235 (0x0E000 + ((_n) * 0x40))) 236 #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 237 (0x0E004 + ((_n) * 0x40))) 238 #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 239 (0x0E008 + ((_n) * 0x40))) 240 #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 241 (0x0E010 + ((_n) * 0x40))) 242 #define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \ 243 (0x0E014 + ((_n) * 0x40))) 244 #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n) 245 #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 246 (0x0E018 + ((_n) * 0x40))) 247 #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 248 (0x0E028 + ((_n) * 0x40))) 249 #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \ 250 (0x0E038 + ((_n) * 0x40))) 251 #define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \ 252 (0x0E03C + ((_n) * 0x40))) 253 #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100)) 254 #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ 255 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 256 #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ 257 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 258 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) 259 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 260 (0x054E0 + ((_i - 16) * 8))) 261 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 262 (0x054E4 + ((_i - 16) * 8))) 263 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) 264 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) 265 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) 266 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) 267 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) 268 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) 269 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) 270 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) 271 #define E1000_PBSLAC 0x03100 /* Pkt Buffer Slave Access Control */ 272 #define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */ 273 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ 274 /* Same as TXPBS, renamed for newer Si - RW */ 275 #define E1000_ITPBS 0x03404 276 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 277 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 278 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 279 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ 280 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ 281 #define E1000_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */ 282 #define E1000_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */ 283 #define E1000_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */ 284 #define E1000_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */ 285 #define E1000_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */ 286 #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ 287 #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */ 288 #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */ 289 /* DMA Tx Max Total Allow Size Reqs - RW */ 290 #define E1000_DTXMXSZRQ 0x03540 291 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ 292 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ 293 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 294 /* Statistics Register Descriptions */ 295 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 296 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 297 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 298 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 299 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 300 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 301 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 302 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 303 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 304 #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 305 #define E1000_DC 0x04030 /* Defer Count - R/clr */ 306 #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ 307 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 308 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 309 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 310 #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ 311 #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ 312 #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ 313 #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ 314 #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ 315 #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ 316 #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ 317 #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ 318 #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ 319 #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ 320 #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ 321 #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ 322 #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ 323 #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ 324 #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ 325 #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ 326 #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ 327 #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ 328 #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ 329 #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ 330 #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ 331 #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ 332 #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ 333 #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ 334 #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ 335 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 336 #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ 337 #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ 338 #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ 339 #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ 340 #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ 341 #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ 342 #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ 343 #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ 344 #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ 345 #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ 346 #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ 347 #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ 348 #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ 349 #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ 350 #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ 351 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ 352 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ 353 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 354 /* Interrupt Cause */ 355 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 356 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ 357 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 358 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 359 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 360 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 361 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 362 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 363 #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ 364 365 #define E1000_VFGPRC 0x00F10 366 #define E1000_VFGORC 0x00F18 367 #define E1000_VFMPRC 0x00F3C 368 #define E1000_VFGPTC 0x00F14 369 #define E1000_VFGOTC 0x00F34 370 #define E1000_VFGOTLBC 0x00F50 371 #define E1000_VFGPTLBC 0x00F44 372 #define E1000_VFGORLBC 0x00F48 373 #define E1000_VFGPRLBC 0x00F40 374 /* Virtualization statistical counters */ 375 #define E1000_PFVFGPRC(_n) (0x010010 + (0x100 * (_n))) 376 #define E1000_PFVFGPTC(_n) (0x010014 + (0x100 * (_n))) 377 #define E1000_PFVFGORC(_n) (0x010018 + (0x100 * (_n))) 378 #define E1000_PFVFGOTC(_n) (0x010034 + (0x100 * (_n))) 379 #define E1000_PFVFMPRC(_n) (0x010038 + (0x100 * (_n))) 380 #define E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n))) 381 #define E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n))) 382 #define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n))) 383 #define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n))) 384 385 /* LinkSec */ 386 #define E1000_LSECTXUT 0x04300 /* Tx Untagged Pkt Cnt */ 387 #define E1000_LSECTXPKTE 0x04304 /* Encrypted Tx Pkts Cnt */ 388 #define E1000_LSECTXPKTP 0x04308 /* Protected Tx Pkt Cnt */ 389 #define E1000_LSECTXOCTE 0x0430C /* Encrypted Tx Octets Cnt */ 390 #define E1000_LSECTXOCTP 0x04310 /* Protected Tx Octets Cnt */ 391 #define E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */ 392 #define E1000_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */ 393 #define E1000_LSECRXOCTV 0x04320 /* Rx Octets Validated */ 394 #define E1000_LSECRXBAD 0x04324 /* Rx Bad Tag */ 395 #define E1000_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */ 396 #define E1000_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */ 397 #define E1000_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */ 398 #define E1000_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */ 399 #define E1000_LSECRXLATE 0x04350 /* Rx Late Packets Count */ 400 #define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */ 401 #define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */ 402 #define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */ 403 #define E1000_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */ 404 #define E1000_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */ 405 #define E1000_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */ 406 #define E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */ 407 #define E1000_LSECTXCTRL 0x0B004 /* Tx Control - RW */ 408 #define E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */ 409 #define E1000_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */ 410 #define E1000_LSECTXSCH 0x0B00C /* Tx SCI High - RW */ 411 #define E1000_LSECTXSA 0x0B010 /* Tx SA0 - RW */ 412 #define E1000_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */ 413 #define E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */ 414 #define E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */ 415 #define E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */ 416 /* LinkSec Tx 128-bit Key 0 - WO */ 417 #define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) 418 /* LinkSec Tx 128-bit Key 1 - WO */ 419 #define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) 420 #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */ 421 #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */ 422 /* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit 423 * key - RW. 424 */ 425 #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) 426 427 #define E1000_SSVPC 0x041A0 /* Switch Security Violation Pkt Cnt */ 428 #define E1000_IPSCTRL 0xB430 /* IpSec Control Register */ 429 #define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */ 430 #define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */ 431 /* IPSec Rx IPv4/v6 Address - RW */ 432 #define E1000_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n))) 433 /* IPSec Rx 128-bit Key - RW */ 434 #define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) 435 #define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */ 436 #define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */ 437 /* IPSec Tx 128-bit Key - RW */ 438 #define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) 439 #define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */ 440 #define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */ 441 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ 442 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 443 #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 444 #define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ 445 #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ 446 #define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ 447 #define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ 448 #define E1000_RPTHC 0x04104 /* Rx Packets To Host */ 449 #define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */ 450 #define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ 451 #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ 452 #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ 453 #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ 454 #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ 455 #define E1000_LENERRS 0x04138 /* Length Errors Count */ 456 #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ 457 #define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ 458 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ 459 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ 460 #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ 461 #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */ 462 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ 463 #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ 464 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 465 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 466 #define E1000_RA 0x05400 /* Receive Address - RW Array */ 467 #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */ 468 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 469 #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ 470 #define E1000_CIAA 0x05B88 /* Config Indirect Access Address - RW */ 471 #define E1000_CIAD 0x05B8C /* Config Indirect Access Data - RW */ 472 #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ 473 #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ 474 #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 475 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 476 #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 477 /* Management registers */ 478 #define E1000_MANC 0x05820 /* Management Control - RW */ 479 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 480 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 481 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 482 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 483 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 484 /* MSI-X Table Register Descriptions */ 485 #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ 486 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 487 #define E1000_HOST_IF 0x08800 /* Host Interface */ 488 #define E1000_HIBBA 0x8F40 /* Host Interface Buffer Base Address */ 489 /* Flexible Host Filter Table */ 490 #define E1000_FHFT(_n) (0x09000 + ((_n) * 0x100)) 491 /* Ext Flexible Host Filter Table */ 492 #define E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100)) 493 494 495 #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 496 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 497 /* Management Decision Filters */ 498 #define E1000_MDEF(_n) (0x05890 + (4 * (_n))) 499 /* Semaphore registers */ 500 #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ 501 #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ 502 #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ 503 #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ 504 /* PCIe Register Description */ 505 #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 506 #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 507 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 508 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 509 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 510 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 511 /* Function Active and Power State to MNG */ 512 #define E1000_FACTPS 0x05B30 513 #define E1000_SWSM 0x05B50 /* SW Semaphore */ 514 #define E1000_FWSM 0x05B54 /* FW Semaphore */ 515 /* Driver-only SW semaphore (not used by BOOT agents) */ 516 #define E1000_SWSM2 0x05B58 517 #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 518 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ 519 #define E1000_UFUSE 0x05B78 /* UFUSE - RO */ 520 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 521 #define E1000_HICR 0x08F00 /* Host Interface Control */ 522 #define E1000_FWSTS 0x08F0C /* FW Status */ 523 524 /* RSS registers */ 525 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 526 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 527 #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ 528 #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/ 529 #define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */ 530 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */ 531 /* Redirection Table - RW Array */ 532 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 533 /* RSS Random Key - RW Array */ 534 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) 535 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 536 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 537 /* VT Registers */ 538 #define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */ 539 #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ 540 #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */ 541 #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */ 542 #define E1000_VFRE 0x00C8C /* VF Receive Enables */ 543 #define E1000_VFTE 0x00C90 /* VF Transmit Enables */ 544 #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */ 545 #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */ 546 #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */ 547 #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ 548 #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ 549 #define E1000_IOVTCL 0x05BBC /* IOV Control Register */ 550 #define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */ 551 #define E1000_VMRVLAN 0x05D90 /* Virtual Mirror Rule VLAN */ 552 #define E1000_VMRVM 0x05DA0 /* Virtual Mirror Rule VM */ 553 #define E1000_MDFB 0x03558 /* Malicious Driver free block */ 554 #define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */ 555 #define E1000_TXSWC 0x05ACC /* Tx Switch Control */ 556 #define E1000_SCCRL 0x05DB0 /* Storm Control Control */ 557 #define E1000_BSCTRH 0x05DB8 /* Broadcast Storm Control Threshold */ 558 #define E1000_MSCTRH 0x05DBC /* Multicast Storm Control Threshold */ 559 /* These act per VF so an array friendly macro is used */ 560 #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) 561 #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) 562 #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 563 #define E1000_VFVMBMEM(_n) (0x00800 + (_n)) 564 #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) 565 /* VLAN Virtual Machine Filter - RW */ 566 #define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) 567 #define E1000_VMVIR(_n) (0x03700 + (4 * (_n))) 568 #define E1000_DVMOLR(_n) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */ 569 #define E1000_VTCTRL(_n) (0x10000 + (0x100 * (_n))) /* VT Control */ 570 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 571 #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 572 #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ 573 #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 574 #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 575 #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ 576 #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ 577 #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 578 #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 579 #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 580 #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 581 #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ 582 #define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */ 583 #define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */ 584 #define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ 585 #define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */ 586 #define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */ 587 #define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */ 588 #define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */ 589 #define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */ 590 #define E1000_TSICR 0x0B66C /* Interrupt Cause Register */ 591 #define E1000_TSIM 0x0B674 /* Interrupt Mask Register */ 592 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 593 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 594 595 /* Filtering Registers */ 596 #define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ 597 #define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ 598 #define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ 599 #define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ 600 #define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */ 601 #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ 602 #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ 603 604 /* ETQF register bit definitions */ 605 #define E1000_ETQF_FILTER_ENABLE (1 << 26) 606 #define E1000_ETQF_IMM_INT (1 << 29) 607 #define E1000_ETQF_QUEUE_ENABLE (1 << 31) 608 #define E1000_ETQF_QUEUE_SHIFT 16 609 #define E1000_ETQF_QUEUE_MASK 0x00070000 610 #define E1000_ETQF_ETYPE_MASK 0x0000FFFF 611 612 #define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */ 613 #define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */ 614 #define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */ 615 #define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */ 616 #define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ 617 /* Tx Desc plane TC Rate-scheduler config */ 618 #define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) 619 /* Tx Packet plane TC Rate-Scheduler Config */ 620 #define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) 621 /* Rx Packet plane TC Rate-Scheduler Config */ 622 #define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) 623 /* Tx Desc Plane TC Rate-Scheduler Status */ 624 #define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) 625 /* Tx Desc Plane TC Rate-Scheduler MMW */ 626 #define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) 627 /* Tx Packet plane TC Rate-Scheduler Status */ 628 #define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) 629 /* Tx Packet plane TC Rate-scheduler MMW */ 630 #define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) 631 /* Rx Packet plane TC Rate-Scheduler Status */ 632 #define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) 633 /* Rx Packet plane TC Rate-Scheduler MMW */ 634 #define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) 635 /* Tx Desc plane VM Rate-Scheduler MMW*/ 636 #define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) 637 /* Tx BCN Rate-Scheduler MMW */ 638 #define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) 639 #define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */ 640 #define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */ 641 #define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */ 642 #define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */ 643 #define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */ 644 #define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */ 645 #define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */ 646 #define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */ 647 #define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */ 648 #define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */ 649 #define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */ 650 #define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */ 651 #define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */ 652 #define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */ 653 654 /* DMA Coalescing registers */ 655 #define E1000_DMACR 0x02508 /* Control Register */ 656 #define E1000_DMCTXTH 0x03550 /* Transmit Threshold */ 657 #define E1000_DMCTLX 0x02514 /* Time to Lx Request */ 658 #define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ 659 #define E1000_DMCCNT 0x05DD4 /* Current Rx Count */ 660 #define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */ 661 #define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ 662 663 /* PCIe Parity Status Register */ 664 #define E1000_PCIEERRSTS 0x05BA8 665 666 #define E1000_PROXYS 0x5F64 /* Proxying Status */ 667 #define E1000_PROXYFC 0x5F60 /* Proxying Filter Control */ 668 /* Thermal sensor configuration and status registers */ 669 #define E1000_THMJT 0x08100 /* Junction Temperature */ 670 #define E1000_THLOWTC 0x08104 /* Low Threshold Control */ 671 #define E1000_THMIDTC 0x08108 /* Mid Threshold Control */ 672 #define E1000_THHIGHTC 0x0810C /* High Threshold Control */ 673 #define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ 674 675 /* Energy Efficient Ethernet "EEE" registers */ 676 #define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ 677 #define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ 678 #define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/ 679 #define E1000_EEE_SU 0x0E34 /* EEE Setup */ 680 #define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */ 681 #define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */ 682 683 /* OS2BMC Registers */ 684 #define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ 685 #define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */ 686 #define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ 687 #define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ 688 689 690 691 #endif 692