1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _E1000_82575_H_ 6 #define _E1000_82575_H_ 7 8 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 9 (ID_LED_DEF1_DEF2 << 8) | \ 10 (ID_LED_DEF1_DEF2 << 4) | \ 11 (ID_LED_OFF1_ON2)) 12 /* 13 * Receive Address Register Count 14 * Number of high/low register pairs in the RAR. The RAR (Receive Address 15 * Registers) holds the directed and multicast addresses that we monitor. 16 * These entries are also used for MAC-based filtering. 17 */ 18 /* 19 * For 82576, there are an additional set of RARs that begin at an offset 20 * separate from the first set of RARs. 21 */ 22 #define E1000_RAR_ENTRIES_82575 16 23 #define E1000_RAR_ENTRIES_82576 24 24 #define E1000_RAR_ENTRIES_82580 24 25 #define E1000_RAR_ENTRIES_I350 32 26 #define E1000_SW_SYNCH_MB 0x00000100 27 #define E1000_STAT_DEV_RST_SET 0x00100000 28 29 struct e1000_adv_data_desc { 30 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 31 union { 32 u32 data; 33 struct { 34 u32 datalen:16; /* Data buffer length */ 35 u32 rsvd:4; 36 u32 dtyp:4; /* Descriptor type */ 37 u32 dcmd:8; /* Descriptor command */ 38 } config; 39 } lower; 40 union { 41 u32 data; 42 struct { 43 u32 status:4; /* Descriptor status */ 44 u32 idx:4; 45 u32 popts:6; /* Packet Options */ 46 u32 paylen:18; /* Payload length */ 47 } options; 48 } upper; 49 }; 50 51 #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */ 52 #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */ 53 #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */ 54 #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */ 55 #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */ 56 #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */ 57 #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */ 58 #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */ 59 #define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */ 60 #define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */ 61 #define E1000_ADV_DCMD_RS 0x8 /* Report Status */ 62 #define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */ 63 #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */ 64 /* Extended Device Control */ 65 #define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */ 66 67 struct e1000_adv_context_desc { 68 union { 69 u32 ip_config; 70 struct { 71 u32 iplen:9; 72 u32 maclen:7; 73 u32 vlan_tag:16; 74 } fields; 75 } ip_setup; 76 u32 seq_num; 77 union { 78 u64 l4_config; 79 struct { 80 u32 mkrloc:9; 81 u32 tucmd:11; 82 u32 dtyp:4; 83 u32 adv:8; 84 u32 rsvd:4; 85 u32 idx:4; 86 u32 l4len:8; 87 u32 mss:16; 88 } fields; 89 } l4_setup; 90 }; 91 92 /* SRRCTL bit definitions */ 93 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 94 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 95 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 96 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 97 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 98 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 99 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 100 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 101 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 102 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 103 #define E1000_SRRCTL_TIMESTAMP 0x40000000 104 #define E1000_SRRCTL_DROP_EN 0x80000000 105 106 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 107 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 108 109 #define E1000_TX_HEAD_WB_ENABLE 0x1 110 #define E1000_TX_SEQNUM_WB_ENABLE 0x2 111 112 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 113 #define E1000_MRQC_ENABLE_VMDQ 0x00000003 114 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 115 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 116 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 117 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 118 #define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 119 120 #define E1000_VMRCTL_MIRROR_PORT_SHIFT 8 121 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << \ 122 E1000_VMRCTL_MIRROR_PORT_SHIFT) 123 #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) 124 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1) 125 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2) 126 127 #define E1000_EICR_TX_QUEUE ( \ 128 E1000_EICR_TX_QUEUE0 | \ 129 E1000_EICR_TX_QUEUE1 | \ 130 E1000_EICR_TX_QUEUE2 | \ 131 E1000_EICR_TX_QUEUE3) 132 133 #define E1000_EICR_RX_QUEUE ( \ 134 E1000_EICR_RX_QUEUE0 | \ 135 E1000_EICR_RX_QUEUE1 | \ 136 E1000_EICR_RX_QUEUE2 | \ 137 E1000_EICR_RX_QUEUE3) 138 139 #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE 140 #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE 141 142 #define EIMS_ENABLE_MASK ( \ 143 E1000_EIMS_RX_QUEUE | \ 144 E1000_EIMS_TX_QUEUE | \ 145 E1000_EIMS_TCP_TIMER | \ 146 E1000_EIMS_OTHER) 147 148 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 149 #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 150 #define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 151 #define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 152 #define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 153 #define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 154 #define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 155 #define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 156 #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 157 158 #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F 159 #define E1000_RXDADV_RSSTYPE_SHIFT 12 160 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 161 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 162 #define E1000_RXDADV_SPLITHEADER_EN 0x00001000 163 #define E1000_RXDADV_SPH 0x8000 164 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 165 #define E1000_RXDADV_ERR_HBO 0x00800000 166 167 /* RSS Hash results */ 168 #define E1000_RXDADV_RSSTYPE_NONE 0x00000000 169 #define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 170 #define E1000_RXDADV_RSSTYPE_IPV4 0x00000002 171 #define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 172 #define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 173 #define E1000_RXDADV_RSSTYPE_IPV6 0x00000005 174 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 175 #define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 176 #define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 177 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 178 179 /* RSS Packet Types as indicated in the receive descriptor */ 180 #define E1000_RXDADV_PKTTYPE_ILMASK 0x000000F0 181 #define E1000_RXDADV_PKTTYPE_TLMASK 0x00000F00 182 #define E1000_RXDADV_PKTTYPE_NONE 0x00000000 183 #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 184 #define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 185 #define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 186 #define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 187 #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 188 #define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 189 #define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 190 #define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 191 192 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 193 #define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 194 #define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 195 #define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 196 #define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 197 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 198 199 /* LinkSec results */ 200 /* Security Processing bit Indication */ 201 #define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 202 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 203 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 204 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 205 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 206 207 #define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 208 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 209 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 210 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 211 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 212 213 /* Adv Transmit Descriptor Config Masks */ 214 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 215 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 216 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 217 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 218 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 219 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 220 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 221 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 222 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 223 #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ 224 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ 225 #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ 226 #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 227 #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 228 #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 229 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 230 /* 1st & Last TSO-full iSCSI PDU*/ 231 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 232 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 233 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 234 235 /* Additional Transmit Descriptor Control definitions */ 236 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 237 #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ 238 /* Tx Queue Arbitration Priority 0=low, 1=high */ 239 #define E1000_TXDCTL_PRIORITY 0x08000000 240 241 /* Additional Receive Descriptor Control definitions */ 242 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 243 #define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ 244 245 /* Direct Cache Access (DCA) definitions */ 246 #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 247 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 248 249 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 250 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 251 252 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 253 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 254 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ 255 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ 256 #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ 257 258 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 259 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 260 #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 261 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 262 #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 263 264 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 265 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 266 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */ 267 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */ 268 269 /* Additional interrupt register bit definitions */ 270 #define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */ 271 #define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 272 #define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */ 273 274 /* 275 * ETQF filter list: one static filter per filter consumer. This is 276 * to avoid filter collisions later. Add new filters 277 * here!! 278 * 279 * Current filters: 280 * EAPOL 802.1x (0x888e): Filter 0 281 */ 282 #define E1000_ETQF_FILTER_EAPOL 0 283 284 #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 285 #define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 286 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 287 288 #define E1000_NVM_APME_82575 0x0400 289 #define MAX_NUM_VFS 7 290 291 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */ 292 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */ 293 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 294 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 295 #define E1000_DTXSWC_LLE_SHIFT 16 296 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */ 297 298 /* Easy defines for setting default pool, would normally be left a zero */ 299 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 300 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 301 302 /* Other useful VMD_CTL register defines */ 303 #define E1000_VT_CTL_IGNORE_MAC (1 << 28) 304 #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 305 #define E1000_VT_CTL_VM_REPL_EN (1 << 30) 306 307 /* Per VM Offload register setup */ 308 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 309 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 310 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 311 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 312 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 313 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 314 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 315 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 316 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 317 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 318 319 #define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */ 320 #define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */ 321 #define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */ 322 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 323 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 324 325 #define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */ 326 #define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */ 327 328 #define E1000_VLVF_ARRAY_SIZE 32 329 #define E1000_VLVF_VLANID_MASK 0x00000FFF 330 #define E1000_VLVF_POOLSEL_SHIFT 12 331 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 332 #define E1000_VLVF_LVLAN 0x00100000 333 #define E1000_VLVF_VLANID_ENABLE 0x80000000 334 335 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 336 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 337 338 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 339 340 #define E1000_IOVCTL 0x05BBC 341 #define E1000_IOVCTL_REUSE_VFQ 0x00000001 342 343 #define E1000_RPLOLR_STRVLAN 0x40000000 344 #define E1000_RPLOLR_STRCRC 0x80000000 345 346 #define E1000_TCTL_EXT_COLD 0x000FFC00 347 #define E1000_TCTL_EXT_COLD_SHIFT 10 348 349 #define E1000_DTXCTL_8023LL 0x0004 350 #define E1000_DTXCTL_VLAN_ADDED 0x0008 351 #define E1000_DTXCTL_OOS_ENABLE 0x0010 352 #define E1000_DTXCTL_MDP_EN 0x0020 353 #define E1000_DTXCTL_SPOOF_INT 0x0040 354 355 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) 356 357 #define ALL_QUEUES 0xFFFF 358 359 s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 360 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 361 362 /* Rx packet buffer size defines */ 363 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F 364 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); 365 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf); 366 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); 367 368 enum e1000_promisc_type { 369 e1000_promisc_disabled = 0, /* all promisc modes disabled */ 370 e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 371 e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 372 e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 373 e1000_num_promisc_types 374 }; 375 376 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool); 377 void e1000_rlpml_set_vf(struct e1000_hw *, u16); 378 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type); 379 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 380 u16 e1000_rxpbs_adjust_82580(u32 data); 381 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data); 382 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M); 383 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M); 384 s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *); 385 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw); 386 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw); 387 388 /* I2C SDA and SCL timing parameters for standard mode */ 389 #define E1000_I2C_T_HD_STA 4 390 #define E1000_I2C_T_LOW 5 391 #define E1000_I2C_T_HIGH 4 392 #define E1000_I2C_T_SU_STA 5 393 #define E1000_I2C_T_HD_DATA 5 394 #define E1000_I2C_T_SU_DATA 1 395 #define E1000_I2C_T_RISE 1 396 #define E1000_I2C_T_FALL 1 397 #define E1000_I2C_T_SU_STO 4 398 #define E1000_I2C_T_BUF 5 399 400 s32 e1000_set_i2c_bb(struct e1000_hw *hw); 401 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 402 u8 dev_addr, u8 *data); 403 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 404 u8 dev_addr, u8 data); 405 void e1000_i2c_bus_clear(struct e1000_hw *hw); 406 #endif /* _E1000_82575_H_ */ 407