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/f-stack/freebsd/contrib/device-tree/Bindings/display/
H A Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
39 DSI peripheral
72 Peripherals that support dual channel DSI
80 an input endpoint of the DSI peripheral.
87 - (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
90 DSI host using of-graph bindings.
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H A Dbrcm,bcm2835-dsi0.yaml7 title: Broadcom VC4 (VideoCore4) DSI Controller
26 - description: The DSI PLL clock feeding the DSI analog PHY
27 - description: The DSI ESC clock
28 - description: The DSI pixel clock
39 # - description: The DSI byte clock for the PHY
40 # - description: The DSI DDR2 clock
41 # - description: The DSI DDR clock
H A Dtruly,nt35597.txt1 Truly model NT35597 DSI display driver
18 for single DSI or Dual DSI
19 This should be low for dual DSI and high for single DSI mode
23 - port@0: DSI input port driven by master DSI
24 - port@1: DSI input port driven by secondary DSI
H A Ddsi-controller.yaml7 title: Common Properties for DSI Display Panels
13 This document defines device tree properties common to DSI, Display
22 Notice: this binding concerns DSI panels connected directly to a master
23 without any intermediate port graph to the panel. Each DSI master
41 description: Panels connected to the DSI link
49 The virtual channel number of a DSI peripheral. Must be in the range
50 from 0 to 3, as DSI uses a 2-bit addressing scheme. Some DSI
59 another DSI host to drive the same peripheral. Hardware supporting
61 to be driven by the same clock. Only the DSI host instance
H A Dst,stm32-dsi.yaml7 title: STMicroelectronics STM32 DSI host controller
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
26 - description: DSI bus clock
53 A node containing DSI input & output port nodes with endpoint
61 DSI input port node, connected to the ltdc rgb output port.
66 DSI output port node, connected to a panel or a bridge input port"
78 Panel or bridge port node, connected to the DSI output port (port@1)
H A Dste,mcde.txt4 and displaying several channels memory resident graphics data on DSI or
24 - #address-cells: should be <1> (for the DSI hosts that will be children)
25 - #size-cells: should be <1> (for the DSI hosts that will be children)
30 The devicetree must specify subnodes for the DSI host adapters.
35 - reg: must specify the register range for the DSI host
45 Display panels and bridges will appear as children on the DSI hosts, and
46 the displays are connected to the DSI hosts using the common binding
50 If a DSI host is unused (not connected) it will have no children defined.
98 /* This DSI port only has the Low Power / Energy Save clock */
/f-stack/freebsd/contrib/device-tree/Bindings/display/panel/
H A Dsharp,lq101r1sx01.txt3 This panel requires a dual-channel DSI host to operate. It supports two modes:
7 Each of the DSI channels controls a separate DSI peripheral. The peripheral
8 driven by the first link (DSI-LINK1), left or even, is considered the primary
10 to the peripheral driven by the second link (DSI-LINK2, right or odd).
12 Note that in video mode the DSI-LINK1 interface always provides the left/even
13 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
20 - reg: DSI virtual channel of the peripheral
22 Required properties (for DSI-LINK1 only):
23 - link2: phandle to the DSI peripheral on the secondary link. Note that the
24 presence of this property marks the containing node as DSI-LINK1.
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H A Dsharp,lq101r1sx01.yaml13 This panel requires a dual-channel DSI host to operate. It supports two modes:
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
22 Note that in video mode the DSI-LINK1 interface always provides the left/even
23 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
42 phandle to the DSI peripheral on the secondary link. Note that the
43 presence of this property marks the containing node as DSI-LINK1
H A Dorisetech,otm8009a.yaml7 title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
14 a MIPI-DSI video interface. Its backlight is managed through the DSI link.
25 description: DSI virtual channel
H A Draspberrypi,7inch-touchscreen.yaml14 This DSI panel contains:
16 - TC358762 DSI->DPI bridge
17 - Atmel microcontroller on I2C for power sequencing the DSI bridge and
21 and this binding covers the DSI display parts but not its touch input.
H A Draydium,rm68200.yaml7 title: Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
14 panel connected using a MIPI-DSI video interface.
26 description: DSI virtual channel
H A Dpanel-dsi-cm.yaml7 title: DSI command mode panels
14 This binding file is a collection of the DSI panels that
16 referenced via the optional backlight property, the DSI
33 - const: panel-dsi-cm # Generic DSI command mode panel compatible fallback
37 description: DSI virtual channel
/f-stack/freebsd/contrib/device-tree/Bindings/display/bridge/
H A Dcdns,dsi.txt1 Cadence DSI bridge
4 The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
9 - interrupts: interrupt line connected to the DSI bridge.
10 - clocks: DSI bridge clocks.
18 - resets: DSI reset lines.
24 * port 0: this port is only needed if some of your DSI devices are
27 DSI virtual channel used by this device.
31 - one subnode per DSI device connected on the DSI bus. Each DSI device should
H A Dtoshiba,tc358764.txt1 TC358764 MIPI-DSI to LVDS panel bridge
5 - reg: the virtual channel number of a DSI peripheral
13 0: DSI Input, not required, if the bridge is DSI controlled
H A Dsnps,dw-mipi-dsi.yaml7 title: Synopsys DesignWare MIPI DSI host controller
14 DSI host controller. It doesn't constitue a device tree binding specification
32 - description: DSI bus clock for either AHB and APB
58 description: DSI output node to panel.
H A Dnwl-dsi.yaml7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
35 - description: DSI core clock
82 A node containing DSI input & output port nodes with endpoint
126 DSI output port node to the panel or the next bridge
/f-stack/freebsd/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_dsim.txt1 Exynos MIPI DSI Master
11 - interrupts: should contain DSI interrupt
23 according to DSI host bindings (see MIPI DSI bindings [1])
24 - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
26 - samsung,esc-clock-frequency: specifies DSI frequency in escape mode
32 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
37 1: DSI output
/f-stack/freebsd/contrib/device-tree/Bindings/display/msm/
H A Ddsi.txt1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
10 - interrupts: The interrupt signal from the DSI block.
31 - phys: phandle to DSI PHY device node
38 - panel@0: Node of panel connected to this DSI controller.
41 driving a panel which needs 2 DSI links.
43 the master link of the 2-DSI panel.
52 DSI Endpoint properties:
82 DSI PHY:
97 For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/display/ti/
H A Dti,omap5-dss.txt21 - DSS Submodules: RFBI, DSI, HDMI
59 DSI
66 - interrupts: the DSI interrupt line
68 - vdd-supply: power supply for DSI
73 - Video port for DSI output
74 - DSI controlled peripherals
76 DSI Endpoint required properties:
77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
H A Dti,omap4-dss.txt21 - DSS Submodules: RFBI, VENC, DSI, HDMI
78 DSI
85 - interrupts: the DSI interrupt line
87 - vdd-supply: power supply for DSI
92 - Video port for DSI output
93 - DSI controlled peripherals
95 DSI Endpoint required properties:
96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
H A Dti,omap3-dss.txt72 DSI
79 - interrupts: the DSI interrupt line
81 - vdd-supply: power supply for DSI
85 DSI Endpoint required properties:
86 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
/f-stack/freebsd/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dsi.txt1 Mediatek DSI Device
4 The Mediatek DSI function block is a sink of the display subsystem and can
5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
20 to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
32 - clock-output-names: name of the output clock line to the DSI encoder
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dmixel,mipi-dsi-phy.txt1 Mixel DSI PHY for i.MX8
3 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
4 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
5 electrical signals for DSI.
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dqcom,mmcc.yaml33 - description: DSI phy instance 0 dsi clock
34 - description: DSI phy instance 0 byte clock
35 - description: DSI phy instance 1 dsi clock
36 - description: DSI phy instance 1 byte clock
H A Dqcom,sdm845-dispcc.yaml30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1

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