1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * 3 * Copyright 2013-2016 Freescale Semiconductor Inc. 4 * Copyright 2016-2019 NXP 5 * 6 */ 7 #ifndef _FSL_DPNI_CMD_H 8 #define _FSL_DPNI_CMD_H 9 10 /* DPNI Version */ 11 #define DPNI_VER_MAJOR 7 12 #define DPNI_VER_MINOR 13 13 14 #define DPNI_CMD_BASE_VERSION 1 15 #define DPNI_CMD_VERSION_2 2 16 #define DPNI_CMD_VERSION_3 3 17 #define DPNI_CMD_ID_OFFSET 4 18 19 #define DPNI_CMD(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION) 20 #define DPNI_CMD_V2(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_2) 21 #define DPNI_CMD_V3(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_3) 22 23 /* Command IDs */ 24 #define DPNI_CMDID_OPEN DPNI_CMD(0x801) 25 #define DPNI_CMDID_CLOSE DPNI_CMD(0x800) 26 #define DPNI_CMDID_CREATE DPNI_CMD_V3(0x901) 27 #define DPNI_CMDID_DESTROY DPNI_CMD(0x981) 28 #define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01) 29 30 #define DPNI_CMDID_ENABLE DPNI_CMD(0x002) 31 #define DPNI_CMDID_DISABLE DPNI_CMD(0x003) 32 #define DPNI_CMDID_GET_ATTR DPNI_CMD_V3(0x004) 33 #define DPNI_CMDID_RESET DPNI_CMD(0x005) 34 #define DPNI_CMDID_IS_ENABLED DPNI_CMD(0x006) 35 36 #define DPNI_CMDID_SET_IRQ_ENABLE DPNI_CMD(0x012) 37 #define DPNI_CMDID_GET_IRQ_ENABLE DPNI_CMD(0x013) 38 #define DPNI_CMDID_SET_IRQ_MASK DPNI_CMD(0x014) 39 #define DPNI_CMDID_GET_IRQ_MASK DPNI_CMD(0x015) 40 #define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016) 41 #define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017) 42 43 #define DPNI_CMDID_SET_POOLS DPNI_CMD_V3(0x200) 44 #define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B) 45 46 #define DPNI_CMDID_GET_QDID DPNI_CMD(0x210) 47 #define DPNI_CMDID_GET_SP_INFO DPNI_CMD(0x211) 48 #define DPNI_CMDID_GET_TX_DATA_OFFSET DPNI_CMD(0x212) 49 #define DPNI_CMDID_GET_LINK_STATE DPNI_CMD_V2(0x215) 50 #define DPNI_CMDID_SET_MAX_FRAME_LENGTH DPNI_CMD(0x216) 51 #define DPNI_CMDID_GET_MAX_FRAME_LENGTH DPNI_CMD(0x217) 52 #define DPNI_CMDID_SET_LINK_CFG DPNI_CMD_V2(0x21A) 53 #define DPNI_CMDID_SET_TX_SHAPING DPNI_CMD_V2(0x21B) 54 55 #define DPNI_CMDID_SET_MCAST_PROMISC DPNI_CMD(0x220) 56 #define DPNI_CMDID_GET_MCAST_PROMISC DPNI_CMD(0x221) 57 #define DPNI_CMDID_SET_UNICAST_PROMISC DPNI_CMD(0x222) 58 #define DPNI_CMDID_GET_UNICAST_PROMISC DPNI_CMD(0x223) 59 #define DPNI_CMDID_SET_PRIM_MAC DPNI_CMD(0x224) 60 #define DPNI_CMDID_GET_PRIM_MAC DPNI_CMD(0x225) 61 #define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD_V2(0x226) 62 #define DPNI_CMDID_REMOVE_MAC_ADDR DPNI_CMD(0x227) 63 #define DPNI_CMDID_CLR_MAC_FILTERS DPNI_CMD(0x228) 64 65 #define DPNI_CMDID_ENABLE_VLAN_FILTER DPNI_CMD(0x230) 66 #define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD_V2(0x231) 67 #define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232) 68 #define DPNI_CMDID_CLR_VLAN_FILTERS DPNI_CMD(0x233) 69 70 #define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD_V3(0x235) 71 72 #define DPNI_CMDID_SET_QOS_TBL DPNI_CMD_V2(0x240) 73 #define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD_V2(0x241) 74 #define DPNI_CMDID_REMOVE_QOS_ENT DPNI_CMD(0x242) 75 #define DPNI_CMDID_CLR_QOS_TBL DPNI_CMD(0x243) 76 #define DPNI_CMDID_ADD_FS_ENT DPNI_CMD(0x244) 77 #define DPNI_CMDID_REMOVE_FS_ENT DPNI_CMD(0x245) 78 #define DPNI_CMDID_CLR_FS_ENT DPNI_CMD(0x246) 79 80 #define DPNI_CMDID_GET_STATISTICS DPNI_CMD_V3(0x25D) 81 #define DPNI_CMDID_RESET_STATISTICS DPNI_CMD(0x25E) 82 #define DPNI_CMDID_GET_QUEUE DPNI_CMD_V2(0x25F) 83 #define DPNI_CMDID_SET_QUEUE DPNI_CMD_V2(0x260) 84 #define DPNI_CMDID_GET_TAILDROP DPNI_CMD_V2(0x261) 85 #define DPNI_CMDID_SET_TAILDROP DPNI_CMD_V2(0x262) 86 87 #define DPNI_CMDID_GET_PORT_MAC_ADDR DPNI_CMD(0x263) 88 89 #define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD_V2(0x264) 90 #define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD_V2(0x265) 91 92 #define DPNI_CMDID_SET_CONGESTION_NOTIFICATION DPNI_CMD_V2(0x267) 93 #define DPNI_CMDID_GET_CONGESTION_NOTIFICATION DPNI_CMD_V2(0x268) 94 #define DPNI_CMDID_SET_EARLY_DROP DPNI_CMD_V2(0x269) 95 #define DPNI_CMDID_GET_EARLY_DROP DPNI_CMD_V2(0x26A) 96 #define DPNI_CMDID_GET_OFFLOAD DPNI_CMD(0x26B) 97 #define DPNI_CMDID_SET_OFFLOAD DPNI_CMD(0x26C) 98 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266) 99 #define DPNI_CMDID_GET_TX_CONFIRMATION_MODE DPNI_CMD(0x26D) 100 #define DPNI_CMDID_LOAD_SW_SEQUENCE DPNI_CMD(0x270) 101 #define DPNI_CMDID_ENABLE_SW_SEQUENCE DPNI_CMD(0x271) 102 #define DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT DPNI_CMD(0x272) 103 #define DPNI_CMDID_SET_OPR DPNI_CMD(0x26e) 104 #define DPNI_CMDID_GET_OPR DPNI_CMD(0x26f) 105 #define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD(0x273) 106 #define DPNI_CMDID_SET_RX_HASH_DIST DPNI_CMD(0x274) 107 #define DPNI_CMDID_ADD_CUSTOM_TPID DPNI_CMD(0x275) 108 #define DPNI_CMDID_REMOVE_CUSTOM_TPID DPNI_CMD(0x276) 109 #define DPNI_CMDID_GET_CUSTOM_TPID DPNI_CMD(0x277) 110 111 /* Macros for accessing command fields smaller than 1byte */ 112 #define DPNI_MASK(field) \ 113 GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \ 114 DPNI_##field##_SHIFT) 115 #define dpni_set_field(var, field, val) \ 116 ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field))) 117 #define dpni_get_field(var, field) \ 118 (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT) 119 120 #pragma pack(push, 1) 121 struct dpni_cmd_open { 122 uint32_t dpni_id; 123 }; 124 125 struct dpni_cmd_create { 126 uint32_t options; 127 uint8_t num_queues; 128 uint8_t num_tcs; 129 uint8_t mac_filter_entries; 130 uint8_t pad1; 131 uint8_t vlan_filter_entries; 132 uint8_t pad2; 133 uint8_t qos_entries; 134 uint8_t pad3; 135 uint16_t fs_entries; 136 uint8_t num_rx_tcs; 137 uint8_t pad4; 138 uint8_t num_cgs; 139 }; 140 141 struct dpni_cmd_destroy { 142 uint32_t dpsw_id; 143 }; 144 145 #define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) 146 147 struct dpni_cmd_pool { 148 uint16_t dpbp_id; 149 uint8_t priority_mask; 150 uint8_t pad; 151 }; 152 153 struct dpni_cmd_set_pools { 154 uint8_t num_dpbp; 155 uint8_t backup_pool_mask; 156 uint8_t pad; 157 uint8_t pool_options; 158 struct dpni_cmd_pool pool[8]; 159 uint16_t buffer_size[8]; 160 }; 161 162 /* The enable indication is always the least significant bit */ 163 #define DPNI_ENABLE_SHIFT 0 164 #define DPNI_ENABLE_SIZE 1 165 166 struct dpni_rsp_is_enabled { 167 uint8_t enabled; 168 }; 169 170 struct dpni_cmd_set_irq_enable { 171 uint8_t enable; 172 uint8_t pad[3]; 173 uint8_t irq_index; 174 }; 175 176 struct dpni_cmd_get_irq_enable { 177 uint32_t pad; 178 uint8_t irq_index; 179 }; 180 181 struct dpni_rsp_get_irq_enable { 182 uint8_t enabled; 183 }; 184 185 struct dpni_cmd_set_irq_mask { 186 uint32_t mask; 187 uint8_t irq_index; 188 }; 189 190 struct dpni_cmd_get_irq_mask { 191 uint32_t pad; 192 uint8_t irq_index; 193 }; 194 195 struct dpni_rsp_get_irq_mask { 196 uint32_t mask; 197 }; 198 199 struct dpni_cmd_get_irq_status { 200 uint32_t status; 201 uint8_t irq_index; 202 }; 203 204 struct dpni_rsp_get_irq_status { 205 uint32_t status; 206 }; 207 208 struct dpni_cmd_clear_irq_status { 209 uint32_t status; 210 uint8_t irq_index; 211 }; 212 213 struct dpni_rsp_get_attr { 214 /* response word 0 */ 215 uint32_t options; 216 uint8_t num_queues; 217 uint8_t num_rx_tcs; 218 uint8_t mac_filter_entries; 219 uint8_t num_tx_tcs; 220 /* response word 1 */ 221 uint8_t vlan_filter_entries; 222 uint8_t pad1; 223 uint8_t qos_entries; 224 uint8_t pad2; 225 uint16_t fs_entries; 226 uint16_t pad3; 227 /* response word 2 */ 228 uint8_t qos_key_size; 229 uint8_t fs_key_size; 230 uint16_t wriop_version; 231 uint8_t num_cgs; 232 }; 233 234 #define DPNI_ERROR_ACTION_SHIFT 0 235 #define DPNI_ERROR_ACTION_SIZE 4 236 #define DPNI_FRAME_ANN_SHIFT 4 237 #define DPNI_FRAME_ANN_SIZE 1 238 239 struct dpni_cmd_set_errors_behavior { 240 uint32_t errors; 241 /* from least significant bit: error_action:4, set_frame_annotation:1 */ 242 uint8_t flags; 243 }; 244 245 /* There are 3 separate commands for configuring Rx, Tx and Tx confirmation 246 * buffer layouts, but they all share the same parameters. 247 * If one of the functions changes, below structure needs to be split. 248 */ 249 250 #define DPNI_PASS_TS_SHIFT 0 251 #define DPNI_PASS_TS_SIZE 1 252 #define DPNI_PASS_PR_SHIFT 1 253 #define DPNI_PASS_PR_SIZE 1 254 #define DPNI_PASS_FS_SHIFT 2 255 #define DPNI_PASS_FS_SIZE 1 256 #define DPNI_PASS_SWO_SHIFT 3 257 #define DPNI_PASS_SWO_SIZE 1 258 259 struct dpni_cmd_get_buffer_layout { 260 uint8_t qtype; 261 }; 262 263 struct dpni_rsp_get_buffer_layout { 264 /* response word 0 */ 265 uint8_t pad0[6]; 266 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ 267 uint8_t flags; 268 uint8_t pad1; 269 /* response word 1 */ 270 uint16_t private_data_size; 271 uint16_t data_align; 272 uint16_t head_room; 273 uint16_t tail_room; 274 }; 275 276 struct dpni_cmd_set_buffer_layout { 277 /* cmd word 0 */ 278 uint8_t qtype; 279 uint8_t pad0[3]; 280 uint16_t options; 281 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ 282 uint8_t flags; 283 uint8_t pad1; 284 /* cmd word 1 */ 285 uint16_t private_data_size; 286 uint16_t data_align; 287 uint16_t head_room; 288 uint16_t tail_room; 289 }; 290 291 struct dpni_cmd_set_offload { 292 uint8_t pad[3]; 293 uint8_t dpni_offload; 294 uint32_t config; 295 }; 296 297 struct dpni_cmd_get_offload { 298 uint8_t pad[3]; 299 uint8_t dpni_offload; 300 }; 301 302 struct dpni_rsp_get_offload { 303 uint32_t pad; 304 uint32_t config; 305 }; 306 307 struct dpni_cmd_get_qdid { 308 uint8_t qtype; 309 }; 310 311 struct dpni_rsp_get_qdid { 312 uint16_t qdid; 313 }; 314 315 struct dpni_rsp_get_sp_info { 316 uint16_t spids[2]; 317 }; 318 319 struct dpni_rsp_get_tx_data_offset { 320 uint16_t data_offset; 321 }; 322 323 struct dpni_cmd_get_statistics { 324 uint8_t page_number; 325 uint16_t param; 326 }; 327 328 struct dpni_rsp_get_statistics { 329 uint64_t counter[7]; 330 }; 331 332 struct dpni_cmd_set_link_cfg { 333 uint64_t pad0; 334 uint32_t rate; 335 uint32_t pad1; 336 uint64_t options; 337 uint64_t advertising; 338 }; 339 340 #define DPNI_LINK_STATE_SHIFT 0 341 #define DPNI_LINK_STATE_SIZE 1 342 #define DPNI_STATE_VALID_SHIFT 1 343 #define DPNI_STATE_VALID_SIZE 1 344 345 struct dpni_rsp_get_link_state { 346 uint32_t pad0; 347 /* from LSB: up:1 */ 348 uint8_t flags; 349 uint8_t pad1[3]; 350 uint32_t rate; 351 uint32_t pad2; 352 uint64_t options; 353 uint64_t supported; 354 uint64_t advertising; 355 }; 356 357 struct dpni_cmd_set_max_frame_length { 358 uint16_t max_frame_length; 359 }; 360 361 struct dpni_rsp_get_max_frame_length { 362 uint16_t max_frame_length; 363 }; 364 365 struct dpni_cmd_set_multicast_promisc { 366 uint8_t enable; 367 }; 368 369 struct dpni_rsp_get_multicast_promisc { 370 uint8_t enabled; 371 }; 372 373 struct dpni_cmd_set_unicast_promisc { 374 uint8_t enable; 375 }; 376 377 struct dpni_rsp_get_unicast_promisc { 378 uint8_t enabled; 379 }; 380 381 struct dpni_cmd_set_primary_mac_addr { 382 uint16_t pad; 383 uint8_t mac_addr[6]; 384 }; 385 386 struct dpni_rsp_get_primary_mac_addr { 387 uint16_t pad; 388 uint8_t mac_addr[6]; 389 }; 390 391 struct dpni_rsp_get_port_mac_addr { 392 uint16_t pad; 393 uint8_t mac_addr[6]; 394 }; 395 396 #define DPNI_MAC_SET_QUEUE_ACTION 1 397 398 struct dpni_cmd_add_mac_addr { 399 uint8_t flags; 400 uint8_t pad; 401 uint8_t mac_addr[6]; 402 uint8_t tc_id; 403 uint8_t fq_id; 404 }; 405 406 struct dpni_cmd_remove_mac_addr { 407 uint16_t pad; 408 uint8_t mac_addr[6]; 409 }; 410 411 #define DPNI_UNICAST_FILTERS_SHIFT 0 412 #define DPNI_UNICAST_FILTERS_SIZE 1 413 #define DPNI_MULTICAST_FILTERS_SHIFT 1 414 #define DPNI_MULTICAST_FILTERS_SIZE 1 415 416 struct dpni_cmd_clear_mac_filters { 417 /* from LSB: unicast:1, multicast:1 */ 418 uint8_t flags; 419 }; 420 421 struct dpni_cmd_enable_vlan_filter { 422 /* only the LSB */ 423 uint8_t en; 424 }; 425 426 #define DPNI_VLAN_SET_QUEUE_ACTION 1 427 428 struct dpni_cmd_vlan_id { 429 uint8_t flags; 430 uint8_t tc_id; 431 uint8_t flow_id; 432 uint8_t pad; 433 uint16_t vlan_id; 434 }; 435 436 #define DPNI_SEPARATE_GRP_SHIFT 0 437 #define DPNI_SEPARATE_GRP_SIZE 1 438 #define DPNI_MODE_1_SHIFT 0 439 #define DPNI_MODE_1_SIZE 4 440 #define DPNI_MODE_2_SHIFT 4 441 #define DPNI_MODE_2_SIZE 4 442 443 struct dpni_cmd_set_tx_priorities { 444 uint16_t flags; 445 uint8_t prio_group_A; 446 uint8_t prio_group_B; 447 uint32_t pad0; 448 uint8_t modes[4]; 449 uint32_t pad1; 450 uint64_t pad2; 451 uint16_t delta_bandwidth[8]; 452 }; 453 454 #define DPNI_DIST_MODE_SHIFT 0 455 #define DPNI_DIST_MODE_SIZE 4 456 #define DPNI_MISS_ACTION_SHIFT 4 457 #define DPNI_MISS_ACTION_SIZE 4 458 #define DPNI_KEEP_HASH_KEY_SHIFT 7 459 #define DPNI_KEEP_HASH_KEY_SIZE 1 460 #define DPNI_KEEP_ENTRIES_SHIFT 6 461 #define DPNI_KEEP_ENTRIES_SIZE 1 462 463 struct dpni_cmd_set_rx_tc_dist { 464 uint16_t dist_size; 465 uint8_t tc_id; 466 /* from LSB: dist_mode:4, miss_action:4 */ 467 uint8_t flags; 468 uint8_t pad0; 469 /* only the LSB */ 470 uint8_t keep_hash_key; 471 uint16_t default_flow_id; 472 uint64_t pad1[5]; 473 uint64_t key_cfg_iova; 474 }; 475 476 struct dpni_cmd_get_queue { 477 uint8_t qtype; 478 uint8_t tc; 479 uint8_t index; 480 }; 481 482 #define DPNI_DEST_TYPE_SHIFT 0 483 #define DPNI_DEST_TYPE_SIZE 4 484 #define DPNI_CGID_VALID_SHIFT 5 485 #define DPNI_CGID_VALID_SIZE 1 486 #define DPNI_STASH_CTRL_SHIFT 6 487 #define DPNI_STASH_CTRL_SIZE 1 488 #define DPNI_HOLD_ACTIVE_SHIFT 7 489 #define DPNI_HOLD_ACTIVE_SIZE 1 490 491 struct dpni_rsp_get_queue { 492 /* response word 0 */ 493 uint64_t pad0; 494 /* response word 1 */ 495 uint32_t dest_id; 496 uint16_t pad1; 497 uint8_t dest_prio; 498 /* From LSB: 499 * dest_type:4, pad:1, cgid_valid:1, flc_stash_ctrl:1, hold_active:1 500 */ 501 uint8_t flags; 502 /* response word 2 */ 503 uint64_t flc; 504 /* response word 3 */ 505 uint64_t user_context; 506 /* response word 4 */ 507 uint32_t fqid; 508 uint16_t qdbin; 509 uint16_t pad2; 510 /* response word 5*/ 511 uint8_t cgid; 512 }; 513 514 struct dpni_cmd_set_queue { 515 /* cmd word 0 */ 516 uint8_t qtype; 517 uint8_t tc; 518 uint8_t index; 519 uint8_t options; 520 uint32_t pad0; 521 /* cmd word 1 */ 522 uint32_t dest_id; 523 uint16_t pad1; 524 uint8_t dest_prio; 525 uint8_t flags; 526 /* cmd word 2 */ 527 uint64_t flc; 528 /* cmd word 3 */ 529 uint64_t user_context; 530 /* cmd word 4 */ 531 uint8_t cgid; 532 }; 533 534 #define DPNI_DISCARD_ON_MISS_SHIFT 0 535 #define DPNI_DISCARD_ON_MISS_SIZE 1 536 #define DPNI_KEEP_QOS_ENTRIES_SHIFT 1 537 #define DPNI_KEEP_QOS_ENTRIES_SIZE 1 538 539 struct dpni_cmd_set_qos_table { 540 uint32_t pad; 541 uint8_t default_tc; 542 /* only the LSB */ 543 uint8_t discard_on_miss; 544 uint16_t pad1[21]; 545 uint64_t key_cfg_iova; 546 }; 547 548 #define DPNI_QOS_OPT_SET_TC_ONLY 0x0 549 #define DPNI_QOS_OPT_SET_FLOW_ID 0x1 550 551 struct dpni_cmd_add_qos_entry { 552 uint8_t flags; 553 uint8_t flow_id; 554 uint8_t tc_id; 555 uint8_t key_size; 556 uint16_t index; 557 uint16_t pad2; 558 uint64_t key_iova; 559 uint64_t mask_iova; 560 }; 561 562 struct dpni_cmd_remove_qos_entry { 563 uint8_t pad1[3]; 564 uint8_t key_size; 565 uint32_t pad2; 566 uint64_t key_iova; 567 uint64_t mask_iova; 568 }; 569 570 struct dpni_cmd_add_fs_entry { 571 uint16_t options; 572 uint8_t tc_id; 573 uint8_t key_size; 574 uint16_t index; 575 uint16_t flow_id; 576 uint64_t key_iova; 577 uint64_t mask_iova; 578 uint64_t flc; 579 }; 580 581 struct dpni_cmd_remove_fs_entry { 582 uint16_t pad1; 583 uint8_t tc_id; 584 uint8_t key_size; 585 uint32_t pad2; 586 uint64_t key_iova; 587 uint64_t mask_iova; 588 }; 589 590 struct dpni_cmd_clear_fs_entries { 591 uint16_t pad; 592 uint8_t tc_id; 593 }; 594 595 #define DPNI_DROP_ENABLE_SHIFT 0 596 #define DPNI_DROP_ENABLE_SIZE 1 597 #define DPNI_DROP_UNITS_SHIFT 2 598 #define DPNI_DROP_UNITS_SIZE 2 599 600 struct dpni_early_drop { 601 /* from LSB: enable:1 units:2 */ 602 uint8_t flags; 603 uint8_t pad0[3]; 604 uint32_t pad1; 605 uint8_t green_drop_probability; 606 uint8_t pad2[7]; 607 uint64_t green_max_threshold; 608 uint64_t green_min_threshold; 609 uint64_t pad3; 610 uint8_t yellow_drop_probability; 611 uint8_t pad4[7]; 612 uint64_t yellow_max_threshold; 613 uint64_t yellow_min_threshold; 614 uint64_t pad5; 615 uint8_t red_drop_probability; 616 uint8_t pad6[7]; 617 uint64_t red_max_threshold; 618 uint64_t red_min_threshold; 619 }; 620 621 struct dpni_cmd_early_drop { 622 uint8_t qtype; 623 uint8_t tc; 624 uint8_t pad[6]; 625 uint64_t early_drop_iova; 626 }; 627 628 struct dpni_rsp_get_api_version { 629 uint16_t major; 630 uint16_t minor; 631 }; 632 633 struct dpni_cmd_get_taildrop { 634 uint8_t congestion_point; 635 uint8_t qtype; 636 uint8_t tc; 637 uint8_t index; 638 }; 639 640 struct dpni_rsp_get_taildrop { 641 /* cmd word 0 */ 642 uint64_t pad0; 643 /* cmd word 1 */ 644 /* from LSB: enable:1 oal_lo:7 */ 645 uint8_t enable_oal_lo; 646 /* from LSB: oal_hi:5 */ 647 uint8_t oal_hi; 648 uint8_t units; 649 uint8_t pad2; 650 uint32_t threshold; 651 }; 652 653 #define DPNI_OAL_LO_SHIFT 1 654 #define DPNI_OAL_LO_SIZE 7 655 #define DPNI_OAL_HI_SHIFT 0 656 #define DPNI_OAL_HI_SIZE 5 657 658 struct dpni_cmd_set_taildrop { 659 /* cmd word 0 */ 660 uint8_t congestion_point; 661 uint8_t qtype; 662 uint8_t tc; 663 uint8_t index; 664 uint32_t pad0; 665 /* cmd word 1 */ 666 /* from LSB: enable:1 oal_lo:7 */ 667 uint8_t enable_oal_lo; 668 /* from LSB: oal_hi:5 */ 669 uint8_t oal_hi; 670 uint8_t units; 671 uint8_t pad2; 672 uint32_t threshold; 673 }; 674 675 struct dpni_tx_confirmation_mode { 676 uint32_t pad; 677 uint8_t confirmation_mode; 678 }; 679 680 #define DPNI_DEST_TYPE_SHIFT 0 681 #define DPNI_DEST_TYPE_SIZE 4 682 #define DPNI_CONG_UNITS_SHIFT 4 683 #define DPNI_CONG_UNITS_SIZE 2 684 685 struct dpni_cmd_set_congestion_notification { 686 uint8_t qtype; 687 uint8_t tc; 688 uint8_t pad; 689 uint8_t congestion_point; 690 uint8_t cgid; 691 uint8_t pad2[3]; 692 uint32_t dest_id; 693 uint16_t notification_mode; 694 uint8_t dest_priority; 695 /* from LSB: dest_type: 4 units:2 */ 696 uint8_t type_units; 697 uint64_t message_iova; 698 uint64_t message_ctx; 699 uint32_t threshold_entry; 700 uint32_t threshold_exit; 701 }; 702 703 struct dpni_cmd_get_congestion_notification { 704 uint8_t qtype; 705 uint8_t tc; 706 uint8_t pad; 707 uint8_t congestion_point; 708 uint8_t cgid; 709 }; 710 711 struct dpni_rsp_get_congestion_notification { 712 uint64_t pad; 713 uint32_t dest_id; 714 uint16_t notification_mode; 715 uint8_t dest_priority; 716 /* from LSB: dest_type: 4 units:2 */ 717 uint8_t type_units; 718 uint64_t message_iova; 719 uint64_t message_ctx; 720 uint32_t threshold_entry; 721 uint32_t threshold_exit; 722 }; 723 724 struct dpni_cmd_set_opr { 725 uint8_t pad0; 726 uint8_t tc_id; 727 uint8_t index; 728 uint8_t options; 729 uint8_t pad1[7]; 730 uint8_t oloe; 731 uint8_t oeane; 732 uint8_t olws; 733 uint8_t oa; 734 uint8_t oprrws; 735 }; 736 737 struct dpni_cmd_get_opr { 738 uint8_t pad; 739 uint8_t tc_id; 740 uint8_t index; 741 }; 742 743 #define DPNI_RIP_SHIFT 0 744 #define DPNI_RIP_SIZE 1 745 #define DPNI_OPR_ENABLE_SHIFT 1 746 #define DPNI_OPR_ENABLE_SIZE 1 747 #define DPNI_TSEQ_NLIS_SHIFT 0 748 #define DPNI_TSEQ_NLIS_SIZE 1 749 #define DPNI_HSEQ_NLIS_SHIFT 0 750 #define DPNI_HSEQ_NLIS_SIZE 1 751 752 struct dpni_rsp_get_opr { 753 uint64_t pad0; 754 /* from LSB: rip:1 enable:1 */ 755 uint8_t flags; 756 uint16_t pad1; 757 uint8_t oloe; 758 uint8_t oeane; 759 uint8_t olws; 760 uint8_t oa; 761 uint8_t oprrws; 762 uint16_t nesn; 763 uint16_t pad8; 764 uint16_t ndsn; 765 uint16_t pad2; 766 uint16_t ea_tseq; 767 /* only the LSB */ 768 uint8_t tseq_nlis; 769 uint8_t pad3; 770 uint16_t ea_hseq; 771 /* only the LSB */ 772 uint8_t hseq_nlis; 773 uint8_t pad4; 774 uint16_t ea_hptr; 775 uint16_t pad5; 776 uint16_t ea_tptr; 777 uint16_t pad6; 778 uint16_t opr_vid; 779 uint16_t pad7; 780 uint16_t opr_id; 781 }; 782 783 struct dpni_cmd_add_custom_tpid { 784 uint16_t pad; 785 uint16_t tpid; 786 }; 787 788 struct dpni_cmd_remove_custom_tpid { 789 uint16_t pad; 790 uint16_t tpid; 791 }; 792 793 struct dpni_rsp_get_custom_tpid { 794 uint16_t tpid1; 795 uint16_t tpid2; 796 }; 797 798 #define DPNI_RX_FS_DIST_ENABLE_SHIFT 0 799 #define DPNI_RX_FS_DIST_ENABLE_SIZE 1 800 struct dpni_cmd_set_rx_fs_dist { 801 uint16_t dist_size; 802 uint8_t enable; 803 uint8_t tc; 804 uint16_t miss_flow_id; 805 uint16_t pad1; 806 uint64_t key_cfg_iova; 807 }; 808 809 #define DPNI_RX_HASH_DIST_ENABLE_SHIFT 0 810 #define DPNI_RX_HASH_DIST_ENABLE_SIZE 1 811 struct dpni_cmd_set_rx_hash_dist { 812 uint16_t dist_size; 813 uint8_t enable; 814 uint8_t tc_id; 815 uint32_t pad; 816 uint64_t key_cfg_iova; 817 }; 818 819 struct dpni_load_sw_sequence { 820 uint8_t dest; 821 uint8_t pad0[7]; 822 uint16_t ss_offset; 823 uint16_t pad1; 824 uint16_t ss_size; 825 uint16_t pad2; 826 uint64_t ss_iova; 827 }; 828 829 struct dpni_enable_sw_sequence { 830 uint8_t dest; 831 uint8_t pad0[7]; 832 uint16_t ss_offset; 833 uint16_t hxs; 834 uint8_t set_start; 835 uint8_t pad1[3]; 836 uint8_t param_offset; 837 uint8_t pad2[3]; 838 uint8_t param_size; 839 uint8_t pad3[3]; 840 uint64_t param_iova; 841 }; 842 843 struct dpni_get_sw_sequence_layout { 844 uint8_t src; 845 uint8_t pad0[7]; 846 uint64_t layout_iova; 847 }; 848 849 struct dpni_sw_sequence_layout_entry { 850 uint16_t ss_offset; 851 uint16_t ss_size; 852 uint8_t param_offset; 853 uint8_t param_size; 854 uint16_t pad; 855 }; 856 857 #pragma pack(pop) 858 #endif /* _FSL_DPNI_CMD_H */ 859