1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2019 Marvell International Ltd. 3 */ 4 5 #ifndef _DPI_RAWDEV_H_ 6 #define _DPI_RAWDEV_H_ 7 8 #include "otx2_common.h" 9 #include "otx2_mempool.h" 10 11 #define DPI_QUEUE_OPEN 0x1 12 #define DPI_QUEUE_CLOSE 0x2 13 14 /* DPI VF register offsets from VF_BAR0 */ 15 #define DPI_VDMA_EN (0x0) 16 #define DPI_VDMA_REQQ_CTL (0x8) 17 #define DPI_VDMA_DBELL (0x10) 18 #define DPI_VDMA_SADDR (0x18) 19 #define DPI_VDMA_COUNTS (0x20) 20 #define DPI_VDMA_NADDR (0x28) 21 #define DPI_VDMA_IWBUSY (0x30) 22 #define DPI_VDMA_CNT (0x38) 23 #define DPI_VF_INT (0x100) 24 #define DPI_VF_INT_W1S (0x108) 25 #define DPI_VF_INT_ENA_W1C (0x110) 26 #define DPI_VF_INT_ENA_W1S (0x118) 27 28 #define DPI_MAX_VFS 8 29 #define DPI_DMA_CMD_SIZE 64 30 #define DPI_CHUNK_SIZE 1024 31 #define DPI_QUEUE_STOP 0x0 32 #define DPI_QUEUE_START 0x1 33 34 #define DPI_VDMA_SADDR_REQ_IDLE 63 35 #define DPI_MAX_POINTER 15 36 #define STRM_INC(s) ((s)->tail = ((s)->tail + 1) % (s)->max_cnt) 37 #define DPI_QFINISH_TIMEOUT (10 * 1000) 38 39 /* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */ 40 #define DPI_XTYPE_OUTBOUND (0) 41 #define DPI_XTYPE_INBOUND (1) 42 #define DPI_XTYPE_INTERNAL_ONLY (2) 43 #define DPI_XTYPE_EXTERNAL_ONLY (3) 44 #define DPI_XTYPE_MASK 0x3 45 #define DPI_HDR_PT_ZBW_CA 0x0 46 #define DPI_HDR_PT_ZBW_NC 0x1 47 #define DPI_HDR_PT_WQP 0x2 48 #define DPI_HDR_PT_WQP_NOSTATUS 0x0 49 #define DPI_HDR_PT_WQP_STATUSCA 0x1 50 #define DPI_HDR_PT_WQP_STATUSNC 0x3 51 #define DPI_HDR_PT_CNT 0x3 52 #define DPI_HDR_PT_MASK 0x3 53 #define DPI_W0_TT_MASK 0x3 54 #define DPI_W0_GRP_MASK 0x3FF 55 /* Set Completion data to 0xFF when request submitted, 56 * upon successful request completion engine reset to completion status 57 */ 58 #define DPI_REQ_CDATA 0xFF 59 60 struct dpi_vf_s { 61 struct rte_pci_device *dev; 62 uint8_t state; 63 uint16_t vf_id; 64 uint8_t domain; 65 uintptr_t vf_bar0; 66 uintptr_t vf_bar2; 67 68 uint16_t pool_size_m1; 69 uint16_t index; 70 uint64_t *base_ptr; 71 void *chunk_pool; 72 struct otx2_mbox *mbox; 73 }; 74 75 struct dpi_rawdev_conf_s { 76 void *chunk_pool; 77 }; 78 79 enum dpi_dma_queue_result_e { 80 DPI_DMA_QUEUE_SUCCESS = 0, 81 DPI_DMA_QUEUE_NO_MEMORY = -1, 82 DPI_DMA_QUEUE_INVALID_PARAM = -2, 83 }; 84 85 struct dpi_dma_req_compl_s { 86 uint64_t cdata; 87 void (*compl_cb)(void *dev, void *arg); 88 void *cb_data; 89 }; 90 91 union dpi_dma_ptr_u { 92 uint64_t u[2]; 93 struct dpi_dma_s { 94 uint64_t length:16; 95 uint64_t reserved:44; 96 uint64_t bed:1; /* Big-Endian */ 97 uint64_t alloc_l2:1; 98 uint64_t full_write:1; 99 uint64_t invert:1; 100 uint64_t ptr; 101 } s; 102 }; 103 104 struct dpi_dma_buf_ptr_s { 105 union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */ 106 union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */ 107 uint8_t rptr_cnt; 108 uint8_t wptr_cnt; 109 struct dpi_dma_req_compl_s *comp_ptr; 110 }; 111 112 struct dpi_cring_data_s { 113 struct dpi_dma_req_compl_s **compl_data; 114 uint16_t max_cnt; 115 uint16_t head; 116 uint16_t tail; 117 }; 118 119 struct dpi_dma_queue_ctx_s { 120 uint16_t xtype:2; 121 122 /* Completion pointer type */ 123 uint16_t pt:2; 124 125 /* Completion updated using WQE */ 126 uint16_t tt:2; 127 uint16_t grp:10; 128 uint32_t tag; 129 130 /* Valid only for Outbound only mode */ 131 uint16_t aura:12; 132 uint16_t csel:1; 133 uint16_t ca:1; 134 uint16_t fi:1; 135 uint16_t ii:1; 136 uint16_t fl:1; 137 138 uint16_t pvfe:1; 139 uint16_t dealloce:1; 140 uint16_t req_type:2; 141 uint16_t use_lock:1; 142 uint16_t deallocv; 143 uint16_t pem_id; 144 145 struct dpi_cring_data_s *c_ring; 146 }; 147 148 /* DPI DMA Instruction Header Format */ 149 union dpi_dma_instr_hdr_u { 150 uint64_t u[4]; 151 152 struct dpi_dma_instr_hdr_s_s { 153 uint64_t tag:32; 154 uint64_t tt:2; 155 uint64_t grp:10; 156 uint64_t reserved_44_47:4; 157 uint64_t nfst:4; 158 uint64_t reserved_52_53:2; 159 uint64_t nlst:4; 160 uint64_t reserved_58_63:6; 161 /* Word 0 - End */ 162 163 uint64_t aura:12; 164 uint64_t reserved_76_79:4; 165 uint64_t deallocv:16; 166 uint64_t dealloce:1; 167 uint64_t pvfe:1; 168 uint64_t reserved_98_99:2; 169 uint64_t pt:2; 170 uint64_t reserved_102_103:2; 171 uint64_t fl:1; 172 uint64_t ii:1; 173 uint64_t fi:1; 174 uint64_t ca:1; 175 uint64_t csel:1; 176 uint64_t reserved_109_111:3; 177 uint64_t xtype:2; 178 uint64_t reserved_114_119:6; 179 uint64_t fport:2; 180 uint64_t reserved_122_123:2; 181 uint64_t lport:2; 182 uint64_t reserved_126_127:2; 183 /* Word 1 - End */ 184 185 uint64_t ptr:64; 186 /* Word 2 - End */ 187 188 uint64_t reserved_192_255:64; 189 /* Word 3 - End */ 190 } s; 191 }; 192 193 int otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura); 194 int otx2_dpi_queue_close(struct dpi_vf_s *dpivf); 195 int test_otx2_dma_rawdev(uint16_t val); 196 197 #endif /* _DPI_RAWDEV_H_ */ 198