Searched refs:DLB2_CHP_CFG_CHP_CSR_CTRL (Results 1 – 2 of 2) sorted by relevance
68 r0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL); in dlb2_hw_enable_sparse_dir_cq_mode()72 DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val); in dlb2_hw_enable_sparse_dir_cq_mode()127 r0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL); in dlb2_hw_enable_sparse_ldb_cq_mode()131 DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val); in dlb2_hw_enable_sparse_ldb_cq_mode()
1383 #define DLB2_CHP_CFG_CHP_CSR_CTRL 0x44000008 macro