1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright 2020 Michal Meloun <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/lock.h>
35 #include <sys/mutex.h>
36 #include <sys/rman.h>
37
38 #include <machine/bus.h>
39
40 #include <dev/extres/clk/clk_div.h>
41 #include <dev/extres/clk/clk_fixed.h>
42 #include <dev/extres/clk/clk_gate.h>
43 #include <dev/extres/clk/clk_mux.h>
44
45 #include <dt-bindings/clock/tegra210-car.h>
46 #include "tegra210_car.h"
47
48 #if 0
49 #define dprintf(...) printf(__VA_ARGS__)
50 #else
51 #define dprintf(...)
52 #endif
53
54 /* All PLLs. */
55 enum pll_type {
56 PLL_M,
57 PLL_MB,
58 PLL_X,
59 PLL_C,
60 PLL_C2,
61 PLL_C3,
62 PLL_C4,
63 PLL_P,
64 PLL_A,
65 PLL_A1,
66 PLL_U,
67 PLL_D,
68 PLL_D2,
69 PLL_DP,
70 PLL_E,
71 PLL_REFE};
72 /* Flags for PLLs */
73
74 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */
75 #define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */
76 #define PLL_FLAG_HAVE_SDM 0x04 /* Have SDM implemented */
77 #define PLL_FLAG_HAVE_SDA 0x04 /* Have SDA implemented */
78
79 /* Common base register bits. */
80 #define PLL_BASE_BYPASS (1U << 31)
81 #define PLL_BASE_ENABLE (1 << 30)
82 #define PLL_BASE_REFDISABLE (1 << 29)
83 #define PLL_BASE_LOCK (1 << 27)
84
85 #define PLLREFE_MISC_LOCK (1 << 27)
86
87 #define PLL_MISC_LOCK_ENABLE (1 << 18)
88 #define PLLM_LOCK_ENABLE (1 << 4)
89 #define PLLMB_LOCK_ENABLE (1 << 16)
90 #define PLLC_LOCK_ENABLE (1 << 24)
91 #define PLLC4_LOCK_ENABLE (1 << 30)
92 #define PLLA_LOCK_ENABLE (1 << 28)
93 #define PLLD2_LOCK_ENABLE (1 << 30)
94 #define PLLU_LOCK_ENABLE (1 << 29)
95 #define PLLREFE_LOCK_ENABLE (1 << 30)
96 #define PLLPD_LOCK_ENABLE (1 << 30)
97 #define PLLE_LOCK_ENABLE (1 << 9)
98
99 #define PLLM_IDDQ_BIT 5
100 #define PLLMB_IDDQ_BIT 17
101 #define PLLC_IDDQ_BIT 27
102 #define PLLC4_IDDQ_BIT 18
103 #define PLLP_IDDQ_BIT 3
104 #define PLLA_IDDQ_BIT 25
105 #define PLLA1_IDDQ_BIT 27
106 #define PLLU_IDDQ_BIT 31
107 #define PLLD_IDDQ_BIT 20
108 #define PLLD2_IDDQ_BIT 18
109 #define PLLX_IDDQ_BIT 3
110 #define PLLREFE_IDDQ_BIT 24
111 #define PLLDP_IDDQ_BIT 18
112
113
114 #define PLL_LOCK_TIMEOUT 5000
115
116 /* Post divider <-> register value mapping. */
117 struct pdiv_table {
118 uint32_t divider; /* real divider */
119 uint32_t value; /* register value */
120 };
121
122 /* Bits definition of M, N and P fields. */
123 struct mnp_bits {
124 uint32_t m_width;
125 uint32_t n_width;
126 uint32_t p_width;
127 uint32_t m_shift;
128 uint32_t n_shift;
129 uint32_t p_shift;
130 };
131
132 struct clk_pll_def {
133 struct clknode_init_def clkdef;
134 enum pll_type type;
135 uint32_t base_reg;
136 uint32_t misc_reg;
137 uint32_t lock_enable;
138 uint32_t iddq_reg;
139 uint32_t iddq_mask;
140 uint32_t flags;
141 struct pdiv_table *pdiv_table;
142 struct mnp_bits mnp_bits;
143 };
144
145 #define PLIST(x) static const char *x[]
146
147 #define PLL(_id, cname, pname) \
148 .clkdef.id = _id, \
149 .clkdef.name = cname, \
150 .clkdef.parent_names = (const char *[]){pname}, \
151 .clkdef.parent_cnt = 1, \
152 .clkdef.flags = CLK_NODE_STATIC_STRINGS
153
154 /* multiplexer for pll sources. */
155 #define MUX(_id, cname, plists, o, s, w) \
156 { \
157 .clkdef.id = _id, \
158 .clkdef.name = cname, \
159 .clkdef.parent_names = plists, \
160 .clkdef.parent_cnt = nitems(plists), \
161 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
162 .offset = o, \
163 .shift = s, \
164 .width = w, \
165 }
166
167 /* Fractional divider (7.1) for PLL branch. */
168 #define DIV7_1(_id, cname, plist, o, s) \
169 { \
170 .clkdef.id = _id, \
171 .clkdef.name = cname, \
172 .clkdef.parent_names = (const char *[]){plist}, \
173 .clkdef.parent_cnt = 1, \
174 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
175 .offset = o, \
176 .i_shift = (s) + 1, \
177 .i_width = 7, \
178 .f_shift = s, \
179 .f_width = 1, \
180 }
181
182 /* P divider (2^n). for PLL branch. */
183 #define DIV5_E(_id, cname, plist, o, s) \
184 { \
185 .clkdef.id = _id, \
186 .clkdef.name = cname, \
187 .clkdef.parent_names = (const char *[]){plist}, \
188 .clkdef.parent_cnt = 1, \
189 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
190 .offset = o, \
191 .i_shift = s, \
192 .i_width = 5, \
193 }
194
195 /* P divider (2^n). for PLL branch. */
196 #define DIV_TB(_id, cname, plist, o, s, n, table) \
197 { \
198 .clkdef.id = _id, \
199 .clkdef.name = cname, \
200 .clkdef.parent_names = (const char *[]){plist}, \
201 .clkdef.parent_cnt = 1, \
202 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
203 .div_flags = CLK_DIV_WITH_TABLE | CLK_DIV_ZERO_BASED, \
204 .offset = o, \
205 .i_shift = s, \
206 .i_width = n, \
207 .div_table = table, \
208 }
209
210 /* Standard gate. */
211 #define GATE(_id, cname, plist, o, s) \
212 { \
213 .clkdef.id = _id, \
214 .clkdef.name = cname, \
215 .clkdef.parent_names = (const char *[]){plist}, \
216 .clkdef.parent_cnt = 1, \
217 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
218 .offset = o, \
219 .shift = s, \
220 .mask = 1, \
221 .on_value = 1, \
222 .off_value = 0, \
223 }
224 /* Gate for PLL branch. */
225 #define GATE_PLL(_id, cname, plist, o, s) \
226 { \
227 .clkdef.id = _id, \
228 .clkdef.name = cname, \
229 .clkdef.parent_names = (const char *[]){plist}, \
230 .clkdef.parent_cnt = 1, \
231 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
232 .offset = o, \
233 .shift = s, \
234 .mask = 3, \
235 .on_value = 3, \
236 .off_value = 0, \
237 }
238
239 /* Fixed rate multipier/divider. */
240 #define FACT(_id, cname, pname, _mult, _div) \
241 { \
242 .clkdef.id = _id, \
243 .clkdef.name = cname, \
244 .clkdef.parent_names = (const char *[]){pname}, \
245 .clkdef.parent_cnt = 1, \
246 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
247 .mult = _mult, \
248 .div = _div, \
249 }
250
251 static struct pdiv_table qlin_map[] = {
252 { 1, 0},
253 { 2, 1},
254 { 3, 2},
255 { 4, 3},
256 { 5, 4},
257 { 6, 5},
258 { 8, 6},
259 { 9, 7},
260 {10, 8},
261 {12, 9},
262 {15, 10},
263 {16, 11},
264 {18, 12},
265 {20, 13},
266 {24, 14},
267 {30, 15},
268 {32, 16},
269 { 0, 0},
270 };
271
272 static struct clk_pll_def pll_clks[] = {
273 /* PLLM: 880 MHz Clock source for EMC 2x clock */
274 {
275 PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"),
276 .type = PLL_M,
277 .base_reg = PLLM_BASE,
278 .misc_reg = PLLM_MISC2,
279 .lock_enable = PLLM_LOCK_ENABLE,
280 .iddq_reg = PLLM_MISC2,
281 .iddq_mask = 1 << PLLM_IDDQ_BIT,
282 .pdiv_table = qlin_map,
283 .mnp_bits = {8, 8, 5, 0, 8, 20},
284 },
285 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
286 {
287 PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"),
288 .type = PLL_MB,
289 .base_reg = PLLMB_BASE,
290 .misc_reg = PLLMB_MISC1,
291 .lock_enable = PLLMB_LOCK_ENABLE,
292 .iddq_reg = PLLMB_MISC1,
293 .iddq_mask = 1 << PLLMB_IDDQ_BIT,
294 .pdiv_table = qlin_map,
295 .mnp_bits = {8, 8, 5, 0, 8, 20},
296 },
297 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
298 {
299 PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"),
300 .type = PLL_X,
301 .base_reg = PLLX_BASE,
302 .misc_reg = PLLX_MISC,
303 .lock_enable = PLL_MISC_LOCK_ENABLE,
304 .iddq_reg = PLLX_MISC_3,
305 .iddq_mask = 1 << PLLX_IDDQ_BIT,
306 .pdiv_table = qlin_map,
307 .mnp_bits = {8, 8, 5, 0, 8, 20},
308 },
309 /* PLLC: 510 MHz Clock source for camera use */
310 {
311 PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
312 .type = PLL_C,
313 .base_reg = PLLC_BASE,
314 .misc_reg = PLLC_MISC_0,
315 .iddq_reg = PLLC_MISC_1,
316 .iddq_mask = 1 << PLLC_IDDQ_BIT,
317 .pdiv_table = qlin_map,
318 .mnp_bits = {8, 8, 5, 0, 10, 20},
319 },
320 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
321 {
322 PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
323 .type = PLL_C2,
324 .base_reg = PLLC2_BASE,
325 .misc_reg = PLLC2_MISC_0,
326 .iddq_reg = PLLC2_MISC_1,
327 .iddq_mask = 1 << PLLC_IDDQ_BIT,
328 .pdiv_table = qlin_map,
329 .mnp_bits = {8, 8, 5, 0, 10, 20},
330 },
331 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
332 {
333 PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
334 .type = PLL_C3,
335 .base_reg = PLLC3_BASE,
336 .misc_reg = PLLC3_MISC_0,
337 .lock_enable = PLL_MISC_LOCK_ENABLE,
338 .iddq_reg = PLLC3_MISC_1,
339 .iddq_mask = 1 << PLLC_IDDQ_BIT,
340 .mnp_bits = {8, 8, 5, 0, 10, 20},
341 },
342 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */
343 {
344 PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"),
345 .type = PLL_C4,
346 .flags = PLL_FLAG_VCO_OUT,
347 .base_reg = PLLC4_BASE,
348 .misc_reg = PLLC4_MISC,
349 .lock_enable = PLLC4_LOCK_ENABLE,
350 .iddq_reg = PLLC4_BASE,
351 .iddq_mask = 1 << PLLC4_IDDQ_BIT,
352 .pdiv_table = qlin_map,
353 .mnp_bits = {8, 8, 5, 0, 8, 19},
354 },
355 /* PLLP: 408 MHz Clock source for most peripherals */
356 {
357 /*
358 * VCO is directly exposed as pllP_out0, P div is used for
359 * pllP_out2
360 */
361 PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
362 .type = PLL_P,
363 .flags = PLL_FLAG_VCO_OUT,
364 .base_reg = PLLP_BASE,
365 .misc_reg = PLLP_MISC,
366 .lock_enable = PLL_MISC_LOCK_ENABLE,
367 .iddq_reg = PLLP_MISC,
368 .iddq_mask = 1 << PLLA_IDDQ_BIT,
369 .mnp_bits = {8, 8, 5, 0, 10, 20},
370 },
371 /* PLLA: Audio clock for precise codec sampling */
372 {
373 PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"),
374 .type = PLL_A,
375 .base_reg = PLLA_BASE,
376 .misc_reg = PLLA_MISC,
377 .lock_enable = PLLA_LOCK_ENABLE,
378 .iddq_reg = PLLA_BASE,
379 .iddq_mask = 1 << PLLA_IDDQ_BIT,
380 .pdiv_table = qlin_map,
381 .mnp_bits = {8, 8, 5, 0, 8, 20},
382 },
383 /* PLLA1: Audio clock for ADSP */
384 {
385 PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"),
386 .type = PLL_A1,
387 .base_reg = PLLA1_BASE,
388 .misc_reg = PLLA1_MISC_1,
389 .iddq_reg = PLLA1_MISC_1,
390 .iddq_mask = 1 << PLLA_IDDQ_BIT,
391 .pdiv_table = qlin_map,
392 .mnp_bits = {8, 8, 5, 0, 8, 20},
393 },
394 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
395 {
396 PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"),
397 .type = PLL_U,
398 .flags = PLL_FLAG_VCO_OUT | PLL_FLAG_HAVE_SDA,
399 .base_reg = PLLU_BASE,
400 .misc_reg = PLLU_MISC,
401 .lock_enable = PLLU_LOCK_ENABLE,
402 .iddq_reg = PLLU_MISC,
403 .iddq_mask = 1 << PLLU_IDDQ_BIT,
404 .pdiv_table = qlin_map,
405 .mnp_bits = {8, 8, 5, 0, 8, 16},
406 },
407 /* PLLD: 594 MHz Clock sources for the DSI and display subsystem */
408 {
409 PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"),
410 .type = PLL_D,
411 .flags = PLL_FLAG_PDIV_POWER2,
412 .base_reg = PLLD_BASE,
413 .misc_reg = PLLD_MISC,
414 .lock_enable = PLL_MISC_LOCK_ENABLE,
415 .iddq_reg = PLLA1_MISC_1,
416 .iddq_mask = 1 << PLLA_IDDQ_BIT,
417 .mnp_bits = {8, 8, 3, 0, 11, 20},
418 },
419 /* PLLD2: 594 MHz Clock sources for the DSI and display subsystem */
420 {
421 PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
422 .type = PLL_D2,
423 .flags = PLL_FLAG_HAVE_SDM,
424 .base_reg = PLLD2_BASE,
425 .misc_reg = PLLD2_MISC,
426 .lock_enable = PLLD2_LOCK_ENABLE,
427 .iddq_reg = PLLD2_BASE,
428 .iddq_mask = 1 << PLLD_IDDQ_BIT,
429 .pdiv_table = qlin_map,
430 .mnp_bits = {8, 8, 5, 0, 8, 19},
431 },
432 /* PLLREFE: 624 Mhz*/
433 {
434 PLL(0, "pllREFE", "osc_div_clk"),
435 .type = PLL_REFE,
436 .flags = PLL_FLAG_VCO_OUT,
437 .base_reg = PLLREFE_BASE,
438 .misc_reg = PLLREFE_MISC,
439 .lock_enable = PLLREFE_LOCK_ENABLE,
440 .iddq_reg = PLLREFE_MISC,
441 .iddq_mask = 1 << PLLREFE_IDDQ_BIT,
442 .pdiv_table = qlin_map,
443 .mnp_bits = {8, 8, 5, 0, 8, 16},
444 },
445 /* PLLE: 100 MHz reference clock for PCIe/SATA/USB 3.0 (spread spectrum) */
446 {
447 PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"),
448 .type = PLL_E,
449 .base_reg = PLLE_BASE,
450 .misc_reg = PLLE_MISC,
451 .lock_enable = PLLE_LOCK_ENABLE,
452 .pdiv_table = qlin_map,
453 .mnp_bits = {8, 8, 5, 0, 8, 24},
454 },
455 /* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */
456 {
457 PLL(0, "pllDP_out0", "pllDP_src"),
458 .type = PLL_DP,
459 .flags = PLL_FLAG_HAVE_SDM,
460 .base_reg = PLLDP_BASE,
461 .misc_reg = PLLDP_MISC,
462 .lock_enable = PLLPD_LOCK_ENABLE,
463 .iddq_reg = PLLDP_BASE,
464 .iddq_mask = 1 << PLLDP_IDDQ_BIT,
465 .pdiv_table = qlin_map,
466 .mnp_bits = {8, 8, 5, 0, 8, 19},
467 },
468 };
469
470 /* Fixed rate dividers. */
471 static struct clk_fixed_def tegra210_pll_fdivs[] = {
472 FACT(0, "pllP_UD", "pllP_out0", 1, 1),
473 FACT(0, "pllC_UD", "pllC_out0", 1, 1),
474 FACT(0, "pllD_UD", "pllD_out0", 1, 1),
475 FACT(0, "pllM_UD", "pllM_out0", 1, 1),
476 FACT(0, "pllMB_UD", "pllMB_out0", 1, 1),
477 FACT(TEGRA210_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2),
478
479 FACT(0, "pllC4_out1", "pllC4", 1, 3),
480 FACT(0, "pllC4_out2", "pllC4", 1, 5),
481 FACT(0, "pllD2_out0", "pllD2_out", 1, 2),
482
483 /* Aliases used in super mux. */
484 FACT(0, "pllX_out0_alias", "pllX_out0", 1, 1),
485 FACT(0, "dfllCPU_out_alias", "dfllCPU_out", 1, 1),
486 };
487
488 /* MUXes for PLL sources. */
489 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
490 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
491 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"};
492 static struct clk_mux_def tegra210_pll_sources[] = {
493 /* Core clocks. */
494 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
495 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
496 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
497 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
498 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
499 };
500
501 /* Gates for PLL branches. */
502 static struct clk_gate_def tegra210_pll_gates[] = {
503 /* Core clocks. */
504 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
505
506 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
507 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
508 GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
509 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
510
511 GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0),
512 GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16),
513 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
514 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
515 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
516
517 GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0),
518 GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0),
519
520 GATE_PLL(0, "pllA_out0", "pllA_out0_div", PLLA_OUT, 0),
521 };
522
523 struct clk_div_table tegra210_pll_pdiv_tbl[] = {
524 /* value , divider */
525 { 0, 1 },
526 { 1, 2 },
527 { 2, 3 },
528 { 3, 4 },
529 { 4, 5 },
530 { 5, 6 },
531 { 6, 8 },
532 { 7, 10 },
533 { 8, 12 },
534 { 9, 16 },
535 {10, 12 },
536 {11, 16 },
537 {12, 20 },
538 {13, 24 },
539 {14, 32 },
540 { 0, 0 },
541 };
542
543 /* Dividers for PLL branches. */
544 static struct clk_div_def tegra210_pll_divs[] = {
545 /* Core clocks. */
546 DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 8),
547
548 DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8),
549 DIV_TB(0, "pllP_out2", "pllP_out0", PLLP_BASE, 20, 5, tegra210_pll_pdiv_tbl),
550 DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),
551 DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),
552 DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24),
553
554 DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl),
555 DIV7_1(0, "pllU_out1_div", "pllU_out0", PLLU_OUTA, 8),
556 DIV7_1(0, "pllU_out2_div", "pllU_out0", PLLU_OUTA, 24),
557
558 DIV_TB(0, "pllREFE_out0", "pllREFE", PLLREFE_BASE, 16, 5, tegra210_pll_pdiv_tbl),
559 DIV7_1(0, "pllREFE_out1_div", "pllREFE", PLLREFE_OUT, 8),
560
561 DIV_TB(TEGRA210_CLK_PLL_C4_OUT0,
562 "pllC4_out0", "pllC4", PLLC4_BASE, 19, 5, tegra210_pll_pdiv_tbl),
563 DIV7_1(0, "pllC4_out3_div", "pllC4_out0", PLLC4_OUT, 8),
564
565 DIV7_1(0, "pllA_out0_div", "pllA", PLLA_OUT, 8),
566
567 };
568
569 static int tegra210_pll_init(struct clknode *clk, device_t dev);
570 static int tegra210_pll_set_gate(struct clknode *clk, bool enable);
571 static int tegra210_pll_recalc(struct clknode *clk, uint64_t *freq);
572 static int tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin,
573 uint64_t *fout, int flags, int *stop);
574 struct pll_sc {
575 device_t clkdev;
576 enum pll_type type;
577 uint32_t base_reg;
578 uint32_t misc_reg;
579 uint32_t lock_enable;
580 uint32_t iddq_reg;
581 uint32_t iddq_mask;
582 uint32_t flags;
583 struct pdiv_table *pdiv_table;
584 struct mnp_bits mnp_bits;
585 };
586
587 static clknode_method_t tegra210_pll_methods[] = {
588 /* Device interface */
589 CLKNODEMETHOD(clknode_init, tegra210_pll_init),
590 CLKNODEMETHOD(clknode_set_gate, tegra210_pll_set_gate),
591 CLKNODEMETHOD(clknode_recalc_freq, tegra210_pll_recalc),
592 CLKNODEMETHOD(clknode_set_freq, tegra210_pll_set_freq),
593 CLKNODEMETHOD_END
594 };
595 DEFINE_CLASS_1(tegra210_pll, tegra210_pll_class, tegra210_pll_methods,
596 sizeof(struct pll_sc), clknode_class);
597
598 static int
pll_enable(struct pll_sc * sc)599 pll_enable(struct pll_sc *sc)
600 {
601 uint32_t reg;
602
603
604 RD4(sc, sc->base_reg, ®);
605 if (sc->type != PLL_E)
606 reg &= ~PLL_BASE_BYPASS;
607 reg |= PLL_BASE_ENABLE;
608 WR4(sc, sc->base_reg, reg);
609 return (0);
610 }
611
612 static int
pll_disable(struct pll_sc * sc)613 pll_disable(struct pll_sc *sc)
614 {
615 uint32_t reg;
616
617 RD4(sc, sc->base_reg, ®);
618 if (sc->type != PLL_E)
619 reg |= PLL_BASE_BYPASS;
620 reg &= ~PLL_BASE_ENABLE;
621 WR4(sc, sc->base_reg, reg);
622 return (0);
623 }
624
625 static uint32_t
pdiv_to_reg(struct pll_sc * sc,uint32_t p_div)626 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)
627 {
628 struct pdiv_table *tbl;
629
630 tbl = sc->pdiv_table;
631 if (tbl == NULL) {
632 if (sc->flags & PLL_FLAG_PDIV_POWER2)
633 return (ffs(p_div) - 1);
634 else
635 return (p_div);
636 }
637
638 while (tbl->divider != 0) {
639 if (p_div <= tbl->divider)
640 return (tbl->value);
641 tbl++;
642 }
643 return (0xFFFFFFFF);
644 }
645
646 static uint32_t
reg_to_pdiv(struct pll_sc * sc,uint32_t reg)647 reg_to_pdiv(struct pll_sc *sc, uint32_t reg)
648 {
649 struct pdiv_table *tbl;
650
651 tbl = sc->pdiv_table;
652 if (tbl == NULL) {
653 if (sc->flags & PLL_FLAG_PDIV_POWER2)
654 return (1 << reg);
655 else
656 return (reg == 0 ? 1: reg);
657 }
658 while (tbl->divider) {
659 if (reg == tbl->value)
660 return (tbl->divider);
661 tbl++;
662 }
663 return (0);
664 }
665
666 static uint32_t
get_masked(uint32_t val,uint32_t shift,uint32_t width)667 get_masked(uint32_t val, uint32_t shift, uint32_t width)
668 {
669
670 return ((val >> shift) & ((1 << width) - 1));
671 }
672
673 static uint32_t
set_masked(uint32_t val,uint32_t v,uint32_t shift,uint32_t width)674 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width)
675 {
676
677 val &= ~(((1 << width) - 1) << shift);
678 val |= (v & ((1 << width) - 1)) << shift;
679 return (val);
680 }
681
682 static void
get_divisors(struct pll_sc * sc,uint32_t * m,uint32_t * n,uint32_t * p)683 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)
684 {
685 uint32_t val;
686 struct mnp_bits *mnp_bits;
687
688 mnp_bits = &sc->mnp_bits;
689 RD4(sc, sc->base_reg, &val);
690 *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width);
691 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width);
692 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
693 }
694
695 static uint32_t
set_divisors(struct pll_sc * sc,uint32_t val,uint32_t m,uint32_t n,uint32_t p)696 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,
697 uint32_t p)
698 {
699 struct mnp_bits *mnp_bits;
700
701 mnp_bits = &sc->mnp_bits;
702 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width);
703 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width);
704 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
705 return (val);
706 }
707
708 static bool
is_locked(struct pll_sc * sc)709 is_locked(struct pll_sc *sc)
710 {
711 uint32_t reg;
712
713 switch (sc->type) {
714 case PLL_REFE:
715 RD4(sc, sc->misc_reg, ®);
716 reg &= PLLREFE_MISC_LOCK;
717 break;
718
719 case PLL_E:
720 RD4(sc, sc->misc_reg, ®);
721 reg &= PLLE_MISC_LOCK;
722 break;
723
724 default:
725 RD4(sc, sc->base_reg, ®);
726 reg &= PLL_BASE_LOCK;
727 break;
728 }
729 return (reg != 0);
730 }
731
732 static int
wait_for_lock(struct pll_sc * sc)733 wait_for_lock(struct pll_sc *sc)
734 {
735 int i;
736
737 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
738 if (is_locked(sc))
739 break;
740 DELAY(10);
741 }
742 if (i <= 0) {
743 printf("PLL lock timeout\n");
744 return (ETIMEDOUT);
745 }
746 return (0);
747 }
748
749 static int
plle_enable(struct pll_sc * sc)750 plle_enable(struct pll_sc *sc)
751 {
752 uint32_t reg;
753 int rv;
754 struct mnp_bits *mnp_bits;
755 uint32_t pll_m = 2;
756 uint32_t pll_n = 125;
757 uint32_t pll_cml = 14;
758
759 mnp_bits = &sc->mnp_bits;
760
761 /* Disable lock override. */
762 RD4(sc, sc->base_reg, ®);
763 reg &= ~PLLE_BASE_LOCK_OVERRIDE;
764 WR4(sc, sc->base_reg, reg);
765
766 /* Enable SW control */
767 RD4(sc, PLLE_AUX, ®);
768 reg |= PLLE_AUX_ENABLE_SWCTL;
769 reg &= ~PLLE_AUX_SEQ_ENABLE;
770 WR4(sc, PLLE_AUX, reg);
771 DELAY(10);
772
773 RD4(sc, sc->misc_reg, ®);
774 reg |= PLLE_MISC_LOCK_ENABLE;
775 reg |= PLLE_MISC_IDDQ_SWCTL;
776 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
777 reg |= PLLE_MISC_PTS;
778 reg &= ~PLLE_MISC_VREG_BG_CTRL(~0);
779 reg &= ~PLLE_MISC_VREG_CTRL(~0);
780 WR4(sc, sc->misc_reg, reg);
781 DELAY(10);
782
783 RD4(sc, PLLE_SS_CNTL, ®);
784 reg |= PLLE_SS_CNTL_DISABLE;
785 WR4(sc, PLLE_SS_CNTL, reg);
786
787 RD4(sc, sc->base_reg, ®);
788 reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml);
789 WR4(sc, sc->base_reg, reg);
790 DELAY(10);
791
792 pll_enable(sc);
793 rv = wait_for_lock(sc);
794 if (rv != 0)
795 return (rv);
796
797 RD4(sc, PLLE_SS_CNTL, ®);
798 reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0);
799 reg &= ~PLLE_SS_CNTL_SSCINC(~0);
800 reg &= ~PLLE_SS_CNTL_SSCINVERT;
801 reg &= ~PLLE_SS_CNTL_SSCCENTER;
802 reg &= ~PLLE_SS_CNTL_SSCMAX(~0);
803 reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23);
804 reg |= PLLE_SS_CNTL_SSCINC(0x1);
805 reg |= PLLE_SS_CNTL_SSCMAX(0x21);
806 WR4(sc, PLLE_SS_CNTL, reg);
807 reg &= ~PLLE_SS_CNTL_SSCBYP;
808 reg &= ~PLLE_SS_CNTL_BYPASS_SS;
809 WR4(sc, PLLE_SS_CNTL, reg);
810 DELAY(10);
811
812 reg &= ~PLLE_SS_CNTL_INTERP_RESET;
813 WR4(sc, PLLE_SS_CNTL, reg);
814 DELAY(10);
815
816 /* HW control of brick pll. */
817 RD4(sc, sc->misc_reg, ®);
818 reg &= ~PLLE_MISC_IDDQ_SWCTL;
819 WR4(sc, sc->misc_reg, reg);
820
821 RD4(sc, PLLE_AUX, ®);
822 reg |= PLLE_AUX_USE_LOCKDET;
823 reg |= PLLE_AUX_SS_SEQ_INCLUDE;
824 reg &= ~PLLE_AUX_ENABLE_SWCTL;
825 reg &= ~PLLE_AUX_SS_SWCTL;
826 WR4(sc, PLLE_AUX, reg);
827 reg |= PLLE_AUX_SEQ_START_STATE;
828 DELAY(10);
829 reg |= PLLE_AUX_SEQ_ENABLE;
830 WR4(sc, PLLE_AUX, reg);
831
832 /* Enable and start XUSBIO PLL HW control*/
833 RD4(sc, XUSBIO_PLL_CFG0, ®);
834 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
835 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
836 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
837 reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
838 reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE;
839 WR4(sc, XUSBIO_PLL_CFG0, reg);
840 DELAY(10);
841
842 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
843 WR4(sc, XUSBIO_PLL_CFG0, reg);
844
845
846 /* Enable and start SATA PLL HW control */
847 RD4(sc, SATA_PLL_CFG0, ®);
848 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
849 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;
850 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
851 reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
852 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;
853 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;
854 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;
855 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;
856 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;
857 WR4(sc, SATA_PLL_CFG0, reg);
858 DELAY(10);
859 reg |= SATA_PLL_CFG0_SEQ_ENABLE;
860 WR4(sc, SATA_PLL_CFG0, reg);
861
862 /* Enable HW control of PCIe PLL. */
863 RD4(sc, PCIE_PLL_CFG, ®);
864 reg |= PCIE_PLL_CFG_SEQ_ENABLE;
865 WR4(sc, PCIE_PLL_CFG, reg);
866
867 return (0);
868 }
869
870 static int
tegra210_pll_set_gate(struct clknode * clknode,bool enable)871 tegra210_pll_set_gate(struct clknode *clknode, bool enable)
872 {
873 int rv;
874 struct pll_sc *sc;
875
876 sc = clknode_get_softc(clknode);
877 if (enable == 0) {
878 rv = pll_disable(sc);
879 return(rv);
880 }
881
882 if (sc->type == PLL_E)
883 rv = plle_enable(sc);
884 else
885 rv = pll_enable(sc);
886 return (rv);
887 }
888
889 static int
pll_set_std(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags,uint32_t m,uint32_t n,uint32_t p)890 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
891 uint32_t m, uint32_t n, uint32_t p)
892 {
893 uint32_t reg;
894 struct mnp_bits *mnp_bits;
895 int rv;
896
897 mnp_bits = &sc->mnp_bits;
898 if (m >= (1 << mnp_bits->m_width))
899 return (ERANGE);
900 if (n >= (1 << mnp_bits->n_width))
901 return (ERANGE);
902 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
903 return (ERANGE);
904
905 if (flags & CLK_SET_DRYRUN) {
906 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
907 (*fout != (((fin / m) * n) /p)))
908 return (ERANGE);
909
910 *fout = ((fin / m) * n) /p;
911
912 return (0);
913 }
914
915 pll_disable(sc);
916
917 /* take pll out of IDDQ */
918 if (sc->iddq_reg != 0)
919 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);
920
921 RD4(sc, sc->base_reg, ®);
922 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width);
923 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width);
924 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
925 mnp_bits->p_width);
926 WR4(sc, sc->base_reg, reg);
927
928 /* Enable PLL. */
929 RD4(sc, sc->base_reg, ®);
930 reg |= PLL_BASE_ENABLE;
931 WR4(sc, sc->base_reg, reg);
932
933 /* Enable lock detection. */
934 RD4(sc, sc->misc_reg, ®);
935 reg |= sc->lock_enable;
936 WR4(sc, sc->misc_reg, reg);
937
938 rv = wait_for_lock(sc);
939 if (rv != 0) {
940 /* Disable PLL */
941 RD4(sc, sc->base_reg, ®);
942 reg &= ~PLL_BASE_ENABLE;
943 WR4(sc, sc->base_reg, reg);
944 return (rv);
945 }
946 RD4(sc, sc->misc_reg, ®);
947
948 pll_enable(sc);
949 *fout = ((fin / m) * n) / p;
950 return 0;
951 }
952
953 static int
plla_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)954 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
955 {
956 uint32_t m, n, p;
957
958 p = 1;
959 m = 3;
960 n = (*fout * p * m + fin / 2)/ fin;
961 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
962 return (pll_set_std(sc, fin, fout, flags, m, n, p));
963 }
964
965 static int
pllc_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)966 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
967 {
968 uint32_t m, n, p;
969
970 p = 2;
971 m = 3;
972 n = (*fout * p * m + fin / 2)/ fin;
973 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
974 return (pll_set_std( sc, fin, fout, flags, m, n, p));
975 }
976
977 static int
pllc4_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)978 pllc4_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
979 {
980 uint32_t m, n, p;
981
982 p = 1;
983 m = 4;
984 n = (*fout * p * m + fin / 2)/ fin;
985 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
986 return (pll_set_std( sc, fin, fout, flags, m, n, p));
987 }
988
989 static int
plldp_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)990 plldp_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
991 {
992 uint32_t m, n, p;
993
994 p = 1;
995 m = 4;
996 n = (*fout * p * m + fin / 2)/ fin;
997 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
998 return (pll_set_std( sc, fin, fout, flags, m, n, p));
999 }
1000
1001
1002 /*
1003 * PLLD2 is used as source for pixel clock for HDMI.
1004 * We must be able to set it frequency very flexibly and
1005 * precisely (within 5% tolerance limit allowed by HDMI specs).
1006 *
1007 * For this reason, it is necessary to search the full state space.
1008 * Fortunately, thanks to early cycle terminations, performance
1009 * is within acceptable limits.
1010 */
1011 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */
1012 #define PLLD2_PFD_MAX 38400000 /* 38.4 MHz */
1013 #define PLLD2_VCO_MIN 750000000 /* 750 MHz */
1014 #define PLLD2_VCO_MAX 1500000000 /* 1.5 GHz */
1015
1016 static int
plld2_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)1017 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
1018 {
1019 uint32_t m, n, p;
1020 uint32_t best_m, best_n, best_p;
1021 uint64_t vco, pfd;
1022 int64_t err, best_err;
1023 struct mnp_bits *mnp_bits;
1024 struct pdiv_table *tbl;
1025 int p_idx, rv;
1026
1027 mnp_bits = &sc->mnp_bits;
1028 tbl = sc->pdiv_table;
1029 best_err = INT64_MAX;
1030
1031 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) {
1032 p = tbl[p_idx].divider;
1033
1034 /* Check constraints */
1035 vco = *fout * p;
1036 if (vco < PLLD2_VCO_MIN)
1037 continue;
1038 if (vco > PLLD2_VCO_MAX)
1039 break;
1040
1041 for (m = 1; m < (1 << mnp_bits->m_width); m++) {
1042 n = (*fout * p * m + fin / 2) / fin;
1043
1044 /* Check constraints */
1045 if (n == 0)
1046 continue;
1047 if (n >= (1 << mnp_bits->n_width))
1048 break;
1049 vco = (fin * n) / m;
1050 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN)
1051 continue;
1052 pfd = fin / m;
1053 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN)
1054 continue;
1055
1056 /* Constraints passed, save best result */
1057 err = *fout - vco / p;
1058 if (err < 0)
1059 err = -err;
1060 if (err < best_err) {
1061 best_err = err;
1062 best_p = p;
1063 best_m = m;
1064 best_n = n;
1065 }
1066 if (err == 0)
1067 goto done;
1068 }
1069 }
1070 done:
1071 /*
1072 * HDMI specification allows 5% pixel clock tolerance,
1073 * we will by a slightly stricter
1074 */
1075 if (best_err > ((*fout * 100) / 4))
1076 return (ERANGE);
1077
1078 if (flags & CLK_SET_DRYRUN)
1079 return (0);
1080 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
1081 /* XXXX Panic for rv == ERANGE ? */
1082 return (rv);
1083 }
1084
1085 static int
pllrefe_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)1086 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
1087 {
1088 uint32_t m, n, p;
1089
1090 m = 1;
1091 p = 1;
1092 n = *fout * p * m / fin;
1093 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
1094 return (pll_set_std(sc, fin, fout, flags, m, n, p));
1095 }
1096
1097 #define PLLX_PFD_MIN 12000000LL /* 12 MHz */
1098 #define PLLX_PFD_MAX 38400000LL /* 38.4 MHz */
1099 #define PLLX_VCO_MIN 900000000LL /* 0.9 GHz */
1100 #define PLLX_VCO_MAX 3000000000LL /* 3 GHz */
1101
1102 static int
pllx_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)1103 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
1104 {
1105 struct mnp_bits *mnp_bits;
1106 uint32_t m, n, p;
1107 uint32_t old_m, old_n, old_p;
1108 uint32_t reg;
1109 int i, rv;
1110
1111 mnp_bits = &sc->mnp_bits;
1112
1113 get_divisors(sc, &old_m, &old_n, &old_p);
1114 old_p = reg_to_pdiv(sc, old_p);
1115
1116 /* Pre-divider is fixed, Compute post-divider */
1117 m = old_m;
1118 p = 1;
1119 while ((*fout * p) < PLLX_VCO_MIN)
1120 p++;
1121 if ((*fout * p) > PLLX_VCO_MAX)
1122 return (ERANGE);
1123
1124 n = (*fout * p * m + fin / 2) / fin;
1125 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
1126
1127 if (m >= (1 << mnp_bits->m_width))
1128 return (ERANGE);
1129 if (n >= (1 << mnp_bits->n_width))
1130 return (ERANGE);
1131 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
1132 return (ERANGE);
1133
1134 if (flags & CLK_SET_DRYRUN) {
1135 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
1136 (*fout != (((fin / m) * n) /p)))
1137 return (ERANGE);
1138 *fout = ((fin / m) * n) /p;
1139 return (0);
1140 }
1141
1142 /* If new post-divider is bigger that original, set it now. */
1143 if (p < old_p) {
1144 RD4(sc, sc->base_reg, ®);
1145 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
1146 mnp_bits->p_width);
1147 WR4(sc, sc->base_reg, reg);
1148 }
1149 DELAY(100);
1150
1151 /* vvv Program dynamic VCO ramp. vvv */
1152 /* 1 - disable dynamic ramp mode. */
1153 RD4(sc, PLLX_MISC_2, ®);
1154 reg &= ~PLLX_MISC_2_EN_DYNRAMP;
1155 WR4(sc, PLLX_MISC_2, reg);
1156
1157 /* 2 - Setup new ndiv. */
1158 RD4(sc, PLLX_MISC_2, ®);
1159 reg &= ~PLLX_MISC_2_NDIV_NEW(~0);
1160 reg |= PLLX_MISC_2_NDIV_NEW(n);
1161 WR4(sc, PLLX_MISC_2, reg);
1162
1163 /* 3 - enable dynamic ramp. */
1164 RD4(sc, PLLX_MISC_2, ®);
1165 reg |= PLLX_MISC_2_EN_DYNRAMP;
1166 WR4(sc, PLLX_MISC_2, reg);
1167
1168 /* 4 - wait for done. */
1169 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
1170 RD4(sc, PLLX_MISC_2, ®);
1171 if (reg & PLLX_MISC_2_DYNRAMP_DONE)
1172 break;
1173 DELAY(10);
1174 }
1175 if (i <= 0) {
1176 printf("PLL X dynamic ramp timedout\n");
1177 return (ETIMEDOUT);
1178 }
1179
1180 /* 5 - copy new ndiv to base register. */
1181 RD4(sc, sc->base_reg, ®);
1182 reg = set_masked(reg, n, mnp_bits->n_shift,
1183 mnp_bits->n_width);
1184 WR4(sc, sc->base_reg, reg);
1185
1186 /* 6 - disable dynamic ramp mode. */
1187 RD4(sc, PLLX_MISC_2, ®);
1188 reg &= ~PLLX_MISC_2_EN_DYNRAMP;
1189 WR4(sc, PLLX_MISC_2, reg);
1190
1191 rv = wait_for_lock(sc);
1192 if (rv != 0) {
1193 printf("PLL X is not locked !!\n");
1194 }
1195 /* ^^^ Dynamic ramp done. ^^^ */
1196
1197 /* If new post-divider is smaller that original, set it. */
1198 if (p > old_p) {
1199 RD4(sc, sc->base_reg, ®);
1200 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
1201 mnp_bits->p_width);
1202 WR4(sc, sc->base_reg, reg);
1203 }
1204
1205 *fout = ((fin / m) * n) / p;
1206 return (0);
1207 }
1208
1209 /* Simplified setup for 38.4 MHz clock. */
1210 #define PLLX_STEP_A 0x04
1211 #define PLLX_STEP_B 0x05
1212 static int
pllx_init(struct pll_sc * sc)1213 pllx_init(struct pll_sc *sc)
1214 {
1215 uint32_t reg;
1216
1217 RD4(sc, PLLX_MISC, ®);
1218 reg = PLLX_MISC_LOCK_ENABLE;
1219 WR4(sc, PLLX_MISC, reg);
1220
1221 /* Setup dynamic ramp. */
1222 reg = 0;
1223 reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A);
1224 reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B);
1225 WR4(sc, PLLX_MISC_2, reg);
1226
1227 /* Disable SDM. */
1228 reg = 0;
1229 WR4(sc, PLLX_MISC_4, reg);
1230 WR4(sc, PLLX_MISC_5, reg);
1231
1232 return (0);
1233 }
1234
1235 static int
tegra210_pll_set_freq(struct clknode * clknode,uint64_t fin,uint64_t * fout,int flags,int * stop)1236 tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
1237 int flags, int *stop)
1238 {
1239 *stop = 1;
1240 int rv;
1241 struct pll_sc *sc;
1242
1243 sc = clknode_get_softc(clknode);
1244 dprintf("%s: %s requested freq: %lu, input freq: %lu\n", __func__,
1245 clknode_get_name(clknode), *fout, fin);
1246 switch (sc->type) {
1247 case PLL_A:
1248 rv = plla_set_freq(sc, fin, fout, flags);
1249 break;
1250
1251 case PLL_C:
1252 case PLL_C2:
1253 case PLL_C3:
1254 rv = pllc_set_freq(sc, fin, fout, flags);
1255 break;
1256
1257 case PLL_C4:
1258 rv = pllc4_set_freq(sc, fin, fout, flags);
1259 break;
1260
1261 case PLL_D2:
1262 rv = plld2_set_freq(sc, fin, fout, flags);
1263 break;
1264
1265 case PLL_DP:
1266 rv = plldp_set_freq(sc, fin, fout, flags);
1267 break;
1268
1269 case PLL_REFE:
1270 rv = pllrefe_set_freq(sc, fin, fout, flags);
1271 break;
1272
1273 case PLL_X:
1274 rv = pllx_set_freq(sc, fin, fout, flags);
1275 break;
1276
1277 case PLL_U:
1278 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */
1279 rv = 0;
1280 else
1281 rv = ERANGE;
1282 break;
1283 default:
1284 rv = ENXIO;
1285 break;
1286 }
1287
1288 return (rv);
1289 }
1290
1291
1292 static int
tegra210_pll_init(struct clknode * clk,device_t dev)1293 tegra210_pll_init(struct clknode *clk, device_t dev)
1294 {
1295 struct pll_sc *sc;
1296 uint32_t reg, rv;
1297
1298 sc = clknode_get_softc(clk);
1299
1300 if (sc->type == PLL_X) {
1301 rv = pllx_init(sc);
1302 if (rv != 0)
1303 return (rv);
1304 }
1305
1306 /* If PLL is enabled, enable lock detect too. */
1307 RD4(sc, sc->base_reg, ®);
1308 if (reg & PLL_BASE_ENABLE) {
1309 RD4(sc, sc->misc_reg, ®);
1310 reg |= sc->lock_enable;
1311 WR4(sc, sc->misc_reg, reg);
1312 }
1313 if (sc->type == PLL_REFE) {
1314 RD4(sc, sc->misc_reg, ®);
1315 reg &= ~(1 << 29); /* Disable lock override */
1316 WR4(sc, sc->misc_reg, reg);
1317 }
1318 clknode_init_parent_idx(clk, 0);
1319 return(0);
1320 }
1321
1322 static int
tegra210_pll_recalc(struct clknode * clk,uint64_t * freq)1323 tegra210_pll_recalc(struct clknode *clk, uint64_t *freq)
1324 {
1325 struct pll_sc *sc;
1326 uint32_t m, n, p, pr;
1327 uint32_t reg, misc_reg;
1328 int locked;
1329
1330 sc = clknode_get_softc(clk);
1331
1332 RD4(sc, sc->base_reg, ®);
1333 RD4(sc, sc->misc_reg, &misc_reg);
1334
1335 get_divisors(sc, &m, &n, &pr);
1336
1337 /* If VCO is directlu exposed, P divider is handled by external node */
1338 if (sc->flags & PLL_FLAG_VCO_OUT)
1339 p = 1;
1340 else
1341 p = reg_to_pdiv(sc, pr);
1342
1343 locked = is_locked(sc);
1344
1345 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): "
1346 "e: %d, r: %d, o: %d - %s\n", __func__,
1347 clknode_get_name(clk), reg, misc_reg, m, n, p, pr,
1348 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,
1349 locked ? "locked" : "unlocked");
1350
1351 if ((m == 0) || (n == 0) || (p == 0)) {
1352 *freq = 0;
1353 return (EINVAL);
1354 }
1355 if (!locked) {
1356 *freq = 0;
1357 return (0);
1358 }
1359 *freq = ((*freq / m) * n) / p;
1360 return (0);
1361 }
1362
1363 static int
pll_register(struct clkdom * clkdom,struct clk_pll_def * clkdef)1364 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef)
1365 {
1366 struct clknode *clk;
1367 struct pll_sc *sc;
1368
1369 clk = clknode_create(clkdom, &tegra210_pll_class, &clkdef->clkdef);
1370 if (clk == NULL)
1371 return (ENXIO);
1372
1373 sc = clknode_get_softc(clk);
1374 sc->clkdev = clknode_get_device(clk);
1375 sc->type = clkdef->type;
1376 sc->base_reg = clkdef->base_reg;
1377 sc->misc_reg = clkdef->misc_reg;
1378 sc->lock_enable = clkdef->lock_enable;
1379 sc->iddq_reg = clkdef->iddq_reg;
1380 sc->iddq_mask = clkdef->iddq_mask;
1381 sc->flags = clkdef->flags;
1382 sc->pdiv_table = clkdef->pdiv_table;
1383 sc->mnp_bits = clkdef->mnp_bits;
1384 clknode_register(clkdom, clk);
1385 return (0);
1386 }
1387
config_utmi_pll(struct tegra210_car_softc * sc)1388 static void config_utmi_pll(struct tegra210_car_softc *sc)
1389 {
1390 uint32_t reg;
1391 /*
1392 * XXX Simplified UTMIP settings for 38.4MHz base clock.
1393 */
1394 #define ENABLE_DELAY_COUNT 0x00
1395 #define STABLE_COUNT 0x00
1396 #define ACTIVE_DELAY_COUNT 0x06
1397 #define XTAL_FREQ_COUNT 0x80
1398
1399 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1400 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1401 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1402
1403 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®);
1404 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1405 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);
1406 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1407 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);
1408 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
1409
1410 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1411 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1412 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);
1413 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1414 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);
1415 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1416 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1417
1418 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1419 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1420 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1421 DELAY(20);
1422
1423 /* Setup samplers. */
1424 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®);
1425 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
1426 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
1427 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
1428 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1429 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1430 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
1431 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
1432
1433 /* Powerup UTMIP. */
1434 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1435 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1436 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1437 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1438 DELAY(10);
1439
1440 /* Prepare UTMIP sequencer. */
1441 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1442 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1443 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1444 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1445 DELAY(10);
1446
1447 CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, ®);
1448 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
1449 CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg);
1450 DELAY(10);
1451
1452 /* HW control of UTMIPLL. */
1453 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1454 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1455 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1456 }
1457
1458 void
tegra210_init_plls(struct tegra210_car_softc * sc)1459 tegra210_init_plls(struct tegra210_car_softc *sc)
1460 {
1461 int i, rv;
1462
1463 for (i = 0; i < nitems(tegra210_pll_sources); i++) {
1464 rv = clknode_mux_register(sc->clkdom, tegra210_pll_sources + i);
1465 if (rv != 0)
1466 panic("clk_mux_register failed");
1467 }
1468
1469 for (i = 0; i < nitems(pll_clks); i++) {
1470 rv = pll_register(sc->clkdom, pll_clks + i);
1471 if (rv != 0)
1472 panic("pll_register failed");
1473 }
1474
1475 config_utmi_pll(sc);
1476
1477 for (i = 0; i < nitems(tegra210_pll_fdivs); i++) {
1478 rv = clknode_fixed_register(sc->clkdom, tegra210_pll_fdivs + i);
1479 if (rv != 0)
1480 panic("clk_fixed_register failed");
1481 }
1482
1483 for (i = 0; i < nitems(tegra210_pll_gates); i++) {
1484 rv = clknode_gate_register(sc->clkdom, tegra210_pll_gates + i);
1485 if (rv != 0)
1486 panic("clk_gate_register failed");
1487 }
1488
1489 for (i = 0; i < nitems(tegra210_pll_divs); i++) {
1490 rv = clknode_div_register(sc->clkdom, tegra210_pll_divs + i);
1491 if (rv != 0)
1492 panic("clk_div_register failed");
1493 }
1494 }
1495