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/f-stack/freebsd/contrib/dev/acpica/components/utilities/
H A Dutcache.c196 if (!Cache) in AcpiOsCreateCache()
208 *ReturnCache = Cache; in AcpiOsCreateCache()
236 if (!Cache) in AcpiOsPurgeCache()
249 while (Cache->ListHead) in AcpiOsPurgeCache()
298 AcpiOsFree (Cache); in AcpiOsDeleteCache()
328 if (!Cache || !Object) in AcpiOsReleaseObject()
335 if (Cache->CurrentDepth >= Cache->MaxDepth) in AcpiOsReleaseObject()
393 if (!Cache) in AcpiOsAcquireObject()
408 if (Cache->ListHead) in AcpiOsAcquireObject()
439 if ((Cache->TotalAllocated - Cache->TotalFreed) > Cache->MaxOccupied) in AcpiOsAcquireObject()
[all …]
H A Duttrack.c215 ACPI_MEMORY_LIST *Cache; in AcpiUtCreateList() local
218 Cache = AcpiOsAllocateZeroed (sizeof (ACPI_MEMORY_LIST)); in AcpiUtCreateList()
219 if (!Cache) in AcpiUtCreateList()
224 Cache->ListName = ListName; in AcpiUtCreateList()
225 Cache->ObjectSize = ObjectSize; in AcpiUtCreateList()
227 *ReturnCache = Cache; in AcpiUtCreateList()
/f-stack/freebsd/contrib/dev/acpica/compiler/
H A Daslcache.c182 ASL_CACHE_INFO *Cache; in UtLocalCacheCalloc() local
192 Cache = UtLocalCalloc (sizeof (Cache->Next) + CacheSize); in UtLocalCacheCalloc()
204 return (Cache->Buffer); in UtLocalCacheCalloc()
212 Cache = UtLocalCalloc (sizeof (Cache->Next) + CacheSize); in UtLocalCacheCalloc()
252 ASL_CACHE_INFO *Cache; in UtParseOpCacheCalloc() local
259 Cache = UtLocalCalloc (sizeof (Cache->Next) + in UtParseOpCacheCalloc()
296 ASL_CACHE_INFO *Cache; in UtSubtableCacheCalloc() local
303 Cache = UtLocalCalloc (sizeof (Cache->Next) + in UtSubtableCacheCalloc()
340 ASL_CACHE_INFO *Cache; in UtFieldCacheCalloc() local
347 Cache = UtLocalCalloc (sizeof (Cache->Next) + in UtFieldCacheCalloc()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,llcc.yaml7 title: Last Level Cache Controller
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
17 common pool of memory. Cache memory is divided into partitions called slices
H A Dqcom,saw2.txt42 device for the core (CPU or Cache) the SPM is attached
/f-stack/freebsd/contrib/device-tree/Bindings/riscv/
H A Dsifive-l2-cache.txt1 SiFive L2 Cache Controller
3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
/f-stack/freebsd/contrib/dev/acpica/include/
H A Dacpiosxf.h395 ACPI_CACHE_T *Cache);
401 ACPI_CACHE_T *Cache);
407 ACPI_CACHE_T *Cache);
413 ACPI_CACHE_T *Cache,
H A Dacdebug.h485 ACPI_MEMORY_LIST *Cache);
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dmvebu-core-clock.txt10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
/f-stack/freebsd/contrib/device-tree/src/powerpc/fsl/
H A De5500_power_isa.dtsi41 power-isa-cs; // Cache Specification
49 power-isa-ecl; // Embedded Cache Locking
57 fsl,eref-deo; // Data Cache Extended Operations
H A De500mc_power_isa.dtsi41 power-isa-cs; // Cache Specification
49 power-isa-ecl; // Embedded Cache Locking
56 fsl,eref-deo; // Data Cache Extended Operations
H A De6500_power_isa.dtsi41 power-isa-cs; // Cache Specification
49 power-isa-ecl; // Embedded Cache Locking
62 fsl,eref-deo; // Data Cache Extended Operations
H A De500v2_power_isa.dtsi41 power-isa-cs; // Cache Specification
44 power-isa-ecl; // Embedded Cache Locking
/f-stack/freebsd/contrib/device-tree/Bindings/arm/mrvl/
H A Dferoceon.txt1 * Marvell Feroceon Cache
H A Dtauros2.txt1 * Marvell Tauros2 Cache
/f-stack/freebsd/contrib/device-tree/Bindings/perf/
H A Darm-ccn.txt1 * ARM CCN (Cache Coherent Network)
/f-stack/freebsd/contrib/dev/acpica/components/debugger/
H A Ddbexec.c425 ACPI_MEMORY_LIST *Cache) in AcpiDbGetCacheInfo() argument
428 return (Cache->TotalAllocated - Cache->TotalFreed - Cache->CurrentDepth); in AcpiDbGetCacheInfo()
/f-stack/freebsd/contrib/device-tree/Bindings/powerpc/fsl/
H A Dcache_sram.txt1 * Freescale PQ3 and QorIQ based Cache SRAM
H A Dl2cache.txt1 Freescale L2 Cache Controller
/f-stack/freebsd/contrib/device-tree/Bindings/interrupt-controller/
H A Dst,sti-irq-syscfg.txt5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
/f-stack/freebsd/contrib/device-tree/Bindings/mips/cavium/
H A Dsata-uctl.txt8 buffers from Level 2 Cache.
/f-stack/freebsd/arm/conf/
H A DARMADA38X94 # L2 Cache
H A DALPINE35 device al_ccu # Alpine Cache Coherency Unit
H A DZEDBOARD45 # Cache controller
/f-stack/app/redis-5.0.5/deps/hiredis/
H A Dappveyor.yml19 # Cache Cygwin files to speed up build

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