1 /***********************license start***************
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38 ***********************license end**************************************/
39
40
41
42
43
44
45
46
47 /**
48 * @file
49 *
50 * Interface to the Trace buffer hardware.
51 *
52 * WRITING THE TRACE BUFFER
53 *
54 * When the trace is enabled, commands are traced continuously (wrapping) or until the buffer is filled once
55 * (no wrapping). Additionally and independent of wrapping, tracing can be temporarily enabled and disabled
56 * by the tracing triggers. All XMC commands can be traced except for IDLE and IOBRSP. The subset of XMC
57 * commands that are traced is determined by the filter and the two triggers, each of which is comprised of
58 * masks for command, sid, did, and address). If triggers are disabled, then only those commands matching
59 * the filter are traced. If triggers are enabled, then only those commands matching the filter, the start
60 * trigger, or the stop trigger are traced during the time between a start trigger and a stop trigger.
61 *
62 * For a given command, its XMC data is written immediately to the buffer. If the command has XMD data,
63 * then that data comes in-order at some later time. The XMD data is accumulated across all valid
64 * XMD cycles and written to the buffer or to a shallow fifo. Data from the fifo is written to the buffer
65 * as soon as it gets access to write the buffer (i.e. the buffer is not currently being written with XMC
66 * data). If the fifo overflows, it simply overwrites itself and the previous XMD data is lost.
67 *
68 *
69 * READING THE TRACE BUFFER
70 *
71 * Each entry of the trace buffer is read by a CSR read command. The trace buffer services each read in order,
72 * as soon as it has access to the (single-ported) trace buffer.
73 *
74 * On Octeon2, each entry of the trace buffer is read by two CSR memory read operations. The first read accesses
75 * bits 63:0 of the buffer entry, and the second read accesses bits 68:64 of the buffer entry. The trace buffer
76 * services each read in order, as soon as it has access to the (single-ported) trace buffer. Buffer's read pointer
77 * increments after two CSR memory read operations.
78 *
79 *
80 * OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS
81 *
82 * The trace buffer maintains a write pointer and a read pointer and detects both the overflow and underflow
83 * conditions. Each time a new trace is enabled, both pointers are reset to entry 0. Normally, each write
84 * (traced event) increments the write pointer and each read increments the read pointer. During the overflow
85 * condition, writing (tracing) is disabled. Tracing will continue as soon as the overflow condition is
86 * resolved. The first entry that is written immediately following the overflow condition may be marked to
87 * indicate that a tracing discontinuity has occurred before this entry. During the underflow condition,
88 * reading does not increment the read pointer and the read data is marked to indicate that no read data is
89 * available.
90 *
91 * The full threshold events are defined to signal an interrupt a certain levels of "fullness" (1/2, 3/4, 4/4).
92 * "fullness" is defined as the relative distance between the write and read pointers (i.e. not defined as the
93 * absolute distance between the write pointer and entry 0). When enabled, the full threshold event occurs
94 * every time the desired level of "fullness" is achieved.
95 *
96 *
97 * Trace buffer entry format
98 * @verbatim
99 * 6 5 4 3 2 1 0
100 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
101 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
102 * |sta| address[35:3] | 0 | src id | 0 | DWB | diff timestamp|
103 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
104 * |sta| address[35:3] | 0 | src id | 0 | PL2 | diff timestamp|
105 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
106 * |sta| address[35:3] | 0 | src id | 0 | PSL1 | diff timestamp|
107 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
108 * |sta| address[35:3] | 0 | src id | 0 | LDD | diff timestamp|
109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
110 * |sta| address[35:3] | 0 | src id | 0 | LDI | diff timestamp|
111 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
112 * |sta| address[35:3] | 0 | src id | 0 | LDT | diff timestamp|
113 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
114 * |sta| address[35:3] | * or 16B mask | src id | 0 | STC | diff timestamp|
115 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
116 * |sta| address[35:3] | * or 16B mask | src id | 0 | STF | diff timestamp|
117 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
118 * |sta| address[35:3] | * or 16B mask | src id | 0 | STP | diff timestamp|
119 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
120 * |sta| address[35:3] | * or 16B mask | src id | 0 | STT | diff timestamp|
121 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
122 * |sta| address[35:0] | 0 | src id| dest id |IOBLD8 | diff timestamp|
123 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
124 * |sta| address[35:1] | 0 | src id| dest id |IOBLD16| diff timestamp|
125 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
126 * |sta| address[35:2] | 0 | src id| dest id |IOBLD32| diff timestamp|
127 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
128 * |sta| address[35:3] | 0 | src id| dest id |IOBLD64| diff timestamp|
129 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
130 * |sta| address[35:3] | * or 16B mask | src id| dest id |IOBST | diff timestamp|
131 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
132 * |sta| * or address[35:3] | * or length | src id| dest id |IOBDMA | diff timestamp|
133 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
134 *
135 *
136 * Trace buffer entry format in Octeon2 is different
137 *
138 * 6 5 4 3 2 1 0
139 * 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
140 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
141 * |sta| address[37:0] | 0 | src id | Group 1 | diff timestamp|
142 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
143 * |sta| address[37:0] | 0 | xmd mask | src id | Group 2 | diff timestamp|
144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 * |sta| address[37:0] | 0 |s-did| dest id | src id | Group 3 | diff timestamp|
146 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
147 * |sta| *address[37:3] | *Length | dest id | src id | Group 4 | diff timestamp|
148 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
149 *
150 * notes:
151 * - diff timestamp is the difference in time from the previous trace event to this event - 1. the granularity of the timestamp is programmable
152 * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time. Note that the
153 * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'.
154 * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows:
155 * 0x0=not valid
156 * 0x1=valid, no discontinuity
157 * 0x2=not valid, discontinuity
158 * 0x3=valid, discontinuity
159 * - commands are encoded as follows:
160 * 0x0=DWB
161 * 0x1=PL2
162 * 0x2=PSL1
163 * 0x3=LDD
164 * 0x4=LDI
165 * 0x5=LDT
166 * 0x6=STF
167 * 0x7=STC
168 * 0x8=STP
169 * 0x9=STT
170 * 0xa=IOBLD8
171 * 0xb=IOBLD16
172 * 0xc=IOBLD32
173 * 0xd=IOBLD64
174 * 0xe=IOBST
175 * 0xf=IOBDMA
176 * - In Octeon2 the commands are grouped as follows:
177 * Group1:
178 * XMC_LDT, XMC_LDI, XMC_PL2, XMC_RPL2, XMC_DWB, XMC_WBL2,
179 * XMC_SET8, XMC_SET16, XMC_SET32, XMC_SET64,
180 * XMC_CLR8, XMC_CLR16, XMC_CLR32, XMC_CLR64,
181 * XMC_INCR8, XMC_INCR16, XMC_INCR32, XMC_INCR64,
182 * XMC_DECR8, XMC_DECR16, XMC_DECR32, XMC_DECR64
183 * Group2:
184 * XMC_STF, XMC_STT, XMC_STP, XMC_STC,
185 * XMC_LDD, XMC_PSL1
186 * XMC_SAA32, XMC_SAA64,
187 * XMC_FAA32, XMC_FAA64,
188 * XMC_FAS32, XMC_FAS64
189 * Group3:
190 * XMC_IOBLD8, XMC_IOBLD16, XMC_IOBLD32, XMC_IOBLD64,
191 * XMC_IOBST8, XMC_IOBST16, XMC_IOBST32, XMC_IOBST64
192 * Group4:
193 * XMC_IOBDMA
194 * - For non IOB* commands
195 * - source id is encoded as follows:
196 * 0x00-0x0f=PP[n]
197 * 0x10=IOB(Packet)
198 * 0x11=IOB(PKO)
199 * 0x12=IOB(ReqLoad, ReqStore)
200 * 0x13=IOB(DWB)
201 * 0x14-0x1e=illegal
202 * 0x1f=IOB(generic)
203 * - dest id is unused (can only be L2c)
204 * - For IOB* commands
205 * - source id is encoded as follows:
206 * 0x00-0x0f = PP[n]
207 * - dest id is encoded as follows:
208 * 0 = CIU/GPIO (for CSRs)
209 * 1-2 = illegal
210 * 3 = PCIe (access to RSL-type CSRs)
211 * 4 = KEY (read/write operations)
212 * 5 = FPA (free pool allocate/free operations)
213 * 6 = DFA
214 * 7 = ZIP (doorbell operations)
215 * 8 = RNG (load/IOBDMA operations)
216 * 10 = PKO (doorbell operations)
217 * 11 = illegal
218 * 12 = POW (get work, add work, status/memory/index loads, NULLrd load operations, CSR operations)
219 * 13-31 = illegal
220 * @endverbatim
221 *
222 * <hr>$Revision: 70030 $<hr>
223 */
224
225 #ifndef __CVMX_TRA_H__
226 #define __CVMX_TRA_H__
227
228 #include "cvmx.h"
229 #include "cvmx-l2c.h"
230 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
231 #include "cvmx-tra-defs.h"
232 #endif
233
234 #ifdef __cplusplus
235 extern "C" {
236 #endif
237
238
239 /* CSR typedefs have been moved to cvmx-tra-defs.h */
240
241 /* The 'saa' filter command is renamed as 'saa64' */
242 #define CVMX_TRA_FILT_SAA CVMX_TRA_FILT_SAA64
243 /* The 'iobst' filter command is renamed as 'iobst64' */
244 #define CVMX_TRA_FILT_IOBST CVMX_TRA_FILT_IOBST64
245
246 /**
247 * Enumeration of the bitmask of all the filter commands. The bit positions
248 * correspond to Octeon2 model.
249 */
250 typedef enum
251 {
252 CVMX_TRA_FILT_NOP = 1ull<<0, /**< none */
253 CVMX_TRA_FILT_LDT = 1ull<<1, /**< don't allocate L2 or L1 */
254 CVMX_TRA_FILT_LDI = 1ull<<2, /**< don't allocate L1 */
255 CVMX_TRA_FILT_PL2 = 1ull<<3, /**< pref L2 */
256 CVMX_TRA_FILT_RPL2 = 1ull<<4, /**< mark for replacement in L2 */
257 CVMX_TRA_FILT_DWB = 1ull<<5, /**< clear L2 dirty bit (no writeback) + RPL2 */
258 CVMX_TRA_FILT_LDD = 1ull<<8, /**< normal load */
259 CVMX_TRA_FILT_PSL1 = 1ull<<9, /**< pref L1, bypass L2 */
260 CVMX_TRA_FILT_IOBDMA = 1ull<<15, /**< store reflection by IOB for prior load */
261 CVMX_TRA_FILT_STF = 1ull<<16, /**< full block store to L2, fill 0's */
262 CVMX_TRA_FILT_STT = 1ull<<17, /**< full block store bypass-L2, fill 0's */
263 CVMX_TRA_FILT_STP = 1ull<<18, /**< partial store to L2 */
264 CVMX_TRA_FILT_STC = 1ull<<19, /**< partial store to L2, if duptag valid */
265 CVMX_TRA_FILT_STFIL1 = 1ull<<20, /**< full block store to L2, fill 0's, invalidate L1 */
266 CVMX_TRA_FILT_STTIL1 = 1ull<<21, /**< full block store bypass-L2, fill 0's, invalidate L1 */
267 CVMX_TRA_FILT_FAS32 = 1ull<<22, /**< to load from and write a word of memory atomically */
268 CVMX_TRA_FILT_FAS64 = 1ull<<23, /**< to load from and write a doubleword of memory atomically */
269 CVMX_TRA_FILT_WBIL2I = 1ull<<24, /**< writeback if dirty, invalidate, clear use bit, by index/way */
270 CVMX_TRA_FILT_LTGL2I = 1ull<<25, /**< read tag @ index/way into CSR */
271 CVMX_TRA_FILT_STGL2I = 1ull<<26, /**< write tag @ index/way from CSR */
272 CVMX_TRA_FILT_INVL2 = 1ull<<28, /**< invalidate, clear use bit, by address (dirty data is LOST) */
273 CVMX_TRA_FILT_WBIL2 = 1ull<<29, /**< writeback if dirty, invalidate, clear use bit, by address */
274 CVMX_TRA_FILT_WBL2 = 1ull<<30, /**< writeback if dirty, make clean, clear use bit, by address */
275 CVMX_TRA_FILT_LCKL2 = 1ull<<31, /**< allocate (if miss), set lock bit, set use bit, by address */
276 CVMX_TRA_FILT_IOBLD8 = 1ull<<32, /**< load reflection 8bit */
277 CVMX_TRA_FILT_IOBLD16 = 1ull<<33, /**< load reflection 16bit */
278 CVMX_TRA_FILT_IOBLD32 = 1ull<<34, /**< load reflection 32bit */
279 CVMX_TRA_FILT_IOBLD64 = 1ull<<35, /**< load reflection 64bit */
280 CVMX_TRA_FILT_IOBST8 = 1ull<<36, /**< store reflection 8bit */
281 CVMX_TRA_FILT_IOBST16 = 1ull<<37, /**< store reflection 16bit */
282 CVMX_TRA_FILT_IOBST32 = 1ull<<38, /**< store reflection 32bit */
283 CVMX_TRA_FILT_IOBST64 = 1ull<<39, /**< store reflection 64bit */
284 CVMX_TRA_FILT_SET8 = 1ull<<40, /**< to load from and write 1's to 8bit of memory atomically */
285 CVMX_TRA_FILT_SET16 = 1ull<<41, /**< to load from and write 1's to 16bit of memory atomically */
286 CVMX_TRA_FILT_SET32 = 1ull<<42, /**< to load from and write 1's to 32bit of memory atomically */
287 CVMX_TRA_FILT_SET64 = 1ull<<43, /**< to load from and write 1's to 64bit of memory atomically */
288 CVMX_TRA_FILT_CLR8 = 1ull<<44, /**< to load from and write 0's to 8bit of memory atomically */
289 CVMX_TRA_FILT_CLR16 = 1ull<<45, /**< to load from and write 0's to 16bit of memory atomically */
290 CVMX_TRA_FILT_CLR32 = 1ull<<46, /**< to load from and write 0's to 32bit of memory atomically */
291 CVMX_TRA_FILT_CLR64 = 1ull<<47, /**< to load from and write 0's to 64bit of memory atomically */
292 CVMX_TRA_FILT_INCR8 = 1ull<<48, /**< to load and increment 8bit of memory atomically */
293 CVMX_TRA_FILT_INCR16 = 1ull<<49, /**< to load and increment 16bit of memory atomically */
294 CVMX_TRA_FILT_INCR32 = 1ull<<50, /**< to load and increment 32bit of memory atomically */
295 CVMX_TRA_FILT_INCR64 = 1ull<<51, /**< to load and increment 64bit of memory atomically */
296 CVMX_TRA_FILT_DECR8 = 1ull<<52, /**< to load and decrement 8bit of memory atomically */
297 CVMX_TRA_FILT_DECR16 = 1ull<<53, /**< to load and decrement 16bit of memory atomically */
298 CVMX_TRA_FILT_DECR32 = 1ull<<54, /**< to load and decrement 32bit of memory atomically */
299 CVMX_TRA_FILT_DECR64 = 1ull<<55, /**< to load and decrement 64bit of memory atomically */
300 CVMX_TRA_FILT_FAA32 = 1ull<<58, /**< to load from and add to a word of memory atomically */
301 CVMX_TRA_FILT_FAA64 = 1ull<<59, /**< to load from and add to a doubleword of memory atomically */
302 CVMX_TRA_FILT_SAA32 = 1ull<<62, /**< to atomically add a word to a memory location */
303 CVMX_TRA_FILT_SAA64 = 1ull<<63, /**< to atomically add a doubleword to a memory location */
304 CVMX_TRA_FILT_ALL = -1ull /**< all the above filter commands */
305 } cvmx_tra_filt_t;
306
307 /*
308 * Enumeration of the bitmask of all source commands.
309 */
310 typedef enum
311 {
312 CVMX_TRA_SID_PP0 = 1ull<<0, /**< Enable tracing from PP0 with matching sourceID */
313 CVMX_TRA_SID_PP1 = 1ull<<1, /**< Enable tracing from PP1 with matching sourceID */
314 CVMX_TRA_SID_PP2 = 1ull<<2, /**< Enable tracing from PP2 with matching sourceID */
315 CVMX_TRA_SID_PP3 = 1ull<<3, /**< Enable tracing from PP3 with matching sourceID */
316 CVMX_TRA_SID_PP4 = 1ull<<4, /**< Enable tracing from PP4 with matching sourceID */
317 CVMX_TRA_SID_PP5 = 1ull<<5, /**< Enable tracing from PP5 with matching sourceID */
318 CVMX_TRA_SID_PP6 = 1ull<<6, /**< Enable tracing from PP6 with matching sourceID */
319 CVMX_TRA_SID_PP7 = 1ull<<7, /**< Enable tracing from PP7 with matching sourceID */
320 CVMX_TRA_SID_PP8 = 1ull<<8, /**< Enable tracing from PP8 with matching sourceID */
321 CVMX_TRA_SID_PP9 = 1ull<<9, /**< Enable tracing from PP9 with matching sourceID */
322 CVMX_TRA_SID_PP10 = 1ull<<10, /**< Enable tracing from PP10 with matching sourceID */
323 CVMX_TRA_SID_PP11 = 1ull<<11, /**< Enable tracing from PP11 with matching sourceID */
324 CVMX_TRA_SID_PP12 = 1ull<<12, /**< Enable tracing from PP12 with matching sourceID */
325 CVMX_TRA_SID_PP13 = 1ull<<13, /**< Enable tracing from PP13 with matching sourceID */
326 CVMX_TRA_SID_PP14 = 1ull<<14, /**< Enable tracing from PP14 with matching sourceID */
327 CVMX_TRA_SID_PP15 = 1ull<<15, /**< Enable tracing from PP15 with matching sourceID */
328 CVMX_TRA_SID_PKI = 1ull<<16, /**< Enable tracing of write requests from PIP/IPD */
329 CVMX_TRA_SID_PKO = 1ull<<17, /**< Enable tracing of write requests from PKO */
330 CVMX_TRA_SID_IOBREQ = 1ull<<18, /**< Enable tracing of write requests from FPA,TIM,DFA,PCI,ZIP,POW, and PKO (writes) */
331 CVMX_TRA_SID_DWB = 1ull<<19, /**< Enable tracing of write requests from IOB DWB engine */
332 CVMX_TRA_SID_ALL = -1ull /**< Enable tracing all the above source commands */
333 } cvmx_tra_sid_t;
334
335
336 #define CVMX_TRA_DID_SLI CVMX_TRA_DID_PCI /**< Enable tracing of requests to SLI and RSL-type CSRs. */
337 /*
338 * Enumeration of the bitmask of all destination commands.
339 */
340 typedef enum
341 {
342 CVMX_TRA_DID_MIO = 1ull<<0, /**< Enable tracing of CIU and GPIO CSR's */
343 CVMX_TRA_DID_PCI = 1ull<<3, /**< Enable tracing of requests to PCI and RSL type CSR's */
344 CVMX_TRA_DID_KEY = 1ull<<4, /**< Enable tracing of requests to KEY memory */
345 CVMX_TRA_DID_FPA = 1ull<<5, /**< Enable tracing of requests to FPA */
346 CVMX_TRA_DID_DFA = 1ull<<6, /**< Enable tracing of requests to DFA */
347 CVMX_TRA_DID_ZIP = 1ull<<7, /**< Enable tracing of requests to ZIP */
348 CVMX_TRA_DID_RNG = 1ull<<8, /**< Enable tracing of requests to RNG */
349 CVMX_TRA_DID_IPD = 1ull<<9, /**< Enable tracing of IPD CSR accesses */
350 CVMX_TRA_DID_PKO = 1ull<<10, /**< Enable tracing of PKO accesses (doorbells) */
351 CVMX_TRA_DID_POW = 1ull<<12, /**< Enable tracing of requests to RNG */
352 CVMX_TRA_DID_USB0 = 1ull<<13, /**< Enable tracing of USB0 accesses (UAHC0 EHCI and OHCI NCB CSRs) */
353 CVMX_TRA_DID_RAD = 1ull<<14, /**< Enable tracing of RAD accesses (doorbells) */
354 CVMX_TRA_DID_DPI = 1ull<<27, /**< Enable tracing of DPI accesses (DPI NCD CSRs) */
355 CVMX_TRA_DID_FAU = 1ull<<30, /**< Enable tracing FAU accesses */
356 CVMX_TRA_DID_ALL = -1ull /**< Enable tracing all the above destination commands */
357 } cvmx_tra_did_t;
358
359 /**
360 * TRA data format definition. Use the type field to
361 * determine which union element to use.
362 *
363 * In Octeon 2, the trace buffer is 69 bits,
364 * the first read accesses bits 63:0 of the trace buffer entry, and
365 * the second read accesses bits 68:64 of the trace buffer entry.
366 */
367 typedef union
368 {
369 struct
370 {
371 #ifdef __BIG_ENDIAN_BITFIELD
372 uint64_t datahi;
373 uint64_t data;
374 #else
375 uint64_t data;
376 uint64_t datahi;
377 #endif
378 } u128;
379
380 struct
381 {
382 #ifdef __BIG_ENDIAN_BITFIELD
383 uint64_t reserved3 : 64;
384 uint64_t valid : 1;
385 uint64_t discontinuity:1;
386 uint64_t address : 36;
387 uint64_t reserved : 5;
388 uint64_t source : 5;
389 uint64_t reserved2 : 3;
390 uint64_t type : 5;
391 uint64_t timestamp : 8;
392 #else
393 uint64_t timestamp : 8;
394 uint64_t type : 5;
395 uint64_t reserved2 : 3;
396 uint64_t source : 5;
397 uint64_t reserved : 5;
398 uint64_t address : 36;
399 uint64_t discontinuity:1;
400 uint64_t valid : 1;
401 uint64_t reserved3 : 64;
402 #endif
403 } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */
404 struct
405 {
406 #ifdef __BIG_ENDIAN_BITFIELD
407 uint64_t reserved3 : 64;
408 uint64_t valid : 1;
409 uint64_t discontinuity:1;
410 uint64_t address : 33;
411 uint64_t mask : 8;
412 uint64_t source : 5;
413 uint64_t reserved2 : 3;
414 uint64_t type : 5;
415 uint64_t timestamp : 8;
416 #else
417 uint64_t timestamp : 8;
418 uint64_t type : 5;
419 uint64_t reserved2 : 3;
420 uint64_t source : 5;
421 uint64_t mask : 8;
422 uint64_t address : 33;
423 uint64_t discontinuity:1;
424 uint64_t valid : 1;
425 uint64_t reserved3 : 64;
426 #endif
427 } store; /**< STC, STF, STP, STT */
428 struct
429 {
430 #ifdef __BIG_ENDIAN_BITFIELD
431 uint64_t reserved3 : 64;
432 uint64_t valid : 1;
433 uint64_t discontinuity:1;
434 uint64_t address : 36;
435 uint64_t reserved : 2;
436 uint64_t subid : 3;
437 uint64_t source : 4;
438 uint64_t dest : 5;
439 uint64_t type : 4;
440 uint64_t timestamp : 8;
441 #else
442 uint64_t timestamp : 8;
443 uint64_t type : 4;
444 uint64_t dest : 5;
445 uint64_t source : 4;
446 uint64_t subid : 3;
447 uint64_t reserved : 2;
448 uint64_t address : 36;
449 uint64_t discontinuity:1;
450 uint64_t valid : 1;
451 uint64_t reserved3 : 64;
452 #endif
453 } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */
454 struct
455 {
456 #ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t reserved3 : 64;
458 uint64_t valid : 1;
459 uint64_t discontinuity:1;
460 uint64_t address : 33;
461 uint64_t mask : 8;
462 uint64_t source : 4;
463 uint64_t dest : 5;
464 uint64_t type : 4;
465 uint64_t timestamp : 8;
466 #else
467 uint64_t timestamp : 8;
468 uint64_t type : 4;
469 uint64_t dest : 5;
470 uint64_t source : 4;
471 uint64_t mask : 8;
472 uint64_t address : 33;
473 uint64_t discontinuity:1;
474 uint64_t valid : 1;
475 uint64_t reserved3 : 64;
476 #endif
477 } iob; /**< for IOBDMA */
478
479 struct
480 {
481 #ifdef __BIG_ENDIAN_BITFIELD
482 uint64_t reserved1 : 59;
483 uint64_t discontinuity:1;
484 uint64_t valid : 1;
485 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
486 uint64_t addresslo : 35; /* and lower 64-bits. */
487 uint64_t reserved : 10;
488 uint64_t source : 5;
489 uint64_t type : 6;
490 uint64_t timestamp : 8;
491 #else
492 uint64_t timestamp : 8;
493 uint64_t type : 6;
494 uint64_t source : 5;
495 uint64_t reserved : 10;
496 uint64_t addresslo : 35;
497 uint64_t addresshi : 3;
498 uint64_t valid : 1;
499 uint64_t discontinuity:1;
500 uint64_t reserved1 : 59;
501 #endif
502 } cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, WBIL2i, LTGL2i, STGL2i, INVL2, WBIL2, LCKL2, SET*, CLR*, INCR*, DECR* */
503 struct
504 {
505 #ifdef __BIG_ENDIAN_BITFIELD
506 uint64_t reserved1 : 59;
507 uint64_t discontinuity:1;
508 uint64_t valid : 1;
509 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
510 uint64_t addresslo : 35; /* and lower 64-bits */
511 uint64_t reserved : 2;
512 uint64_t mask : 8;
513 uint64_t source : 5;
514 uint64_t type : 6;
515 uint64_t timestamp : 8;
516 #else
517 uint64_t timestamp : 8;
518 uint64_t type : 6;
519 uint64_t source : 5;
520 uint64_t mask : 8;
521 uint64_t reserved : 2;
522 uint64_t addresslo : 35;
523 uint64_t addresshi : 3;
524 uint64_t valid : 1;
525 uint64_t discontinuity:1;
526 uint64_t reserved1 : 59;
527 #endif
528 } store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64, STTIL1, STFIL1 */
529 struct
530 {
531 #ifdef __BIG_ENDIAN_BITFIELD
532 uint64_t reserved1 : 59;
533 uint64_t discontinuity:1;
534 uint64_t valid : 1;
535 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
536 uint64_t addresslo : 35; /* and lower 64-bits */
537 uint64_t reserved : 2;
538 uint64_t subid : 3;
539 uint64_t dest : 5;
540 uint64_t source : 5;
541 uint64_t type : 6;
542 uint64_t timestamp : 8;
543 #else
544 uint64_t timestamp : 8;
545 uint64_t type : 6;
546 uint64_t source : 5;
547 uint64_t dest : 5;
548 uint64_t subid : 3;
549 uint64_t reserved : 2;
550 uint64_t addresslo : 35;
551 uint64_t addresshi : 3;
552 uint64_t valid : 1;
553 uint64_t discontinuity:1;
554 uint64_t reserved1 : 59;
555 #endif
556 } iobld2; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST64, IOBST32, IOBST16, IOBST8 */
557 struct
558 {
559 #ifdef __BIG_ENDIAN_BITFIELD
560 uint64_t reserved1 : 59;
561 uint64_t discontinuity:1;
562 uint64_t valid : 1;
563 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */
564 uint64_t addresslo : 32; /* and lower 64-bits */
565 uint64_t mask : 8;
566 uint64_t dest : 5;
567 uint64_t source : 5;
568 uint64_t type : 6;
569 uint64_t timestamp : 8;
570 #else
571 uint64_t timestamp : 8;
572 uint64_t type : 6;
573 uint64_t source : 5;
574 uint64_t dest : 5;
575 uint64_t mask : 8;
576 uint64_t addresslo : 32;
577 uint64_t addresshi : 3;
578 uint64_t valid : 1;
579 uint64_t discontinuity:1;
580 uint64_t reserved1 : 59;
581 #endif
582 } iob2; /**< for IOBDMA */
583 } cvmx_tra_data_t;
584
585 /* The trace buffer number to use. */
586 extern int _cvmx_tra_unit;
587
588 /**
589 * Setup the TRA buffer for use
590 *
591 * @param control TRA control setup
592 * @param filter Which events to log
593 * @param source_filter
594 * Source match
595 * @param dest_filter
596 * Destination match
597 * @param address Address compare
598 * @param address_mask
599 * Address mask
600 */
601 extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
602 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
603 uint64_t address, uint64_t address_mask);
604
605 /**
606 * Setup each TRA buffer for use
607 *
608 * @param tra Which TRA buffer to use (0-3)
609 * @param control TRA control setup
610 * @param filter Which events to log
611 * @param source_filter
612 * Source match
613 * @param dest_filter
614 * Destination match
615 * @param address Address compare
616 * @param address_mask
617 * Address mask
618 */
619 extern void cvmx_tra_setup_v2(int tra, cvmx_tra_ctl_t control, cvmx_tra_filt_t filter,
620 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
621 uint64_t address, uint64_t address_mask);
622
623 /**
624 * Setup a TRA trigger. How the triggers are used should be
625 * setup using cvmx_tra_setup.
626 *
627 * @param trigger Trigger to setup (0 or 1)
628 * @param filter Which types of events to trigger on
629 * @param source_filter
630 * Source trigger match
631 * @param dest_filter
632 * Destination trigger match
633 * @param address Trigger address compare
634 * @param address_mask
635 * Trigger address mask
636 */
637 extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter,
638 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
639 uint64_t address, uint64_t address_mask);
640
641 /**
642 * Setup each TRA trigger. How the triggers are used should be
643 * setup using cvmx_tra_setup.
644 *
645 * @param tra Which TRA buffer to use (0-3)
646 * @param trigger Trigger to setup (0 or 1)
647 * @param filter Which types of events to trigger on
648 * @param source_filter
649 * Source trigger match
650 * @param dest_filter
651 * Destination trigger match
652 * @param address Trigger address compare
653 * @param address_mask
654 * Trigger address mask
655 */
656 extern void cvmx_tra_trig_setup_v2(int tra, uint64_t trigger, cvmx_tra_filt_t filter,
657 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter,
658 uint64_t address, uint64_t address_mask);
659
660 /**
661 * Read an entry from the TRA buffer. The trace buffer format is
662 * different in Octeon2, need to read twice from TRA_READ_DAT.
663 *
664 * @return Value return. High bit will be zero if there wasn't any data
665 */
666 extern cvmx_tra_data_t cvmx_tra_read(void);
667
668 /**
669 * Read an entry from the TRA buffer from a given TRA unit.
670 *
671 * @param tra_unit Trace buffer unit to read
672 *
673 * @return Value return. High bit will be zero if there wasn't any data
674 */
675 cvmx_tra_data_t cvmx_tra_read_v2(int tra_unit);
676
677 /**
678 * Decode a TRA entry into human readable output
679 *
680 * @param tra_ctl Trace control setup
681 * @param data Data to decode
682 */
683 extern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data);
684
685 /**
686 * Display the entire trace buffer. It is advised that you
687 * disable the trace buffer before calling this routine
688 * otherwise it could infinitely loop displaying trace data
689 * that it created.
690 */
691 extern void cvmx_tra_display(void);
692
693 /**
694 * Display the entire trace buffer. It is advised that you
695 * disable the trace buffer before calling this routine
696 * otherwise it could infinitely loop displaying trace data
697 * that it created.
698 *
699 * @param tra_unit Which TRA buffer to use.
700 */
701 extern void cvmx_tra_display_v2(int tra_unit);
702
703 /**
704 * Enable or disable the TRA hardware, by default enables all TRAs.
705 *
706 * @param enable 1=enable, 0=disable
707 */
cvmx_tra_enable(int enable)708 static inline void cvmx_tra_enable(int enable)
709 {
710 cvmx_tra_ctl_t control;
711 int tad;
712
713 for (tad = 0; tad < CVMX_L2C_TADS; tad++)
714 {
715 control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tad));
716 control.s.ena = enable;
717 cvmx_write_csr(CVMX_TRAX_CTL(tad), control.u64);
718 cvmx_read_csr(CVMX_TRAX_CTL(tad));
719 }
720 }
721
722 /**
723 * Enable or disable a particular TRA hardware
724 *
725 * @param enable 1=enable, 0=disable
726 * @param tra which TRA to enable, CN68XX has 4.
727 */
cvmx_tra_enable_v2(int enable,int tra)728 static inline void cvmx_tra_enable_v2(int enable, int tra)
729 {
730 cvmx_tra_ctl_t control;
731
732 if ((tra + 1) > CVMX_L2C_TADS)
733 {
734 cvmx_dprintf("cvmx_tra_enable: Invalid TRA(%d), max allowed are %d\n", tra, CVMX_L2C_TADS - 1);
735 tra = 0;
736 }
737 control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tra));
738 control.s.ena = enable;
739 cvmx_write_csr(CVMX_TRAX_CTL(tra), control.u64);
740 cvmx_read_csr(CVMX_TRAX_CTL(tra));
741 }
742
743 #ifdef __cplusplus
744 }
745 #endif
746
747 #endif
748
749