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39
40
41 /**
42 * cvmx-pip-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon pip.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_PIP_DEFS_H__
53 #define __CVMX_PIP_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_ALT_SKIP_CFGX(unsigned long offset)56 static inline uint64_t CVMX_PIP_ALT_SKIP_CFGX(unsigned long offset)
57 {
58 if (!(
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
62 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
63 cvmx_warn("CVMX_PIP_ALT_SKIP_CFGX(%lu) is invalid on this chip\n", offset);
64 return CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8;
65 }
66 #else
67 #define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
68 #endif
69 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
70 #define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC()
CVMX_PIP_BCK_PRS_FUNC(void)71 static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
72 {
73 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
74 cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n");
75 return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
76 }
77 #else
78 #define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull))
79 #endif
80 #define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
81 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_BSEL_EXT_CFGX(unsigned long offset)82 static inline uint64_t CVMX_PIP_BSEL_EXT_CFGX(unsigned long offset)
83 {
84 if (!(
85 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
87 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
88 cvmx_warn("CVMX_PIP_BSEL_EXT_CFGX(%lu) is invalid on this chip\n", offset);
89 return CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16;
90 }
91 #else
92 #define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
93 #endif
94 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_BSEL_EXT_POSX(unsigned long offset)95 static inline uint64_t CVMX_PIP_BSEL_EXT_POSX(unsigned long offset)
96 {
97 if (!(
98 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
99 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
100 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
101 cvmx_warn("CVMX_PIP_BSEL_EXT_POSX(%lu) is invalid on this chip\n", offset);
102 return CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16;
103 }
104 #else
105 #define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
106 #endif
107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_BSEL_TBL_ENTX(unsigned long offset)108 static inline uint64_t CVMX_PIP_BSEL_TBL_ENTX(unsigned long offset)
109 {
110 if (!(
111 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 511))) ||
112 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) ||
113 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 511)))))
114 cvmx_warn("CVMX_PIP_BSEL_TBL_ENTX(%lu) is invalid on this chip\n", offset);
115 return CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8;
116 }
117 #else
118 #define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8)
119 #endif
120 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
121 #define CVMX_PIP_CLKEN CVMX_PIP_CLKEN_FUNC()
CVMX_PIP_CLKEN_FUNC(void)122 static inline uint64_t CVMX_PIP_CLKEN_FUNC(void)
123 {
124 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
125 cvmx_warn("CVMX_PIP_CLKEN not supported on this chip\n");
126 return CVMX_ADD_IO_SEG(0x00011800A0000040ull);
127 }
128 #else
129 #define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull))
130 #endif
131 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_CRC_CTLX(unsigned long offset)132 static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset)
133 {
134 if (!(
135 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
137 cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset);
138 return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8;
139 }
140 #else
141 #define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8)
142 #endif
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_CRC_IVX(unsigned long offset)144 static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset)
145 {
146 if (!(
147 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
148 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
149 cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset);
150 return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8;
151 }
152 #else
153 #define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8)
154 #endif
155 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_DEC_IPSECX(unsigned long offset)156 static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
157 {
158 if (!(
159 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
160 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
161 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
162 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
163 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
164 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
170 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
171 cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset);
172 return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8;
173 }
174 #else
175 #define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8)
176 #endif
177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
178 #define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC()
CVMX_PIP_DSA_SRC_GRP_FUNC(void)179 static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
180 {
181 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
182 cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n");
183 return CVMX_ADD_IO_SEG(0x00011800A0000190ull);
184 }
185 #else
186 #define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull))
187 #endif
188 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
189 #define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC()
CVMX_PIP_DSA_VID_GRP_FUNC(void)190 static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void)
191 {
192 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
193 cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n");
194 return CVMX_ADD_IO_SEG(0x00011800A0000198ull);
195 }
196 #else
197 #define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull))
198 #endif
199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)200 static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
201 {
202 if (!(
203 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
205 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
206 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) ||
207 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) ||
208 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) ||
209 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
210 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0)))))
211 cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset);
212 return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8;
213 }
214 #else
215 #define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8)
216 #endif
217 #define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull))
218 #define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull))
219 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
220 #define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC()
CVMX_PIP_HG_PRI_QOS_FUNC(void)221 static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
222 {
223 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
224 cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n");
225 return CVMX_ADD_IO_SEG(0x00011800A00001A0ull);
226 }
227 #else
228 #define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull))
229 #endif
230 #define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull))
231 #define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull))
232 #define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull))
233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_PRI_TBLX(unsigned long offset)234 static inline uint64_t CVMX_PIP_PRI_TBLX(unsigned long offset)
235 {
236 if (!(
237 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255)))))
238 cvmx_warn("CVMX_PIP_PRI_TBLX(%lu) is invalid on this chip\n", offset);
239 return CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8;
240 }
241 #else
242 #define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8)
243 #endif
244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_PRT_CFGBX(unsigned long offset)245 static inline uint64_t CVMX_PIP_PRT_CFGBX(unsigned long offset)
246 {
247 if (!(
248 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
249 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)) || ((offset >= 44) && (offset <= 47)))) ||
250 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
251 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
252 cvmx_warn("CVMX_PIP_PRT_CFGBX(%lu) is invalid on this chip\n", offset);
253 return CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8;
254 }
255 #else
256 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
257 #endif
258 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_PRT_CFGX(unsigned long offset)259 static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
260 {
261 if (!(
262 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
265 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
266 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
267 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
268 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
269 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
271 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
272 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
273 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
274 cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset);
275 return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8;
276 }
277 #else
278 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
279 #endif
280 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_PRT_TAGX(unsigned long offset)281 static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
282 {
283 if (!(
284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
286 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
288 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
289 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
290 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
291 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
292 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
293 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
294 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
295 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
296 cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset);
297 return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8;
298 }
299 #else
300 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
301 #endif
302 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_QOS_DIFFX(unsigned long offset)303 static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
304 {
305 if (!(
306 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
307 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
308 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
309 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
310 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
311 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
312 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
313 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) ||
314 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) ||
316 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
317 cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset);
318 return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8;
319 }
320 #else
321 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
322 #endif
323 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_QOS_VLANX(unsigned long offset)324 static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
325 {
326 if (!(
327 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
328 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
329 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
333 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
334 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
335 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
336 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
337 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
338 cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset);
339 return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8;
340 }
341 #else
342 #define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8)
343 #endif
344 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_QOS_WATCHX(unsigned long offset)345 static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
346 {
347 if (!(
348 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
349 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
350 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
351 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
352 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
353 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
354 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
355 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
357 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
358 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
359 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
360 cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset);
361 return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8;
362 }
363 #else
364 #define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8)
365 #endif
366 #define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull))
367 #define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull))
368 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT0_PRTX(unsigned long offset)369 static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
370 {
371 if (!(
372 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
373 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
374 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
375 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
376 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
378 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
379 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
380 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
381 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
382 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
383 cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset);
384 return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80;
385 }
386 #else
387 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
388 #endif
389 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT0_X(unsigned long offset)390 static inline uint64_t CVMX_PIP_STAT0_X(unsigned long offset)
391 {
392 if (!(
393 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
394 cvmx_warn("CVMX_PIP_STAT0_X(%lu) is invalid on this chip\n", offset);
395 return CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128;
396 }
397 #else
398 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
399 #endif
400 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT10_PRTX(unsigned long offset)401 static inline uint64_t CVMX_PIP_STAT10_PRTX(unsigned long offset)
402 {
403 if (!(
404 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
406 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
408 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
409 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
410 cvmx_warn("CVMX_PIP_STAT10_PRTX(%lu) is invalid on this chip\n", offset);
411 return CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16;
412 }
413 #else
414 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
415 #endif
416 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT10_X(unsigned long offset)417 static inline uint64_t CVMX_PIP_STAT10_X(unsigned long offset)
418 {
419 if (!(
420 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
421 cvmx_warn("CVMX_PIP_STAT10_X(%lu) is invalid on this chip\n", offset);
422 return CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128;
423 }
424 #else
425 #define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
426 #endif
427 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT11_PRTX(unsigned long offset)428 static inline uint64_t CVMX_PIP_STAT11_PRTX(unsigned long offset)
429 {
430 if (!(
431 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
432 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
433 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
434 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
435 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
436 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
437 cvmx_warn("CVMX_PIP_STAT11_PRTX(%lu) is invalid on this chip\n", offset);
438 return CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16;
439 }
440 #else
441 #define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
442 #endif
443 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT11_X(unsigned long offset)444 static inline uint64_t CVMX_PIP_STAT11_X(unsigned long offset)
445 {
446 if (!(
447 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
448 cvmx_warn("CVMX_PIP_STAT11_X(%lu) is invalid on this chip\n", offset);
449 return CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128;
450 }
451 #else
452 #define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
453 #endif
454 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT1_PRTX(unsigned long offset)455 static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
456 {
457 if (!(
458 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
459 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
460 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
461 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
462 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
463 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
464 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
465 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
466 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
467 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
468 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
469 cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset);
470 return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80;
471 }
472 #else
473 #define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
474 #endif
475 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT1_X(unsigned long offset)476 static inline uint64_t CVMX_PIP_STAT1_X(unsigned long offset)
477 {
478 if (!(
479 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
480 cvmx_warn("CVMX_PIP_STAT1_X(%lu) is invalid on this chip\n", offset);
481 return CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128;
482 }
483 #else
484 #define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
485 #endif
486 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT2_PRTX(unsigned long offset)487 static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
488 {
489 if (!(
490 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
491 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
492 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
493 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
494 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
495 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
496 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
497 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
498 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
499 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
500 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
501 cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset);
502 return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80;
503 }
504 #else
505 #define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
506 #endif
507 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT2_X(unsigned long offset)508 static inline uint64_t CVMX_PIP_STAT2_X(unsigned long offset)
509 {
510 if (!(
511 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
512 cvmx_warn("CVMX_PIP_STAT2_X(%lu) is invalid on this chip\n", offset);
513 return CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128;
514 }
515 #else
516 #define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
517 #endif
518 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT3_PRTX(unsigned long offset)519 static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
520 {
521 if (!(
522 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
523 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
524 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
525 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
526 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
527 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
528 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
529 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
530 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
531 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
532 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
533 cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset);
534 return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80;
535 }
536 #else
537 #define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
538 #endif
539 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT3_X(unsigned long offset)540 static inline uint64_t CVMX_PIP_STAT3_X(unsigned long offset)
541 {
542 if (!(
543 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
544 cvmx_warn("CVMX_PIP_STAT3_X(%lu) is invalid on this chip\n", offset);
545 return CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128;
546 }
547 #else
548 #define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
549 #endif
550 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT4_PRTX(unsigned long offset)551 static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
552 {
553 if (!(
554 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
555 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
556 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
557 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
558 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
559 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
560 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
561 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
562 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
563 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
564 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
565 cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset);
566 return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80;
567 }
568 #else
569 #define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
570 #endif
571 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT4_X(unsigned long offset)572 static inline uint64_t CVMX_PIP_STAT4_X(unsigned long offset)
573 {
574 if (!(
575 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
576 cvmx_warn("CVMX_PIP_STAT4_X(%lu) is invalid on this chip\n", offset);
577 return CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128;
578 }
579 #else
580 #define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
581 #endif
582 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT5_PRTX(unsigned long offset)583 static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
584 {
585 if (!(
586 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
587 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
588 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
589 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
590 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
591 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
592 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
593 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
594 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
595 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
596 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
597 cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset);
598 return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80;
599 }
600 #else
601 #define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
602 #endif
603 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT5_X(unsigned long offset)604 static inline uint64_t CVMX_PIP_STAT5_X(unsigned long offset)
605 {
606 if (!(
607 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
608 cvmx_warn("CVMX_PIP_STAT5_X(%lu) is invalid on this chip\n", offset);
609 return CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128;
610 }
611 #else
612 #define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
613 #endif
614 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT6_PRTX(unsigned long offset)615 static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
616 {
617 if (!(
618 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
619 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
620 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
621 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
622 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
623 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
624 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
625 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
626 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
627 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
628 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
629 cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset);
630 return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80;
631 }
632 #else
633 #define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
634 #endif
635 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT6_X(unsigned long offset)636 static inline uint64_t CVMX_PIP_STAT6_X(unsigned long offset)
637 {
638 if (!(
639 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
640 cvmx_warn("CVMX_PIP_STAT6_X(%lu) is invalid on this chip\n", offset);
641 return CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128;
642 }
643 #else
644 #define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
645 #endif
646 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT7_PRTX(unsigned long offset)647 static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
648 {
649 if (!(
650 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
651 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
652 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
653 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
654 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
655 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
656 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
657 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
658 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
659 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
660 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
661 cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset);
662 return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80;
663 }
664 #else
665 #define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
666 #endif
667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT7_X(unsigned long offset)668 static inline uint64_t CVMX_PIP_STAT7_X(unsigned long offset)
669 {
670 if (!(
671 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
672 cvmx_warn("CVMX_PIP_STAT7_X(%lu) is invalid on this chip\n", offset);
673 return CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128;
674 }
675 #else
676 #define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
677 #endif
678 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT8_PRTX(unsigned long offset)679 static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
680 {
681 if (!(
682 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
683 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
684 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
685 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
686 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
687 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
688 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
689 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
690 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
691 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
692 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
693 cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset);
694 return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80;
695 }
696 #else
697 #define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
698 #endif
699 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT8_X(unsigned long offset)700 static inline uint64_t CVMX_PIP_STAT8_X(unsigned long offset)
701 {
702 if (!(
703 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
704 cvmx_warn("CVMX_PIP_STAT8_X(%lu) is invalid on this chip\n", offset);
705 return CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128;
706 }
707 #else
708 #define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
709 #endif
710 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT9_PRTX(unsigned long offset)711 static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
712 {
713 if (!(
714 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
715 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
716 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
717 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
718 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
719 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
720 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
721 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
722 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
723 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
724 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
725 cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset);
726 return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80;
727 }
728 #else
729 #define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
730 #endif
731 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT9_X(unsigned long offset)732 static inline uint64_t CVMX_PIP_STAT9_X(unsigned long offset)
733 {
734 if (!(
735 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
736 cvmx_warn("CVMX_PIP_STAT9_X(%lu) is invalid on this chip\n", offset);
737 return CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128;
738 }
739 #else
740 #define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
741 #endif
742 #define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull))
743 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)744 static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
745 {
746 if (!(
747 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
748 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
749 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
750 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
751 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
752 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
753 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
754 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
755 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
757 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
758 cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset);
759 return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32;
760 }
761 #else
762 #define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
763 #endif
764 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT_INB_ERRS_PKNDX(unsigned long offset)765 static inline uint64_t CVMX_PIP_STAT_INB_ERRS_PKNDX(unsigned long offset)
766 {
767 if (!(
768 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
769 cvmx_warn("CVMX_PIP_STAT_INB_ERRS_PKNDX(%lu) is invalid on this chip\n", offset);
770 return CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32;
771 }
772 #else
773 #define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
774 #endif
775 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)776 static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
777 {
778 if (!(
779 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
780 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
781 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
782 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
783 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
784 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
785 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
786 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
787 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
788 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
789 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
790 cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset);
791 return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32;
792 }
793 #else
794 #define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
795 #endif
796 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT_INB_OCTS_PKNDX(unsigned long offset)797 static inline uint64_t CVMX_PIP_STAT_INB_OCTS_PKNDX(unsigned long offset)
798 {
799 if (!(
800 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
801 cvmx_warn("CVMX_PIP_STAT_INB_OCTS_PKNDX(%lu) is invalid on this chip\n", offset);
802 return CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32;
803 }
804 #else
805 #define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
806 #endif
807 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)808 static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
809 {
810 if (!(
811 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
812 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
813 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
814 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
815 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
816 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
817 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
818 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
819 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) ||
820 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
821 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
822 cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset);
823 return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32;
824 }
825 #else
826 #define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
827 #endif
828 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_STAT_INB_PKTS_PKNDX(unsigned long offset)829 static inline uint64_t CVMX_PIP_STAT_INB_PKTS_PKNDX(unsigned long offset)
830 {
831 if (!(
832 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
833 cvmx_warn("CVMX_PIP_STAT_INB_PKTS_PKNDX(%lu) is invalid on this chip\n", offset);
834 return CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32;
835 }
836 #else
837 #define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
838 #endif
839 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_SUB_PKIND_FCSX(unsigned long block_id)840 static inline uint64_t CVMX_PIP_SUB_PKIND_FCSX(unsigned long block_id)
841 {
842 if (!(
843 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0)))))
844 cvmx_warn("CVMX_PIP_SUB_PKIND_FCSX(%lu) is invalid on this chip\n", block_id);
845 return CVMX_ADD_IO_SEG(0x00011800A0080000ull);
846 }
847 #else
848 #define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull))
849 #endif
850 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_TAG_INCX(unsigned long offset)851 static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
852 {
853 if (!(
854 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
855 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
856 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
857 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
858 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) ||
859 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
860 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
861 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) ||
862 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) ||
863 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) ||
864 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) ||
865 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63)))))
866 cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset);
867 return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8;
868 }
869 #else
870 #define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
871 #endif
872 #define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull))
873 #define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull))
874 #define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull))
875 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_VLAN_ETYPESX(unsigned long offset)876 static inline uint64_t CVMX_PIP_VLAN_ETYPESX(unsigned long offset)
877 {
878 if (!(
879 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
880 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
881 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
882 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
883 cvmx_warn("CVMX_PIP_VLAN_ETYPESX(%lu) is invalid on this chip\n", offset);
884 return CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8;
885 }
886 #else
887 #define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8)
888 #endif
889 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT0_PRTX(unsigned long offset)890 static inline uint64_t CVMX_PIP_XSTAT0_PRTX(unsigned long offset)
891 {
892 if (!(
893 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
894 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
895 cvmx_warn("CVMX_PIP_XSTAT0_PRTX(%lu) is invalid on this chip\n", offset);
896 return CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40;
897 }
898 #else
899 #define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
900 #endif
901 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT10_PRTX(unsigned long offset)902 static inline uint64_t CVMX_PIP_XSTAT10_PRTX(unsigned long offset)
903 {
904 if (!(
905 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
906 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
907 cvmx_warn("CVMX_PIP_XSTAT10_PRTX(%lu) is invalid on this chip\n", offset);
908 return CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40;
909 }
910 #else
911 #define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
912 #endif
913 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT11_PRTX(unsigned long offset)914 static inline uint64_t CVMX_PIP_XSTAT11_PRTX(unsigned long offset)
915 {
916 if (!(
917 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
918 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
919 cvmx_warn("CVMX_PIP_XSTAT11_PRTX(%lu) is invalid on this chip\n", offset);
920 return CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40;
921 }
922 #else
923 #define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
924 #endif
925 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT1_PRTX(unsigned long offset)926 static inline uint64_t CVMX_PIP_XSTAT1_PRTX(unsigned long offset)
927 {
928 if (!(
929 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
930 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
931 cvmx_warn("CVMX_PIP_XSTAT1_PRTX(%lu) is invalid on this chip\n", offset);
932 return CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40;
933 }
934 #else
935 #define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
936 #endif
937 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT2_PRTX(unsigned long offset)938 static inline uint64_t CVMX_PIP_XSTAT2_PRTX(unsigned long offset)
939 {
940 if (!(
941 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
942 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
943 cvmx_warn("CVMX_PIP_XSTAT2_PRTX(%lu) is invalid on this chip\n", offset);
944 return CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40;
945 }
946 #else
947 #define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
948 #endif
949 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT3_PRTX(unsigned long offset)950 static inline uint64_t CVMX_PIP_XSTAT3_PRTX(unsigned long offset)
951 {
952 if (!(
953 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
954 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
955 cvmx_warn("CVMX_PIP_XSTAT3_PRTX(%lu) is invalid on this chip\n", offset);
956 return CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40;
957 }
958 #else
959 #define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
960 #endif
961 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT4_PRTX(unsigned long offset)962 static inline uint64_t CVMX_PIP_XSTAT4_PRTX(unsigned long offset)
963 {
964 if (!(
965 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
966 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
967 cvmx_warn("CVMX_PIP_XSTAT4_PRTX(%lu) is invalid on this chip\n", offset);
968 return CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40;
969 }
970 #else
971 #define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
972 #endif
973 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT5_PRTX(unsigned long offset)974 static inline uint64_t CVMX_PIP_XSTAT5_PRTX(unsigned long offset)
975 {
976 if (!(
977 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
978 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
979 cvmx_warn("CVMX_PIP_XSTAT5_PRTX(%lu) is invalid on this chip\n", offset);
980 return CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40;
981 }
982 #else
983 #define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
984 #endif
985 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT6_PRTX(unsigned long offset)986 static inline uint64_t CVMX_PIP_XSTAT6_PRTX(unsigned long offset)
987 {
988 if (!(
989 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
990 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
991 cvmx_warn("CVMX_PIP_XSTAT6_PRTX(%lu) is invalid on this chip\n", offset);
992 return CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40;
993 }
994 #else
995 #define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
996 #endif
997 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT7_PRTX(unsigned long offset)998 static inline uint64_t CVMX_PIP_XSTAT7_PRTX(unsigned long offset)
999 {
1000 if (!(
1001 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
1002 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
1003 cvmx_warn("CVMX_PIP_XSTAT7_PRTX(%lu) is invalid on this chip\n", offset);
1004 return CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40;
1005 }
1006 #else
1007 #define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
1008 #endif
1009 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT8_PRTX(unsigned long offset)1010 static inline uint64_t CVMX_PIP_XSTAT8_PRTX(unsigned long offset)
1011 {
1012 if (!(
1013 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
1014 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
1015 cvmx_warn("CVMX_PIP_XSTAT8_PRTX(%lu) is invalid on this chip\n", offset);
1016 return CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40;
1017 }
1018 #else
1019 #define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
1020 #endif
1021 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PIP_XSTAT9_PRTX(unsigned long offset)1022 static inline uint64_t CVMX_PIP_XSTAT9_PRTX(unsigned long offset)
1023 {
1024 if (!(
1025 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
1026 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47))))))
1027 cvmx_warn("CVMX_PIP_XSTAT9_PRTX(%lu) is invalid on this chip\n", offset);
1028 return CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40;
1029 }
1030 #else
1031 #define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
1032 #endif
1033
1034 /**
1035 * cvmx_pip_alt_skip_cfg#
1036 *
1037 * Notes:
1038 * The actual SKIP I determined by HW is based on the packet contents. BIT0 and
1039 * BIT1 make up a two value value that the selects the skip value as follows.
1040 *
1041 * lookup_value = LEN ? ( packet_in_bits[BIT1], packet_in_bits[BIT0] ) : ( 0, packet_in_bits[BIT0] );
1042 * SKIP I = lookup_value == 3 ? SKIP3 :
1043 * lookup_value == 2 ? SKIP2 :
1044 * lookup_value == 1 ? SKIP1 :
1045 * PIP_PRT_CFG<pknd>[SKIP];
1046 */
1047 union cvmx_pip_alt_skip_cfgx {
1048 uint64_t u64;
1049 struct cvmx_pip_alt_skip_cfgx_s {
1050 #ifdef __BIG_ENDIAN_BITFIELD
1051 uint64_t reserved_57_63 : 7;
1052 uint64_t len : 1; /**< Indicates the length of the selection field
1053 0 = 0, BIT0
1054 1 = BIT1, BIT0 */
1055 uint64_t reserved_46_55 : 10;
1056 uint64_t bit1 : 6; /**< Indicates the bit location in the first word of
1057 the packet to use to select the skip amount.
1058 BIT1 must be present in the packet. */
1059 uint64_t reserved_38_39 : 2;
1060 uint64_t bit0 : 6; /**< Indicates the bit location in the first word of
1061 the packet to use to select the skip amount.
1062 BIT0 must be present in the packet. */
1063 uint64_t reserved_23_31 : 9;
1064 uint64_t skip3 : 7; /**< Indicates number of bytes to skip from start of
1065 packet 0-64 */
1066 uint64_t reserved_15_15 : 1;
1067 uint64_t skip2 : 7; /**< Indicates number of bytes to skip from start of
1068 packet 0-64 */
1069 uint64_t reserved_7_7 : 1;
1070 uint64_t skip1 : 7; /**< Indicates number of bytes to skip from start of
1071 packet 0-64 */
1072 #else
1073 uint64_t skip1 : 7;
1074 uint64_t reserved_7_7 : 1;
1075 uint64_t skip2 : 7;
1076 uint64_t reserved_15_15 : 1;
1077 uint64_t skip3 : 7;
1078 uint64_t reserved_23_31 : 9;
1079 uint64_t bit0 : 6;
1080 uint64_t reserved_38_39 : 2;
1081 uint64_t bit1 : 6;
1082 uint64_t reserved_46_55 : 10;
1083 uint64_t len : 1;
1084 uint64_t reserved_57_63 : 7;
1085 #endif
1086 } s;
1087 struct cvmx_pip_alt_skip_cfgx_s cn61xx;
1088 struct cvmx_pip_alt_skip_cfgx_s cn66xx;
1089 struct cvmx_pip_alt_skip_cfgx_s cn68xx;
1090 struct cvmx_pip_alt_skip_cfgx_s cnf71xx;
1091 };
1092 typedef union cvmx_pip_alt_skip_cfgx cvmx_pip_alt_skip_cfgx_t;
1093
1094 /**
1095 * cvmx_pip_bck_prs
1096 *
1097 * PIP_BCK_PRS = PIP's Back Pressure Register
1098 *
1099 * When to assert backpressure based on the todo list filling up
1100 */
1101 union cvmx_pip_bck_prs {
1102 uint64_t u64;
1103 struct cvmx_pip_bck_prs_s {
1104 #ifdef __BIG_ENDIAN_BITFIELD
1105 uint64_t bckprs : 1; /**< PIP is currently asserting backpressure to IOB
1106 Backpressure from PIP will assert when the
1107 entries to the todo list exceed HIWATER.
1108 Backpressure will be held until the todo entries
1109 is less than or equal to LOWATER. */
1110 uint64_t reserved_13_62 : 50;
1111 uint64_t hiwater : 5; /**< Water mark in the todo list to assert backpressure
1112 Legal values are 1-26. A 0 value will deadlock
1113 the machine. A value > 26, will trash memory */
1114 uint64_t reserved_5_7 : 3;
1115 uint64_t lowater : 5; /**< Water mark in the todo list to release backpressure
1116 The LOWATER value should be < HIWATER. */
1117 #else
1118 uint64_t lowater : 5;
1119 uint64_t reserved_5_7 : 3;
1120 uint64_t hiwater : 5;
1121 uint64_t reserved_13_62 : 50;
1122 uint64_t bckprs : 1;
1123 #endif
1124 } s;
1125 struct cvmx_pip_bck_prs_s cn38xx;
1126 struct cvmx_pip_bck_prs_s cn38xxp2;
1127 struct cvmx_pip_bck_prs_s cn56xx;
1128 struct cvmx_pip_bck_prs_s cn56xxp1;
1129 struct cvmx_pip_bck_prs_s cn58xx;
1130 struct cvmx_pip_bck_prs_s cn58xxp1;
1131 struct cvmx_pip_bck_prs_s cn61xx;
1132 struct cvmx_pip_bck_prs_s cn63xx;
1133 struct cvmx_pip_bck_prs_s cn63xxp1;
1134 struct cvmx_pip_bck_prs_s cn66xx;
1135 struct cvmx_pip_bck_prs_s cn68xx;
1136 struct cvmx_pip_bck_prs_s cn68xxp1;
1137 struct cvmx_pip_bck_prs_s cnf71xx;
1138 };
1139 typedef union cvmx_pip_bck_prs cvmx_pip_bck_prs_t;
1140
1141 /**
1142 * cvmx_pip_bist_status
1143 *
1144 * PIP_BIST_STATUS = PIP's BIST Results
1145 *
1146 */
1147 union cvmx_pip_bist_status {
1148 uint64_t u64;
1149 struct cvmx_pip_bist_status_s {
1150 #ifdef __BIG_ENDIAN_BITFIELD
1151 uint64_t reserved_22_63 : 42;
1152 uint64_t bist : 22; /**< BIST Results.
1153 HW sets a bit in BIST for for memory that fails
1154 BIST. */
1155 #else
1156 uint64_t bist : 22;
1157 uint64_t reserved_22_63 : 42;
1158 #endif
1159 } s;
1160 struct cvmx_pip_bist_status_cn30xx {
1161 #ifdef __BIG_ENDIAN_BITFIELD
1162 uint64_t reserved_18_63 : 46;
1163 uint64_t bist : 18; /**< BIST Results.
1164 HW sets a bit in BIST for for memory that fails
1165 BIST. */
1166 #else
1167 uint64_t bist : 18;
1168 uint64_t reserved_18_63 : 46;
1169 #endif
1170 } cn30xx;
1171 struct cvmx_pip_bist_status_cn30xx cn31xx;
1172 struct cvmx_pip_bist_status_cn30xx cn38xx;
1173 struct cvmx_pip_bist_status_cn30xx cn38xxp2;
1174 struct cvmx_pip_bist_status_cn50xx {
1175 #ifdef __BIG_ENDIAN_BITFIELD
1176 uint64_t reserved_17_63 : 47;
1177 uint64_t bist : 17; /**< BIST Results.
1178 HW sets a bit in BIST for for memory that fails
1179 BIST. */
1180 #else
1181 uint64_t bist : 17;
1182 uint64_t reserved_17_63 : 47;
1183 #endif
1184 } cn50xx;
1185 struct cvmx_pip_bist_status_cn30xx cn52xx;
1186 struct cvmx_pip_bist_status_cn30xx cn52xxp1;
1187 struct cvmx_pip_bist_status_cn30xx cn56xx;
1188 struct cvmx_pip_bist_status_cn30xx cn56xxp1;
1189 struct cvmx_pip_bist_status_cn30xx cn58xx;
1190 struct cvmx_pip_bist_status_cn30xx cn58xxp1;
1191 struct cvmx_pip_bist_status_cn61xx {
1192 #ifdef __BIG_ENDIAN_BITFIELD
1193 uint64_t reserved_20_63 : 44;
1194 uint64_t bist : 20; /**< BIST Results.
1195 HW sets a bit in BIST for for memory that fails
1196 BIST. */
1197 #else
1198 uint64_t bist : 20;
1199 uint64_t reserved_20_63 : 44;
1200 #endif
1201 } cn61xx;
1202 struct cvmx_pip_bist_status_cn30xx cn63xx;
1203 struct cvmx_pip_bist_status_cn30xx cn63xxp1;
1204 struct cvmx_pip_bist_status_cn61xx cn66xx;
1205 struct cvmx_pip_bist_status_s cn68xx;
1206 struct cvmx_pip_bist_status_cn61xx cn68xxp1;
1207 struct cvmx_pip_bist_status_cn61xx cnf71xx;
1208 };
1209 typedef union cvmx_pip_bist_status cvmx_pip_bist_status_t;
1210
1211 /**
1212 * cvmx_pip_bsel_ext_cfg#
1213 *
1214 * PIP_BSEL_EXT_CFGX = Bit Select Extractor config register containing the
1215 * tag, offset, and skip values to be used when using the corresponding extractor.
1216 */
1217 union cvmx_pip_bsel_ext_cfgx {
1218 uint64_t u64;
1219 struct cvmx_pip_bsel_ext_cfgx_s {
1220 #ifdef __BIG_ENDIAN_BITFIELD
1221 uint64_t reserved_56_63 : 8;
1222 uint64_t upper_tag : 16; /**< Extra Tag bits to be added to tag field from table
1223 Only included when PIP_PRT_TAG[INC_PRT]=0
1224 WORD2[TAG<31:16>] */
1225 uint64_t tag : 8; /**< Extra Tag bits to be added to tag field from table
1226 WORD2[TAG<15:8>] */
1227 uint64_t reserved_25_31 : 7;
1228 uint64_t offset : 9; /**< Indicates offset to add to extractor mem adr
1229 to get final address to the lookup table */
1230 uint64_t reserved_7_15 : 9;
1231 uint64_t skip : 7; /**< Indicates number of bytes to skip from start of
1232 packet 0-64 */
1233 #else
1234 uint64_t skip : 7;
1235 uint64_t reserved_7_15 : 9;
1236 uint64_t offset : 9;
1237 uint64_t reserved_25_31 : 7;
1238 uint64_t tag : 8;
1239 uint64_t upper_tag : 16;
1240 uint64_t reserved_56_63 : 8;
1241 #endif
1242 } s;
1243 struct cvmx_pip_bsel_ext_cfgx_s cn61xx;
1244 struct cvmx_pip_bsel_ext_cfgx_s cn68xx;
1245 struct cvmx_pip_bsel_ext_cfgx_s cnf71xx;
1246 };
1247 typedef union cvmx_pip_bsel_ext_cfgx cvmx_pip_bsel_ext_cfgx_t;
1248
1249 /**
1250 * cvmx_pip_bsel_ext_pos#
1251 *
1252 * PIP_BSEL_EXT_POSX = Bit Select Extractor config register containing the 8
1253 * bit positions and valids to be used when using the corresponding extractor.
1254 *
1255 * Notes:
1256 * Examples on bit positioning:
1257 * the most-significant-bit of the 3rd byte ... PIP_BSEL_EXT_CFG*[SKIP]=1 POSn=15 (decimal) or
1258 * PIP_BSEL_EXT_CFG*[SKIP]=0 POSn=23 (decimal)
1259 * the least-significant-bit of the 5th byte ... PIP_BSEL_EXT_CFG*[SKIP]=4 POSn=0
1260 * the second-least-significant bit of the 1st byte ... PIP_BSEL_EXT_CFG*[SKIP]=0 POSn=1
1261 *
1262 * POSn_VAL and POSn correspond to <n> in the resultant index into
1263 * PIP_BSEL_TBL_ENT. When only x bits (0 < x < 7) are to be extracted,
1264 * POS[7:x] should normally be clear.
1265 */
1266 union cvmx_pip_bsel_ext_posx {
1267 uint64_t u64;
1268 struct cvmx_pip_bsel_ext_posx_s {
1269 #ifdef __BIG_ENDIAN_BITFIELD
1270 uint64_t pos7_val : 1; /**< Valid bit for bit position 7 */
1271 uint64_t pos7 : 7; /**< Bit position for the 8th bit from 128 bit segment
1272 of pkt that is defined by the SKIP field of
1273 PIP_BSEL_EXT_CFG register. */
1274 uint64_t pos6_val : 1; /**< Valid bit for bit position 6 */
1275 uint64_t pos6 : 7; /**< Bit position for the 7th bit from 128 bit segment
1276 of pkt that is defined by the SKIP field of
1277 PIP_BSEL_EXT_CFG register. */
1278 uint64_t pos5_val : 1; /**< Valid bit for bit position 5 */
1279 uint64_t pos5 : 7; /**< Bit position for the 6th bit from 128 bit segment
1280 of pkt that is defined by the SKIP field of
1281 PIP_BSEL_EXT_CFG register. */
1282 uint64_t pos4_val : 1; /**< Valid bit for bit position 4 */
1283 uint64_t pos4 : 7; /**< Bit position for the 5th bit from 128 bit segment
1284 of pkt that is defined by the SKIP field of
1285 PIP_BSEL_EXT_CFG register. */
1286 uint64_t pos3_val : 1; /**< Valid bit for bit position 3 */
1287 uint64_t pos3 : 7; /**< Bit position for the 4th bit from 128 bit segment
1288 of pkt that is defined by the SKIP field of
1289 PIP_BSEL_EXT_CFG register. */
1290 uint64_t pos2_val : 1; /**< Valid bit for bit position 2 */
1291 uint64_t pos2 : 7; /**< Bit position for the 3rd bit from 128 bit segment
1292 of pkt that is defined by the SKIP field of
1293 PIP_BSEL_EXT_CFG register. */
1294 uint64_t pos1_val : 1; /**< Valid bit for bit position 1 */
1295 uint64_t pos1 : 7; /**< Bit position for the 2nd bit from 128 bit segment
1296 of pkt that is defined by the SKIP field of
1297 PIP_BSEL_EXT_CFG register. */
1298 uint64_t pos0_val : 1; /**< Valid bit for bit position 0 */
1299 uint64_t pos0 : 7; /**< Bit position for the 1st bit from 128 bit segment
1300 of pkt that is defined by the SKIP field of
1301 PIP_BSEL_EXT_CFG register. */
1302 #else
1303 uint64_t pos0 : 7;
1304 uint64_t pos0_val : 1;
1305 uint64_t pos1 : 7;
1306 uint64_t pos1_val : 1;
1307 uint64_t pos2 : 7;
1308 uint64_t pos2_val : 1;
1309 uint64_t pos3 : 7;
1310 uint64_t pos3_val : 1;
1311 uint64_t pos4 : 7;
1312 uint64_t pos4_val : 1;
1313 uint64_t pos5 : 7;
1314 uint64_t pos5_val : 1;
1315 uint64_t pos6 : 7;
1316 uint64_t pos6_val : 1;
1317 uint64_t pos7 : 7;
1318 uint64_t pos7_val : 1;
1319 #endif
1320 } s;
1321 struct cvmx_pip_bsel_ext_posx_s cn61xx;
1322 struct cvmx_pip_bsel_ext_posx_s cn68xx;
1323 struct cvmx_pip_bsel_ext_posx_s cnf71xx;
1324 };
1325 typedef union cvmx_pip_bsel_ext_posx cvmx_pip_bsel_ext_posx_t;
1326
1327 /**
1328 * cvmx_pip_bsel_tbl_ent#
1329 *
1330 * PIP_BSEL_TBL_ENTX = Entry for the extractor table
1331 *
1332 */
1333 union cvmx_pip_bsel_tbl_entx {
1334 uint64_t u64;
1335 struct cvmx_pip_bsel_tbl_entx_s {
1336 #ifdef __BIG_ENDIAN_BITFIELD
1337 uint64_t tag_en : 1; /**< Enables the use of the TAG field */
1338 uint64_t grp_en : 1; /**< Enables the use of the GRP field */
1339 uint64_t tt_en : 1; /**< Enables the use of the TT field */
1340 uint64_t qos_en : 1; /**< Enables the use of the QOS field */
1341 uint64_t reserved_40_59 : 20;
1342 uint64_t tag : 8; /**< TAG bits to be used if TAG_EN is set */
1343 uint64_t reserved_22_31 : 10;
1344 uint64_t grp : 6; /**< GRP field to be used if GRP_EN is set */
1345 uint64_t reserved_10_15 : 6;
1346 uint64_t tt : 2; /**< TT field to be used if TT_EN is set */
1347 uint64_t reserved_3_7 : 5;
1348 uint64_t qos : 3; /**< QOS field to be used if QOS_EN is set */
1349 #else
1350 uint64_t qos : 3;
1351 uint64_t reserved_3_7 : 5;
1352 uint64_t tt : 2;
1353 uint64_t reserved_10_15 : 6;
1354 uint64_t grp : 6;
1355 uint64_t reserved_22_31 : 10;
1356 uint64_t tag : 8;
1357 uint64_t reserved_40_59 : 20;
1358 uint64_t qos_en : 1;
1359 uint64_t tt_en : 1;
1360 uint64_t grp_en : 1;
1361 uint64_t tag_en : 1;
1362 #endif
1363 } s;
1364 struct cvmx_pip_bsel_tbl_entx_cn61xx {
1365 #ifdef __BIG_ENDIAN_BITFIELD
1366 uint64_t tag_en : 1; /**< Enables the use of the TAG field */
1367 uint64_t grp_en : 1; /**< Enables the use of the GRP field */
1368 uint64_t tt_en : 1; /**< Enables the use of the TT field */
1369 uint64_t qos_en : 1; /**< Enables the use of the QOS field */
1370 uint64_t reserved_40_59 : 20;
1371 uint64_t tag : 8; /**< TAG bits to be used if TAG_EN is set */
1372 uint64_t reserved_20_31 : 12;
1373 uint64_t grp : 4; /**< GRP field to be used if GRP_EN is set */
1374 uint64_t reserved_10_15 : 6;
1375 uint64_t tt : 2; /**< TT field to be used if TT_EN is set */
1376 uint64_t reserved_3_7 : 5;
1377 uint64_t qos : 3; /**< QOS field to be used if QOS_EN is set */
1378 #else
1379 uint64_t qos : 3;
1380 uint64_t reserved_3_7 : 5;
1381 uint64_t tt : 2;
1382 uint64_t reserved_10_15 : 6;
1383 uint64_t grp : 4;
1384 uint64_t reserved_20_31 : 12;
1385 uint64_t tag : 8;
1386 uint64_t reserved_40_59 : 20;
1387 uint64_t qos_en : 1;
1388 uint64_t tt_en : 1;
1389 uint64_t grp_en : 1;
1390 uint64_t tag_en : 1;
1391 #endif
1392 } cn61xx;
1393 struct cvmx_pip_bsel_tbl_entx_s cn68xx;
1394 struct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx;
1395 };
1396 typedef union cvmx_pip_bsel_tbl_entx cvmx_pip_bsel_tbl_entx_t;
1397
1398 /**
1399 * cvmx_pip_clken
1400 */
1401 union cvmx_pip_clken {
1402 uint64_t u64;
1403 struct cvmx_pip_clken_s {
1404 #ifdef __BIG_ENDIAN_BITFIELD
1405 uint64_t reserved_1_63 : 63;
1406 uint64_t clken : 1; /**< Controls the conditional clocking within PIP
1407 0=Allow HW to control the clocks
1408 1=Force the clocks to be always on */
1409 #else
1410 uint64_t clken : 1;
1411 uint64_t reserved_1_63 : 63;
1412 #endif
1413 } s;
1414 struct cvmx_pip_clken_s cn61xx;
1415 struct cvmx_pip_clken_s cn63xx;
1416 struct cvmx_pip_clken_s cn63xxp1;
1417 struct cvmx_pip_clken_s cn66xx;
1418 struct cvmx_pip_clken_s cn68xx;
1419 struct cvmx_pip_clken_s cn68xxp1;
1420 struct cvmx_pip_clken_s cnf71xx;
1421 };
1422 typedef union cvmx_pip_clken cvmx_pip_clken_t;
1423
1424 /**
1425 * cvmx_pip_crc_ctl#
1426 *
1427 * PIP_CRC_CTL = PIP CRC Control Register
1428 *
1429 * Controls datapath reflection when calculating CRC
1430 */
1431 union cvmx_pip_crc_ctlx {
1432 uint64_t u64;
1433 struct cvmx_pip_crc_ctlx_s {
1434 #ifdef __BIG_ENDIAN_BITFIELD
1435 uint64_t reserved_2_63 : 62;
1436 uint64_t invres : 1; /**< Invert the result */
1437 uint64_t reflect : 1; /**< Reflect the bits in each byte.
1438 Byte order does not change.
1439 - 0: CRC is calculated MSB to LSB
1440 - 1: CRC is calculated LSB to MSB */
1441 #else
1442 uint64_t reflect : 1;
1443 uint64_t invres : 1;
1444 uint64_t reserved_2_63 : 62;
1445 #endif
1446 } s;
1447 struct cvmx_pip_crc_ctlx_s cn38xx;
1448 struct cvmx_pip_crc_ctlx_s cn38xxp2;
1449 struct cvmx_pip_crc_ctlx_s cn58xx;
1450 struct cvmx_pip_crc_ctlx_s cn58xxp1;
1451 };
1452 typedef union cvmx_pip_crc_ctlx cvmx_pip_crc_ctlx_t;
1453
1454 /**
1455 * cvmx_pip_crc_iv#
1456 *
1457 * PIP_CRC_IV = PIP CRC IV Register
1458 *
1459 * Determines the IV used by the CRC algorithm
1460 *
1461 * Notes:
1462 * * PIP_CRC_IV
1463 * PIP_CRC_IV controls the initial state of the CRC algorithm. Octane can
1464 * support a wide range of CRC algorithms and as such, the IV must be
1465 * carefully constructed to meet the specific algorithm. The code below
1466 * determines the value to program into Octane based on the algorthim's IV
1467 * and width. In the case of Octane, the width should always be 32.
1468 *
1469 * PIP_CRC_IV0 sets the IV for ports 0-15 while PIP_CRC_IV1 sets the IV for
1470 * ports 16-31.
1471 *
1472 * unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
1473 * [
1474 * int i;
1475 * int doit;
1476 * unsigned int current_val = algorithm_iv;
1477 *
1478 * for(i = 0; i < w; i++) [
1479 * doit = current_val & 0x1;
1480 *
1481 * if(doit) current_val ^= poly;
1482 * assert(!(current_val & 0x1));
1483 *
1484 * current_val = (current_val >> 1) | (doit << (w-1));
1485 * ]
1486 *
1487 * return current_val;
1488 * ]
1489 */
1490 union cvmx_pip_crc_ivx {
1491 uint64_t u64;
1492 struct cvmx_pip_crc_ivx_s {
1493 #ifdef __BIG_ENDIAN_BITFIELD
1494 uint64_t reserved_32_63 : 32;
1495 uint64_t iv : 32; /**< IV used by the CRC algorithm. Default is FCS32. */
1496 #else
1497 uint64_t iv : 32;
1498 uint64_t reserved_32_63 : 32;
1499 #endif
1500 } s;
1501 struct cvmx_pip_crc_ivx_s cn38xx;
1502 struct cvmx_pip_crc_ivx_s cn38xxp2;
1503 struct cvmx_pip_crc_ivx_s cn58xx;
1504 struct cvmx_pip_crc_ivx_s cn58xxp1;
1505 };
1506 typedef union cvmx_pip_crc_ivx cvmx_pip_crc_ivx_t;
1507
1508 /**
1509 * cvmx_pip_dec_ipsec#
1510 *
1511 * PIP_DEC_IPSEC = UDP or TCP ports to watch for DEC IPSEC
1512 *
1513 * PIP sets the dec_ipsec based on TCP or UDP destination port.
1514 */
1515 union cvmx_pip_dec_ipsecx {
1516 uint64_t u64;
1517 struct cvmx_pip_dec_ipsecx_s {
1518 #ifdef __BIG_ENDIAN_BITFIELD
1519 uint64_t reserved_18_63 : 46;
1520 uint64_t tcp : 1; /**< This DPRT should be used for TCP packets */
1521 uint64_t udp : 1; /**< This DPRT should be used for UDP packets */
1522 uint64_t dprt : 16; /**< UDP or TCP destination port to match on */
1523 #else
1524 uint64_t dprt : 16;
1525 uint64_t udp : 1;
1526 uint64_t tcp : 1;
1527 uint64_t reserved_18_63 : 46;
1528 #endif
1529 } s;
1530 struct cvmx_pip_dec_ipsecx_s cn30xx;
1531 struct cvmx_pip_dec_ipsecx_s cn31xx;
1532 struct cvmx_pip_dec_ipsecx_s cn38xx;
1533 struct cvmx_pip_dec_ipsecx_s cn38xxp2;
1534 struct cvmx_pip_dec_ipsecx_s cn50xx;
1535 struct cvmx_pip_dec_ipsecx_s cn52xx;
1536 struct cvmx_pip_dec_ipsecx_s cn52xxp1;
1537 struct cvmx_pip_dec_ipsecx_s cn56xx;
1538 struct cvmx_pip_dec_ipsecx_s cn56xxp1;
1539 struct cvmx_pip_dec_ipsecx_s cn58xx;
1540 struct cvmx_pip_dec_ipsecx_s cn58xxp1;
1541 struct cvmx_pip_dec_ipsecx_s cn61xx;
1542 struct cvmx_pip_dec_ipsecx_s cn63xx;
1543 struct cvmx_pip_dec_ipsecx_s cn63xxp1;
1544 struct cvmx_pip_dec_ipsecx_s cn66xx;
1545 struct cvmx_pip_dec_ipsecx_s cn68xx;
1546 struct cvmx_pip_dec_ipsecx_s cn68xxp1;
1547 struct cvmx_pip_dec_ipsecx_s cnf71xx;
1548 };
1549 typedef union cvmx_pip_dec_ipsecx cvmx_pip_dec_ipsecx_t;
1550
1551 /**
1552 * cvmx_pip_dsa_src_grp
1553 */
1554 union cvmx_pip_dsa_src_grp {
1555 uint64_t u64;
1556 struct cvmx_pip_dsa_src_grp_s {
1557 #ifdef __BIG_ENDIAN_BITFIELD
1558 uint64_t map15 : 4; /**< DSA Group Algorithm */
1559 uint64_t map14 : 4; /**< DSA Group Algorithm */
1560 uint64_t map13 : 4; /**< DSA Group Algorithm */
1561 uint64_t map12 : 4; /**< DSA Group Algorithm */
1562 uint64_t map11 : 4; /**< DSA Group Algorithm */
1563 uint64_t map10 : 4; /**< DSA Group Algorithm */
1564 uint64_t map9 : 4; /**< DSA Group Algorithm */
1565 uint64_t map8 : 4; /**< DSA Group Algorithm */
1566 uint64_t map7 : 4; /**< DSA Group Algorithm */
1567 uint64_t map6 : 4; /**< DSA Group Algorithm */
1568 uint64_t map5 : 4; /**< DSA Group Algorithm */
1569 uint64_t map4 : 4; /**< DSA Group Algorithm */
1570 uint64_t map3 : 4; /**< DSA Group Algorithm */
1571 uint64_t map2 : 4; /**< DSA Group Algorithm */
1572 uint64_t map1 : 4; /**< DSA Group Algorithm */
1573 uint64_t map0 : 4; /**< DSA Group Algorithm
1574 Use the DSA source id to compute GRP */
1575 #else
1576 uint64_t map0 : 4;
1577 uint64_t map1 : 4;
1578 uint64_t map2 : 4;
1579 uint64_t map3 : 4;
1580 uint64_t map4 : 4;
1581 uint64_t map5 : 4;
1582 uint64_t map6 : 4;
1583 uint64_t map7 : 4;
1584 uint64_t map8 : 4;
1585 uint64_t map9 : 4;
1586 uint64_t map10 : 4;
1587 uint64_t map11 : 4;
1588 uint64_t map12 : 4;
1589 uint64_t map13 : 4;
1590 uint64_t map14 : 4;
1591 uint64_t map15 : 4;
1592 #endif
1593 } s;
1594 struct cvmx_pip_dsa_src_grp_s cn52xx;
1595 struct cvmx_pip_dsa_src_grp_s cn52xxp1;
1596 struct cvmx_pip_dsa_src_grp_s cn56xx;
1597 struct cvmx_pip_dsa_src_grp_s cn61xx;
1598 struct cvmx_pip_dsa_src_grp_s cn63xx;
1599 struct cvmx_pip_dsa_src_grp_s cn63xxp1;
1600 struct cvmx_pip_dsa_src_grp_s cn66xx;
1601 struct cvmx_pip_dsa_src_grp_s cn68xx;
1602 struct cvmx_pip_dsa_src_grp_s cn68xxp1;
1603 struct cvmx_pip_dsa_src_grp_s cnf71xx;
1604 };
1605 typedef union cvmx_pip_dsa_src_grp cvmx_pip_dsa_src_grp_t;
1606
1607 /**
1608 * cvmx_pip_dsa_vid_grp
1609 */
1610 union cvmx_pip_dsa_vid_grp {
1611 uint64_t u64;
1612 struct cvmx_pip_dsa_vid_grp_s {
1613 #ifdef __BIG_ENDIAN_BITFIELD
1614 uint64_t map15 : 4; /**< DSA Group Algorithm */
1615 uint64_t map14 : 4; /**< DSA Group Algorithm */
1616 uint64_t map13 : 4; /**< DSA Group Algorithm */
1617 uint64_t map12 : 4; /**< DSA Group Algorithm */
1618 uint64_t map11 : 4; /**< DSA Group Algorithm */
1619 uint64_t map10 : 4; /**< DSA Group Algorithm */
1620 uint64_t map9 : 4; /**< DSA Group Algorithm */
1621 uint64_t map8 : 4; /**< DSA Group Algorithm */
1622 uint64_t map7 : 4; /**< DSA Group Algorithm */
1623 uint64_t map6 : 4; /**< DSA Group Algorithm */
1624 uint64_t map5 : 4; /**< DSA Group Algorithm */
1625 uint64_t map4 : 4; /**< DSA Group Algorithm */
1626 uint64_t map3 : 4; /**< DSA Group Algorithm */
1627 uint64_t map2 : 4; /**< DSA Group Algorithm */
1628 uint64_t map1 : 4; /**< DSA Group Algorithm */
1629 uint64_t map0 : 4; /**< DSA Group Algorithm
1630 Use the DSA source id to compute GRP */
1631 #else
1632 uint64_t map0 : 4;
1633 uint64_t map1 : 4;
1634 uint64_t map2 : 4;
1635 uint64_t map3 : 4;
1636 uint64_t map4 : 4;
1637 uint64_t map5 : 4;
1638 uint64_t map6 : 4;
1639 uint64_t map7 : 4;
1640 uint64_t map8 : 4;
1641 uint64_t map9 : 4;
1642 uint64_t map10 : 4;
1643 uint64_t map11 : 4;
1644 uint64_t map12 : 4;
1645 uint64_t map13 : 4;
1646 uint64_t map14 : 4;
1647 uint64_t map15 : 4;
1648 #endif
1649 } s;
1650 struct cvmx_pip_dsa_vid_grp_s cn52xx;
1651 struct cvmx_pip_dsa_vid_grp_s cn52xxp1;
1652 struct cvmx_pip_dsa_vid_grp_s cn56xx;
1653 struct cvmx_pip_dsa_vid_grp_s cn61xx;
1654 struct cvmx_pip_dsa_vid_grp_s cn63xx;
1655 struct cvmx_pip_dsa_vid_grp_s cn63xxp1;
1656 struct cvmx_pip_dsa_vid_grp_s cn66xx;
1657 struct cvmx_pip_dsa_vid_grp_s cn68xx;
1658 struct cvmx_pip_dsa_vid_grp_s cn68xxp1;
1659 struct cvmx_pip_dsa_vid_grp_s cnf71xx;
1660 };
1661 typedef union cvmx_pip_dsa_vid_grp cvmx_pip_dsa_vid_grp_t;
1662
1663 /**
1664 * cvmx_pip_frm_len_chk#
1665 *
1666 * Notes:
1667 * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, PCI RAW, and PKO loopback ports.
1668 * PIP_FRM_LEN_CHK1 is unused.
1669 */
1670 union cvmx_pip_frm_len_chkx {
1671 uint64_t u64;
1672 struct cvmx_pip_frm_len_chkx_s {
1673 #ifdef __BIG_ENDIAN_BITFIELD
1674 uint64_t reserved_32_63 : 32;
1675 uint64_t maxlen : 16; /**< Byte count for Max-sized frame check
1676 PIP_PRT_CFGn[MAXERR_EN] enables the check for
1677 port n.
1678 If enabled, failing packets set the MAXERR
1679 interrupt and work-queue entry WORD2[opcode] is
1680 set to OVER_FCS (0x3, if packet has bad FCS) or
1681 OVER_ERR (0x4, if packet has good FCS).
1682 The effective MAXLEN used by HW is
1683 PIP_PRT_CFG[DSA_EN] == 0,
1684 PIP_FRM_LEN_CHK[MAXLEN] + 4*VV + 4*VS
1685 PIP_PRT_CFG[DSA_EN] == 1,
1686 PIP_FRM_LEN_CHK[MAXLEN] + PIP_PRT_CFG[SKIP]+4*VS
1687 If PTP_MODE, the 8B timestamp is prepended to the
1688 packet. MAXLEN should be increased by 8 to
1689 compensate for the additional timestamp field. */
1690 uint64_t minlen : 16; /**< Byte count for Min-sized frame check
1691 PIP_PRT_CFGn[MINERR_EN] enables the check for
1692 port n.
1693 If enabled, failing packets set the MINERR
1694 interrupt and work-queue entry WORD2[opcode] is
1695 set to UNDER_FCS (0x6, if packet has bad FCS) or
1696 UNDER_ERR (0x8, if packet has good FCS).
1697 If PTP_MODE, the 8B timestamp is prepended to the
1698 packet. MINLEN should be increased by 8 to
1699 compensate for the additional timestamp field. */
1700 #else
1701 uint64_t minlen : 16;
1702 uint64_t maxlen : 16;
1703 uint64_t reserved_32_63 : 32;
1704 #endif
1705 } s;
1706 struct cvmx_pip_frm_len_chkx_s cn50xx;
1707 struct cvmx_pip_frm_len_chkx_s cn52xx;
1708 struct cvmx_pip_frm_len_chkx_s cn52xxp1;
1709 struct cvmx_pip_frm_len_chkx_s cn56xx;
1710 struct cvmx_pip_frm_len_chkx_s cn56xxp1;
1711 struct cvmx_pip_frm_len_chkx_s cn61xx;
1712 struct cvmx_pip_frm_len_chkx_s cn63xx;
1713 struct cvmx_pip_frm_len_chkx_s cn63xxp1;
1714 struct cvmx_pip_frm_len_chkx_s cn66xx;
1715 struct cvmx_pip_frm_len_chkx_s cn68xx;
1716 struct cvmx_pip_frm_len_chkx_s cn68xxp1;
1717 struct cvmx_pip_frm_len_chkx_s cnf71xx;
1718 };
1719 typedef union cvmx_pip_frm_len_chkx cvmx_pip_frm_len_chkx_t;
1720
1721 /**
1722 * cvmx_pip_gbl_cfg
1723 *
1724 * PIP_GBL_CFG = PIP's Global Config Register
1725 *
1726 * Global config information that applies to all ports.
1727 *
1728 * Notes:
1729 * * IP6_UDP
1730 * IPv4 allows optional UDP checksum by sending the all 0's patterns. IPv6
1731 * outlaws this and the spec says to always check UDP checksum. This mode
1732 * bit allows the user to treat IPv6 as IPv4, meaning that the all 0's
1733 * pattern will cause a UDP checksum pass.
1734 */
1735 union cvmx_pip_gbl_cfg {
1736 uint64_t u64;
1737 struct cvmx_pip_gbl_cfg_s {
1738 #ifdef __BIG_ENDIAN_BITFIELD
1739 uint64_t reserved_19_63 : 45;
1740 uint64_t tag_syn : 1; /**< Do not include src_crc for TCP/SYN&!ACK packets
1741 0 = include src_crc
1742 1 = tag hash is dst_crc for TCP/SYN&!ACK packets */
1743 uint64_t ip6_udp : 1; /**< IPv6/UDP checksum is not optional
1744 0 = Allow optional checksum code
1745 1 = Do not allow optional checksum code */
1746 uint64_t max_l2 : 1; /**< Config bit to choose the largest L2 frame size
1747 Chooses the value of the L2 Type/Length field
1748 to classify the frame as length.
1749 0 = 1500 / 0x5dc
1750 1 = 1535 / 0x5ff */
1751 uint64_t reserved_11_15 : 5;
1752 uint64_t raw_shf : 3; /**< RAW Packet shift amount
1753 Number of bytes to pad a RAW packet. */
1754 uint64_t reserved_3_7 : 5;
1755 uint64_t nip_shf : 3; /**< Non-IP shift amount
1756 Number of bytes to pad a packet that has been
1757 classified as not IP. */
1758 #else
1759 uint64_t nip_shf : 3;
1760 uint64_t reserved_3_7 : 5;
1761 uint64_t raw_shf : 3;
1762 uint64_t reserved_11_15 : 5;
1763 uint64_t max_l2 : 1;
1764 uint64_t ip6_udp : 1;
1765 uint64_t tag_syn : 1;
1766 uint64_t reserved_19_63 : 45;
1767 #endif
1768 } s;
1769 struct cvmx_pip_gbl_cfg_s cn30xx;
1770 struct cvmx_pip_gbl_cfg_s cn31xx;
1771 struct cvmx_pip_gbl_cfg_s cn38xx;
1772 struct cvmx_pip_gbl_cfg_s cn38xxp2;
1773 struct cvmx_pip_gbl_cfg_s cn50xx;
1774 struct cvmx_pip_gbl_cfg_s cn52xx;
1775 struct cvmx_pip_gbl_cfg_s cn52xxp1;
1776 struct cvmx_pip_gbl_cfg_s cn56xx;
1777 struct cvmx_pip_gbl_cfg_s cn56xxp1;
1778 struct cvmx_pip_gbl_cfg_s cn58xx;
1779 struct cvmx_pip_gbl_cfg_s cn58xxp1;
1780 struct cvmx_pip_gbl_cfg_s cn61xx;
1781 struct cvmx_pip_gbl_cfg_s cn63xx;
1782 struct cvmx_pip_gbl_cfg_s cn63xxp1;
1783 struct cvmx_pip_gbl_cfg_s cn66xx;
1784 struct cvmx_pip_gbl_cfg_s cn68xx;
1785 struct cvmx_pip_gbl_cfg_s cn68xxp1;
1786 struct cvmx_pip_gbl_cfg_s cnf71xx;
1787 };
1788 typedef union cvmx_pip_gbl_cfg cvmx_pip_gbl_cfg_t;
1789
1790 /**
1791 * cvmx_pip_gbl_ctl
1792 *
1793 * PIP_GBL_CTL = PIP's Global Control Register
1794 *
1795 * Global control information. These are the global checker enables for
1796 * IPv4/IPv6 and TCP/UDP parsing. The enables effect all ports.
1797 *
1798 * Notes:
1799 * The following text describes the conditions in which each checker will
1800 * assert and flag an exception. By disabling the checker, the exception will
1801 * not be flagged and the packet will be parsed as best it can. Note, by
1802 * disabling conditions, packets can be parsed incorrectly (.i.e. IP_MAL and
1803 * L4_MAL could cause bits to be seen in the wrong place. IP_CHK and L4_CHK
1804 * means that the packet was corrupted).
1805 *
1806 * * IP_CHK
1807 * Indicates that an IPv4 packet contained an IPv4 header checksum
1808 * violations. Only applies to packets classified as IPv4.
1809 *
1810 * * IP_MAL
1811 * Indicates that the packet was malformed. Malformed packets are defined as
1812 * packets that are not long enough to cover the IP header or not long enough
1813 * to cover the length in the IP header.
1814 *
1815 * * IP_HOP
1816 * Indicates that the IPv4 TTL field or IPv6 HOP field is zero.
1817 *
1818 * * IP4_OPTS
1819 * Indicates the presence of IPv4 options. It is set when the length != 5.
1820 * This only applies to packets classified as IPv4.
1821 *
1822 * * IP6_EEXT
1823 * Indicate the presence of IPv6 early extension headers. These bits only
1824 * apply to packets classified as IPv6. Bit 0 will flag early extensions
1825 * when next_header is any one of the following...
1826 *
1827 * - hop-by-hop (0)
1828 * - destination (60)
1829 * - routing (43)
1830 *
1831 * Bit 1 will flag early extentions when next_header is NOT any of the
1832 * following...
1833 *
1834 * - TCP (6)
1835 * - UDP (17)
1836 * - fragmentation (44)
1837 * - ICMP (58)
1838 * - IPSEC ESP (50)
1839 * - IPSEC AH (51)
1840 * - IPCOMP
1841 *
1842 * * L4_MAL
1843 * Indicates that a TCP or UDP packet is not long enough to cover the TCP or
1844 * UDP header.
1845 *
1846 * * L4_PRT
1847 * Indicates that a TCP or UDP packet has an illegal port number - either the
1848 * source or destination port is zero.
1849 *
1850 * * L4_CHK
1851 * Indicates that a packet classified as either TCP or UDP contains an L4
1852 * checksum failure
1853 *
1854 * * L4_LEN
1855 * Indicates that the TCP or UDP length does not match the the IP length.
1856 *
1857 * * TCP_FLAG
1858 * Indicates any of the following conditions...
1859 *
1860 * [URG, ACK, PSH, RST, SYN, FIN] : tcp_flag
1861 * 6'b000001: (FIN only)
1862 * 6'b000000: (0)
1863 * 6'bxxx1x1: (RST+FIN+*)
1864 * 6'b1xxx1x: (URG+SYN+*)
1865 * 6'bxxx11x: (RST+SYN+*)
1866 * 6'bxxxx11: (SYN+FIN+*)
1867 */
1868 union cvmx_pip_gbl_ctl {
1869 uint64_t u64;
1870 struct cvmx_pip_gbl_ctl_s {
1871 #ifdef __BIG_ENDIAN_BITFIELD
1872 uint64_t reserved_29_63 : 35;
1873 uint64_t egrp_dis : 1; /**< PKT_INST_HDR extended group field disable
1874 When set, HW will ignore the EGRP field of the
1875 PKT_INST_HDR - bits 47:46. */
1876 uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable
1877 0=Allow NTAG,NTT,NGRP,NQOS bits in the
1878 instruction header to control which fields from
1879 the instruction header are used for WQE WORD2.
1880 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
1881 instruction header and act as if these fields
1882 were zero. Thus always use the TAG,TT,GRP,QOS
1883 (depending on the instruction header length)
1884 from the instruction header for the WQE WORD2. */
1885 uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm
1886 Use the DSA source id to compute GRP */
1887 uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm
1888 Use the DSA source id to compute GRP when the
1889 DSA tag command to TO_CPU */
1890 uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm
1891 Use the DSA VLAN id to compute GRP */
1892 uint64_t reserved_21_23 : 3;
1893 uint64_t ring_en : 1; /**< Enable DPI ring information in WQE */
1894 uint64_t reserved_17_19 : 3;
1895 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set
1896 Does not apply to DPI ports (32-35)
1897 When using 2-byte instruction header words,
1898 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
1899 uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
1900 0=use the 1st (network order) VLAN
1901 1=use the 2nd (network order) VLAN */
1902 uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking
1903 0=use the 1st (network order) VLAN
1904 1=use the 2nd (network order) VLAN */
1905 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */
1906 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */
1907 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */
1908 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */
1909 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */
1910 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */
1911 uint64_t reserved_6_7 : 2;
1912 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */
1913 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */
1914 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */
1915 uint64_t ip_mal : 1; /**< Enable malformed check */
1916 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */
1917 #else
1918 uint64_t ip_chk : 1;
1919 uint64_t ip_mal : 1;
1920 uint64_t ip_hop : 1;
1921 uint64_t ip4_opts : 1;
1922 uint64_t ip6_eext : 2;
1923 uint64_t reserved_6_7 : 2;
1924 uint64_t l4_mal : 1;
1925 uint64_t l4_prt : 1;
1926 uint64_t l4_chk : 1;
1927 uint64_t l4_len : 1;
1928 uint64_t tcp_flag : 1;
1929 uint64_t l2_mal : 1;
1930 uint64_t vs_qos : 1;
1931 uint64_t vs_wqe : 1;
1932 uint64_t ignrs : 1;
1933 uint64_t reserved_17_19 : 3;
1934 uint64_t ring_en : 1;
1935 uint64_t reserved_21_23 : 3;
1936 uint64_t dsa_grp_sid : 1;
1937 uint64_t dsa_grp_scmd : 1;
1938 uint64_t dsa_grp_tvid : 1;
1939 uint64_t ihmsk_dis : 1;
1940 uint64_t egrp_dis : 1;
1941 uint64_t reserved_29_63 : 35;
1942 #endif
1943 } s;
1944 struct cvmx_pip_gbl_ctl_cn30xx {
1945 #ifdef __BIG_ENDIAN_BITFIELD
1946 uint64_t reserved_17_63 : 47;
1947 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set
1948 Only applies to the packet interface prts (0-31)
1949 When using 2-byte instruction header words,
1950 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
1951 uint64_t vs_wqe : 1; /**< Which VLAN CFI and ID to use when VLAN Stacking
1952 0=use the 1st (network order) VLAN
1953 1=use the 2nd (network order) VLAN */
1954 uint64_t vs_qos : 1; /**< Which VLAN priority to use when VLAN Stacking
1955 0=use the 1st (network order) VLAN
1956 1=use the 2nd (network order) VLAN */
1957 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */
1958 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */
1959 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */
1960 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */
1961 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */
1962 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */
1963 uint64_t reserved_6_7 : 2;
1964 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */
1965 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */
1966 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */
1967 uint64_t ip_mal : 1; /**< Enable malformed check */
1968 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */
1969 #else
1970 uint64_t ip_chk : 1;
1971 uint64_t ip_mal : 1;
1972 uint64_t ip_hop : 1;
1973 uint64_t ip4_opts : 1;
1974 uint64_t ip6_eext : 2;
1975 uint64_t reserved_6_7 : 2;
1976 uint64_t l4_mal : 1;
1977 uint64_t l4_prt : 1;
1978 uint64_t l4_chk : 1;
1979 uint64_t l4_len : 1;
1980 uint64_t tcp_flag : 1;
1981 uint64_t l2_mal : 1;
1982 uint64_t vs_qos : 1;
1983 uint64_t vs_wqe : 1;
1984 uint64_t ignrs : 1;
1985 uint64_t reserved_17_63 : 47;
1986 #endif
1987 } cn30xx;
1988 struct cvmx_pip_gbl_ctl_cn30xx cn31xx;
1989 struct cvmx_pip_gbl_ctl_cn30xx cn38xx;
1990 struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;
1991 struct cvmx_pip_gbl_ctl_cn30xx cn50xx;
1992 struct cvmx_pip_gbl_ctl_cn52xx {
1993 #ifdef __BIG_ENDIAN_BITFIELD
1994 uint64_t reserved_27_63 : 37;
1995 uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm
1996 Use the DSA source id to compute GRP */
1997 uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm
1998 Use the DSA source id to compute GRP when the
1999 DSA tag command to TO_CPU */
2000 uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm
2001 Use the DSA VLAN id to compute GRP */
2002 uint64_t reserved_21_23 : 3;
2003 uint64_t ring_en : 1; /**< Enable PCIe ring information in WQE */
2004 uint64_t reserved_17_19 : 3;
2005 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set
2006 Does not apply to PCI ports (32-35)
2007 When using 2-byte instruction header words,
2008 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
2009 uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
2010 0=use the 1st (network order) VLAN
2011 1=use the 2nd (network order) VLAN */
2012 uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking
2013 0=use the 1st (network order) VLAN
2014 1=use the 2nd (network order) VLAN */
2015 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */
2016 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */
2017 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */
2018 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */
2019 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */
2020 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */
2021 uint64_t reserved_6_7 : 2;
2022 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */
2023 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */
2024 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */
2025 uint64_t ip_mal : 1; /**< Enable malformed check */
2026 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */
2027 #else
2028 uint64_t ip_chk : 1;
2029 uint64_t ip_mal : 1;
2030 uint64_t ip_hop : 1;
2031 uint64_t ip4_opts : 1;
2032 uint64_t ip6_eext : 2;
2033 uint64_t reserved_6_7 : 2;
2034 uint64_t l4_mal : 1;
2035 uint64_t l4_prt : 1;
2036 uint64_t l4_chk : 1;
2037 uint64_t l4_len : 1;
2038 uint64_t tcp_flag : 1;
2039 uint64_t l2_mal : 1;
2040 uint64_t vs_qos : 1;
2041 uint64_t vs_wqe : 1;
2042 uint64_t ignrs : 1;
2043 uint64_t reserved_17_19 : 3;
2044 uint64_t ring_en : 1;
2045 uint64_t reserved_21_23 : 3;
2046 uint64_t dsa_grp_sid : 1;
2047 uint64_t dsa_grp_scmd : 1;
2048 uint64_t dsa_grp_tvid : 1;
2049 uint64_t reserved_27_63 : 37;
2050 #endif
2051 } cn52xx;
2052 struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1;
2053 struct cvmx_pip_gbl_ctl_cn52xx cn56xx;
2054 struct cvmx_pip_gbl_ctl_cn56xxp1 {
2055 #ifdef __BIG_ENDIAN_BITFIELD
2056 uint64_t reserved_21_63 : 43;
2057 uint64_t ring_en : 1; /**< Enable PCIe ring information in WQE */
2058 uint64_t reserved_17_19 : 3;
2059 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set
2060 Does not apply to PCI ports (32-35)
2061 When using 2-byte instruction header words,
2062 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
2063 uint64_t vs_wqe : 1; /**< Which VLAN CFI and ID to use when VLAN Stacking
2064 0=use the 1st (network order) VLAN
2065 1=use the 2nd (network order) VLAN */
2066 uint64_t vs_qos : 1; /**< Which VLAN priority to use when VLAN Stacking
2067 0=use the 1st (network order) VLAN
2068 1=use the 2nd (network order) VLAN */
2069 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */
2070 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */
2071 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */
2072 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */
2073 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */
2074 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */
2075 uint64_t reserved_6_7 : 2;
2076 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */
2077 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */
2078 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */
2079 uint64_t ip_mal : 1; /**< Enable malformed check */
2080 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */
2081 #else
2082 uint64_t ip_chk : 1;
2083 uint64_t ip_mal : 1;
2084 uint64_t ip_hop : 1;
2085 uint64_t ip4_opts : 1;
2086 uint64_t ip6_eext : 2;
2087 uint64_t reserved_6_7 : 2;
2088 uint64_t l4_mal : 1;
2089 uint64_t l4_prt : 1;
2090 uint64_t l4_chk : 1;
2091 uint64_t l4_len : 1;
2092 uint64_t tcp_flag : 1;
2093 uint64_t l2_mal : 1;
2094 uint64_t vs_qos : 1;
2095 uint64_t vs_wqe : 1;
2096 uint64_t ignrs : 1;
2097 uint64_t reserved_17_19 : 3;
2098 uint64_t ring_en : 1;
2099 uint64_t reserved_21_63 : 43;
2100 #endif
2101 } cn56xxp1;
2102 struct cvmx_pip_gbl_ctl_cn30xx cn58xx;
2103 struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;
2104 struct cvmx_pip_gbl_ctl_cn61xx {
2105 #ifdef __BIG_ENDIAN_BITFIELD
2106 uint64_t reserved_28_63 : 36;
2107 uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable
2108 0=Allow NTAG,NTT,NGRP,NQOS bits in the
2109 instruction header to control which fields from
2110 the instruction header are used for WQE WORD2.
2111 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
2112 instruction header and act as if these fields
2113 were zero. Thus always use the TAG,TT,GRP,QOS
2114 (depending on the instruction header length)
2115 from the instruction header for the WQE WORD2. */
2116 uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm
2117 Use the DSA source id to compute GRP */
2118 uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm
2119 Use the DSA source id to compute GRP when the
2120 DSA tag command to TO_CPU */
2121 uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm
2122 Use the DSA VLAN id to compute GRP */
2123 uint64_t reserved_21_23 : 3;
2124 uint64_t ring_en : 1; /**< Enable DPI ring information in WQE */
2125 uint64_t reserved_17_19 : 3;
2126 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set
2127 Does not apply to DPI ports (32-35)
2128 When using 2-byte instruction header words,
2129 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
2130 uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
2131 0=use the 1st (network order) VLAN
2132 1=use the 2nd (network order) VLAN */
2133 uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking
2134 0=use the 1st (network order) VLAN
2135 1=use the 2nd (network order) VLAN */
2136 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */
2137 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */
2138 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */
2139 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */
2140 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */
2141 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */
2142 uint64_t reserved_6_7 : 2;
2143 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */
2144 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */
2145 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */
2146 uint64_t ip_mal : 1; /**< Enable malformed check */
2147 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */
2148 #else
2149 uint64_t ip_chk : 1;
2150 uint64_t ip_mal : 1;
2151 uint64_t ip_hop : 1;
2152 uint64_t ip4_opts : 1;
2153 uint64_t ip6_eext : 2;
2154 uint64_t reserved_6_7 : 2;
2155 uint64_t l4_mal : 1;
2156 uint64_t l4_prt : 1;
2157 uint64_t l4_chk : 1;
2158 uint64_t l4_len : 1;
2159 uint64_t tcp_flag : 1;
2160 uint64_t l2_mal : 1;
2161 uint64_t vs_qos : 1;
2162 uint64_t vs_wqe : 1;
2163 uint64_t ignrs : 1;
2164 uint64_t reserved_17_19 : 3;
2165 uint64_t ring_en : 1;
2166 uint64_t reserved_21_23 : 3;
2167 uint64_t dsa_grp_sid : 1;
2168 uint64_t dsa_grp_scmd : 1;
2169 uint64_t dsa_grp_tvid : 1;
2170 uint64_t ihmsk_dis : 1;
2171 uint64_t reserved_28_63 : 36;
2172 #endif
2173 } cn61xx;
2174 struct cvmx_pip_gbl_ctl_cn61xx cn63xx;
2175 struct cvmx_pip_gbl_ctl_cn61xx cn63xxp1;
2176 struct cvmx_pip_gbl_ctl_cn61xx cn66xx;
2177 struct cvmx_pip_gbl_ctl_cn68xx {
2178 #ifdef __BIG_ENDIAN_BITFIELD
2179 uint64_t reserved_29_63 : 35;
2180 uint64_t egrp_dis : 1; /**< PKT_INST_HDR extended group field disable
2181 When set, HW will ignore the EGRP field of the
2182 PKT_INST_HDR - bits 47:46. */
2183 uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable
2184 0=Allow NTAG,NTT,NGRP,NQOS bits in the
2185 instruction header to control which fields from
2186 the instruction header are used for WQE WORD2.
2187 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
2188 instruction header and act as if these fields
2189 were zero. Thus always use the TAG,TT,GRP,QOS
2190 (depending on the instruction header length)
2191 from the instruction header for the WQE WORD2. */
2192 uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm
2193 Use the DSA source id to compute GRP */
2194 uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm
2195 Use the DSA source id to compute GRP when the
2196 DSA tag command to TO_CPU */
2197 uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm
2198 Use the DSA VLAN id to compute GRP */
2199 uint64_t reserved_17_23 : 7;
2200 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set
2201 When using 2-byte instruction header words,
2202 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
2203 uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
2204 0=use the 1st (network order) VLAN
2205 1=use the 2nd (network order) VLAN */
2206 uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking
2207 0=use the 1st (network order) VLAN
2208 1=use the 2nd (network order) VLAN */
2209 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */
2210 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */
2211 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */
2212 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */
2213 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */
2214 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */
2215 uint64_t reserved_6_7 : 2;
2216 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */
2217 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */
2218 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */
2219 uint64_t ip_mal : 1; /**< Enable malformed check */
2220 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */
2221 #else
2222 uint64_t ip_chk : 1;
2223 uint64_t ip_mal : 1;
2224 uint64_t ip_hop : 1;
2225 uint64_t ip4_opts : 1;
2226 uint64_t ip6_eext : 2;
2227 uint64_t reserved_6_7 : 2;
2228 uint64_t l4_mal : 1;
2229 uint64_t l4_prt : 1;
2230 uint64_t l4_chk : 1;
2231 uint64_t l4_len : 1;
2232 uint64_t tcp_flag : 1;
2233 uint64_t l2_mal : 1;
2234 uint64_t vs_qos : 1;
2235 uint64_t vs_wqe : 1;
2236 uint64_t ignrs : 1;
2237 uint64_t reserved_17_23 : 7;
2238 uint64_t dsa_grp_sid : 1;
2239 uint64_t dsa_grp_scmd : 1;
2240 uint64_t dsa_grp_tvid : 1;
2241 uint64_t ihmsk_dis : 1;
2242 uint64_t egrp_dis : 1;
2243 uint64_t reserved_29_63 : 35;
2244 #endif
2245 } cn68xx;
2246 struct cvmx_pip_gbl_ctl_cn68xxp1 {
2247 #ifdef __BIG_ENDIAN_BITFIELD
2248 uint64_t reserved_28_63 : 36;
2249 uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable
2250 0=Allow NTAG,NTT,NGRP,NQOS bits in the
2251 instruction header to control which fields from
2252 the instruction header are used for WQE WORD2.
2253 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the
2254 instruction header and act as if these fields
2255 were zero. Thus always use the TAG,TT,GRP,QOS
2256 (depending on the instruction header length)
2257 from the instruction header for the WQE WORD2. */
2258 uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm
2259 Use the DSA source id to compute GRP */
2260 uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm
2261 Use the DSA source id to compute GRP when the
2262 DSA tag command to TO_CPU */
2263 uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm
2264 Use the DSA VLAN id to compute GRP */
2265 uint64_t reserved_17_23 : 7;
2266 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set
2267 When using 2-byte instruction header words,
2268 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */
2269 uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking
2270 0=use the 1st (network order) VLAN
2271 1=use the 2nd (network order) VLAN */
2272 uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking
2273 0=use the 1st (network order) VLAN
2274 1=use the 2nd (network order) VLAN */
2275 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */
2276 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */
2277 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */
2278 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */
2279 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */
2280 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */
2281 uint64_t reserved_6_7 : 2;
2282 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */
2283 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */
2284 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */
2285 uint64_t ip_mal : 1; /**< Enable malformed check */
2286 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */
2287 #else
2288 uint64_t ip_chk : 1;
2289 uint64_t ip_mal : 1;
2290 uint64_t ip_hop : 1;
2291 uint64_t ip4_opts : 1;
2292 uint64_t ip6_eext : 2;
2293 uint64_t reserved_6_7 : 2;
2294 uint64_t l4_mal : 1;
2295 uint64_t l4_prt : 1;
2296 uint64_t l4_chk : 1;
2297 uint64_t l4_len : 1;
2298 uint64_t tcp_flag : 1;
2299 uint64_t l2_mal : 1;
2300 uint64_t vs_qos : 1;
2301 uint64_t vs_wqe : 1;
2302 uint64_t ignrs : 1;
2303 uint64_t reserved_17_23 : 7;
2304 uint64_t dsa_grp_sid : 1;
2305 uint64_t dsa_grp_scmd : 1;
2306 uint64_t dsa_grp_tvid : 1;
2307 uint64_t ihmsk_dis : 1;
2308 uint64_t reserved_28_63 : 36;
2309 #endif
2310 } cn68xxp1;
2311 struct cvmx_pip_gbl_ctl_cn61xx cnf71xx;
2312 };
2313 typedef union cvmx_pip_gbl_ctl cvmx_pip_gbl_ctl_t;
2314
2315 /**
2316 * cvmx_pip_hg_pri_qos
2317 *
2318 * Notes:
2319 * This register controls accesses to the HG_QOS_TABLE. To write an entry of
2320 * the table, write PIP_HG_PRI_QOS with PRI=table address, QOS=priority level,
2321 * UP_QOS=1. To read an entry of the table, write PIP_HG_PRI_QOS with
2322 * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read
2323 * PIP_HG_PRI_QOS. The table data will be in PIP_HG_PRI_QOS[QOS].
2324 */
2325 union cvmx_pip_hg_pri_qos {
2326 uint64_t u64;
2327 struct cvmx_pip_hg_pri_qos_s {
2328 #ifdef __BIG_ENDIAN_BITFIELD
2329 uint64_t reserved_13_63 : 51;
2330 uint64_t up_qos : 1; /**< When written to '1', updates the entry in the
2331 HG_QOS_TABLE as specified by PRI to a value of
2332 QOS as follows
2333 HG_QOS_TABLE[PRI] = QOS */
2334 uint64_t reserved_11_11 : 1;
2335 uint64_t qos : 3; /**< QOS Map level to priority */
2336 uint64_t reserved_6_7 : 2;
2337 uint64_t pri : 6; /**< The priority level from HiGig header
2338 HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]]
2339 HiGig2 PRI = [DP[1:0], TC[3:0]] */
2340 #else
2341 uint64_t pri : 6;
2342 uint64_t reserved_6_7 : 2;
2343 uint64_t qos : 3;
2344 uint64_t reserved_11_11 : 1;
2345 uint64_t up_qos : 1;
2346 uint64_t reserved_13_63 : 51;
2347 #endif
2348 } s;
2349 struct cvmx_pip_hg_pri_qos_s cn52xx;
2350 struct cvmx_pip_hg_pri_qos_s cn52xxp1;
2351 struct cvmx_pip_hg_pri_qos_s cn56xx;
2352 struct cvmx_pip_hg_pri_qos_s cn61xx;
2353 struct cvmx_pip_hg_pri_qos_s cn63xx;
2354 struct cvmx_pip_hg_pri_qos_s cn63xxp1;
2355 struct cvmx_pip_hg_pri_qos_s cn66xx;
2356 struct cvmx_pip_hg_pri_qos_s cnf71xx;
2357 };
2358 typedef union cvmx_pip_hg_pri_qos cvmx_pip_hg_pri_qos_t;
2359
2360 /**
2361 * cvmx_pip_int_en
2362 *
2363 * PIP_INT_EN = PIP's Interrupt Enable Register
2364 *
2365 * Determines if hardward should raise an interrupt to software
2366 * when an exception event occurs.
2367 */
2368 union cvmx_pip_int_en {
2369 uint64_t u64;
2370 struct cvmx_pip_int_en_s {
2371 #ifdef __BIG_ENDIAN_BITFIELD
2372 uint64_t reserved_13_63 : 51;
2373 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC
2374 stripping in IPD is enable */
2375 uint64_t lenerr : 1; /**< Frame was received with length error */
2376 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2377 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2378 uint64_t beperr : 1; /**< Parity Error in back end memory */
2379 uint64_t feperr : 1; /**< Parity Error in front end memory */
2380 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
2381 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */
2382 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2383 uint64_t prtnxa : 1; /**< Non-existent port */
2384 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2385 uint64_t crcerr : 1; /**< PIP calculated bad CRC */
2386 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2387 #else
2388 uint64_t pktdrp : 1;
2389 uint64_t crcerr : 1;
2390 uint64_t bckprs : 1;
2391 uint64_t prtnxa : 1;
2392 uint64_t badtag : 1;
2393 uint64_t skprunt : 1;
2394 uint64_t todoovr : 1;
2395 uint64_t feperr : 1;
2396 uint64_t beperr : 1;
2397 uint64_t minerr : 1;
2398 uint64_t maxerr : 1;
2399 uint64_t lenerr : 1;
2400 uint64_t punyerr : 1;
2401 uint64_t reserved_13_63 : 51;
2402 #endif
2403 } s;
2404 struct cvmx_pip_int_en_cn30xx {
2405 #ifdef __BIG_ENDIAN_BITFIELD
2406 uint64_t reserved_9_63 : 55;
2407 uint64_t beperr : 1; /**< Parity Error in back end memory */
2408 uint64_t feperr : 1; /**< Parity Error in front end memory */
2409 uint64_t todoovr : 1; /**< Todo list overflow
2410 (not used in O2P) */
2411 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */
2412 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2413 uint64_t prtnxa : 1; /**< Non-existent port */
2414 uint64_t bckprs : 1; /**< PIP asserted backpressure
2415 (not used in O2P) */
2416 uint64_t crcerr : 1; /**< PIP calculated bad CRC
2417 (not used in O2P) */
2418 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2419 #else
2420 uint64_t pktdrp : 1;
2421 uint64_t crcerr : 1;
2422 uint64_t bckprs : 1;
2423 uint64_t prtnxa : 1;
2424 uint64_t badtag : 1;
2425 uint64_t skprunt : 1;
2426 uint64_t todoovr : 1;
2427 uint64_t feperr : 1;
2428 uint64_t beperr : 1;
2429 uint64_t reserved_9_63 : 55;
2430 #endif
2431 } cn30xx;
2432 struct cvmx_pip_int_en_cn30xx cn31xx;
2433 struct cvmx_pip_int_en_cn30xx cn38xx;
2434 struct cvmx_pip_int_en_cn30xx cn38xxp2;
2435 struct cvmx_pip_int_en_cn50xx {
2436 #ifdef __BIG_ENDIAN_BITFIELD
2437 uint64_t reserved_12_63 : 52;
2438 uint64_t lenerr : 1; /**< Frame was received with length error */
2439 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2440 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2441 uint64_t beperr : 1; /**< Parity Error in back end memory */
2442 uint64_t feperr : 1; /**< Parity Error in front end memory */
2443 uint64_t todoovr : 1; /**< Todo list overflow */
2444 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */
2445 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2446 uint64_t prtnxa : 1; /**< Non-existent port */
2447 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2448 uint64_t reserved_1_1 : 1;
2449 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2450 #else
2451 uint64_t pktdrp : 1;
2452 uint64_t reserved_1_1 : 1;
2453 uint64_t bckprs : 1;
2454 uint64_t prtnxa : 1;
2455 uint64_t badtag : 1;
2456 uint64_t skprunt : 1;
2457 uint64_t todoovr : 1;
2458 uint64_t feperr : 1;
2459 uint64_t beperr : 1;
2460 uint64_t minerr : 1;
2461 uint64_t maxerr : 1;
2462 uint64_t lenerr : 1;
2463 uint64_t reserved_12_63 : 52;
2464 #endif
2465 } cn50xx;
2466 struct cvmx_pip_int_en_cn52xx {
2467 #ifdef __BIG_ENDIAN_BITFIELD
2468 uint64_t reserved_13_63 : 51;
2469 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC
2470 stripping in IPD is enable */
2471 uint64_t lenerr : 1; /**< Frame was received with length error */
2472 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2473 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2474 uint64_t beperr : 1; /**< Parity Error in back end memory */
2475 uint64_t feperr : 1; /**< Parity Error in front end memory */
2476 uint64_t todoovr : 1; /**< Todo list overflow */
2477 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */
2478 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2479 uint64_t prtnxa : 1; /**< Non-existent port */
2480 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2481 uint64_t reserved_1_1 : 1;
2482 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2483 #else
2484 uint64_t pktdrp : 1;
2485 uint64_t reserved_1_1 : 1;
2486 uint64_t bckprs : 1;
2487 uint64_t prtnxa : 1;
2488 uint64_t badtag : 1;
2489 uint64_t skprunt : 1;
2490 uint64_t todoovr : 1;
2491 uint64_t feperr : 1;
2492 uint64_t beperr : 1;
2493 uint64_t minerr : 1;
2494 uint64_t maxerr : 1;
2495 uint64_t lenerr : 1;
2496 uint64_t punyerr : 1;
2497 uint64_t reserved_13_63 : 51;
2498 #endif
2499 } cn52xx;
2500 struct cvmx_pip_int_en_cn52xx cn52xxp1;
2501 struct cvmx_pip_int_en_s cn56xx;
2502 struct cvmx_pip_int_en_cn56xxp1 {
2503 #ifdef __BIG_ENDIAN_BITFIELD
2504 uint64_t reserved_12_63 : 52;
2505 uint64_t lenerr : 1; /**< Frame was received with length error */
2506 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2507 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2508 uint64_t beperr : 1; /**< Parity Error in back end memory */
2509 uint64_t feperr : 1; /**< Parity Error in front end memory */
2510 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
2511 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */
2512 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2513 uint64_t prtnxa : 1; /**< Non-existent port */
2514 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2515 uint64_t crcerr : 1; /**< PIP calculated bad CRC
2516 (Disabled in 56xx) */
2517 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2518 #else
2519 uint64_t pktdrp : 1;
2520 uint64_t crcerr : 1;
2521 uint64_t bckprs : 1;
2522 uint64_t prtnxa : 1;
2523 uint64_t badtag : 1;
2524 uint64_t skprunt : 1;
2525 uint64_t todoovr : 1;
2526 uint64_t feperr : 1;
2527 uint64_t beperr : 1;
2528 uint64_t minerr : 1;
2529 uint64_t maxerr : 1;
2530 uint64_t lenerr : 1;
2531 uint64_t reserved_12_63 : 52;
2532 #endif
2533 } cn56xxp1;
2534 struct cvmx_pip_int_en_cn58xx {
2535 #ifdef __BIG_ENDIAN_BITFIELD
2536 uint64_t reserved_13_63 : 51;
2537 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC
2538 stripping in IPD is enable */
2539 uint64_t reserved_9_11 : 3;
2540 uint64_t beperr : 1; /**< Parity Error in back end memory */
2541 uint64_t feperr : 1; /**< Parity Error in front end memory */
2542 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
2543 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */
2544 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2545 uint64_t prtnxa : 1; /**< Non-existent port */
2546 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2547 uint64_t crcerr : 1; /**< PIP calculated bad CRC */
2548 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2549 #else
2550 uint64_t pktdrp : 1;
2551 uint64_t crcerr : 1;
2552 uint64_t bckprs : 1;
2553 uint64_t prtnxa : 1;
2554 uint64_t badtag : 1;
2555 uint64_t skprunt : 1;
2556 uint64_t todoovr : 1;
2557 uint64_t feperr : 1;
2558 uint64_t beperr : 1;
2559 uint64_t reserved_9_11 : 3;
2560 uint64_t punyerr : 1;
2561 uint64_t reserved_13_63 : 51;
2562 #endif
2563 } cn58xx;
2564 struct cvmx_pip_int_en_cn30xx cn58xxp1;
2565 struct cvmx_pip_int_en_s cn61xx;
2566 struct cvmx_pip_int_en_s cn63xx;
2567 struct cvmx_pip_int_en_s cn63xxp1;
2568 struct cvmx_pip_int_en_s cn66xx;
2569 struct cvmx_pip_int_en_s cn68xx;
2570 struct cvmx_pip_int_en_s cn68xxp1;
2571 struct cvmx_pip_int_en_s cnf71xx;
2572 };
2573 typedef union cvmx_pip_int_en cvmx_pip_int_en_t;
2574
2575 /**
2576 * cvmx_pip_int_reg
2577 *
2578 * PIP_INT_REG = PIP's Interrupt Register
2579 *
2580 * Any exception event that occurs is captured in the PIP_INT_REG.
2581 * PIP_INT_REG will set the exception bit regardless of the value
2582 * of PIP_INT_EN. PIP_INT_EN only controls if an interrupt is
2583 * raised to software.
2584 *
2585 * Notes:
2586 * * TODOOVR
2587 * The PIP Todo list stores packets that have been received and require work
2588 * queue entry generation. PIP will normally assert backpressure when the
2589 * list fills up such that any error is normally is result of a programming
2590 * the PIP_BCK_PRS[HIWATER] incorrectly. PIP itself can handle 29M
2591 * packets/sec X500MHz or 15Gbs X 64B packets.
2592 *
2593 * * SKPRUNT
2594 * If a packet size is less then the amount programmed in the per port
2595 * skippers, then there will be nothing to parse and the entire packet will
2596 * basically be skipped over. This is probably not what the user desired, so
2597 * there is an indication to software.
2598 *
2599 * * BADTAG
2600 * A tag is considered bad when it is resued by a new packet before it was
2601 * released by PIP. PIP considers a tag released by one of two methods.
2602 * . QOS dropped so that it is released over the pip__ipd_release bus.
2603 * . WorkQ entry is validated by the pip__ipd_done signal
2604 *
2605 * * PRTNXA
2606 * If PIP receives a packet that is not in the valid port range, the port
2607 * processed will be mapped into the valid port space (the mapping is
2608 * currently unpredictable) and the PRTNXA bit will be set. PRTNXA will be
2609 * set for packets received under the following conditions:
2610 *
2611 * * packet ports (ports 0-31)
2612 * - GMX_INF_MODE[TYPE]==0 (SGMII), received port is 4-15 or 20-31
2613 * - GMX_INF_MODE[TYPE]==1 (XAUI), received port is 1-15 or 17-31
2614 * * upper ports (pci and loopback ports 32-63)
2615 * - received port is 40-47 or 52-63
2616 *
2617 * * BCKPRS
2618 * PIP can assert backpressure to the receive logic when the todo list
2619 * exceeds a high-water mark (see PIP_BCK_PRS for more details). When this
2620 * occurs, PIP can raise an interrupt to software.
2621 *
2622 * * CRCERR
2623 * Octane can compute CRC in two places. Each RGMII port will compute its
2624 * own CRC, but PIP can provide an additional check or check loopback or
2625 * PCI ports. If PIP computes a bad CRC, then PIP will raise an interrupt.
2626 *
2627 * * PKTDRP
2628 * PIP can drop packets based on QOS results received from IPD. If the QOS
2629 * algorithm decides to drop a packet, PIP will assert an interrupt.
2630 */
2631 union cvmx_pip_int_reg {
2632 uint64_t u64;
2633 struct cvmx_pip_int_reg_s {
2634 #ifdef __BIG_ENDIAN_BITFIELD
2635 uint64_t reserved_13_63 : 51;
2636 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC
2637 stripping in IPD is enable */
2638 uint64_t lenerr : 1; /**< Frame was received with length error */
2639 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2640 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2641 uint64_t beperr : 1; /**< Parity Error in back end memory */
2642 uint64_t feperr : 1; /**< Parity Error in front end memory */
2643 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
2644 uint64_t skprunt : 1; /**< Packet was engulfed by skipper
2645 This interrupt can occur with received PARTIAL
2646 packets that are truncated to SKIP bytes or
2647 smaller. */
2648 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2649 uint64_t prtnxa : 1; /**< Non-existent port */
2650 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2651 uint64_t crcerr : 1; /**< PIP calculated bad CRC */
2652 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2653 #else
2654 uint64_t pktdrp : 1;
2655 uint64_t crcerr : 1;
2656 uint64_t bckprs : 1;
2657 uint64_t prtnxa : 1;
2658 uint64_t badtag : 1;
2659 uint64_t skprunt : 1;
2660 uint64_t todoovr : 1;
2661 uint64_t feperr : 1;
2662 uint64_t beperr : 1;
2663 uint64_t minerr : 1;
2664 uint64_t maxerr : 1;
2665 uint64_t lenerr : 1;
2666 uint64_t punyerr : 1;
2667 uint64_t reserved_13_63 : 51;
2668 #endif
2669 } s;
2670 struct cvmx_pip_int_reg_cn30xx {
2671 #ifdef __BIG_ENDIAN_BITFIELD
2672 uint64_t reserved_9_63 : 55;
2673 uint64_t beperr : 1; /**< Parity Error in back end memory */
2674 uint64_t feperr : 1; /**< Parity Error in front end memory */
2675 uint64_t todoovr : 1; /**< Todo list overflow
2676 (not used in O2P) */
2677 uint64_t skprunt : 1; /**< Packet was engulfed by skipper
2678 This interrupt can occur with received PARTIAL
2679 packets that are truncated to SKIP bytes or
2680 smaller. */
2681 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2682 uint64_t prtnxa : 1; /**< Non-existent port */
2683 uint64_t bckprs : 1; /**< PIP asserted backpressure
2684 (not used in O2P) */
2685 uint64_t crcerr : 1; /**< PIP calculated bad CRC
2686 (not used in O2P) */
2687 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2688 #else
2689 uint64_t pktdrp : 1;
2690 uint64_t crcerr : 1;
2691 uint64_t bckprs : 1;
2692 uint64_t prtnxa : 1;
2693 uint64_t badtag : 1;
2694 uint64_t skprunt : 1;
2695 uint64_t todoovr : 1;
2696 uint64_t feperr : 1;
2697 uint64_t beperr : 1;
2698 uint64_t reserved_9_63 : 55;
2699 #endif
2700 } cn30xx;
2701 struct cvmx_pip_int_reg_cn30xx cn31xx;
2702 struct cvmx_pip_int_reg_cn30xx cn38xx;
2703 struct cvmx_pip_int_reg_cn30xx cn38xxp2;
2704 struct cvmx_pip_int_reg_cn50xx {
2705 #ifdef __BIG_ENDIAN_BITFIELD
2706 uint64_t reserved_12_63 : 52;
2707 uint64_t lenerr : 1; /**< Frame was received with length error */
2708 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2709 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2710 uint64_t beperr : 1; /**< Parity Error in back end memory */
2711 uint64_t feperr : 1; /**< Parity Error in front end memory */
2712 uint64_t todoovr : 1; /**< Todo list overflow */
2713 uint64_t skprunt : 1; /**< Packet was engulfed by skipper
2714 This interrupt can occur with received PARTIAL
2715 packets that are truncated to SKIP bytes or
2716 smaller. */
2717 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2718 uint64_t prtnxa : 1; /**< Non-existent port */
2719 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2720 uint64_t reserved_1_1 : 1;
2721 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2722 #else
2723 uint64_t pktdrp : 1;
2724 uint64_t reserved_1_1 : 1;
2725 uint64_t bckprs : 1;
2726 uint64_t prtnxa : 1;
2727 uint64_t badtag : 1;
2728 uint64_t skprunt : 1;
2729 uint64_t todoovr : 1;
2730 uint64_t feperr : 1;
2731 uint64_t beperr : 1;
2732 uint64_t minerr : 1;
2733 uint64_t maxerr : 1;
2734 uint64_t lenerr : 1;
2735 uint64_t reserved_12_63 : 52;
2736 #endif
2737 } cn50xx;
2738 struct cvmx_pip_int_reg_cn52xx {
2739 #ifdef __BIG_ENDIAN_BITFIELD
2740 uint64_t reserved_13_63 : 51;
2741 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC
2742 stripping in IPD is enable */
2743 uint64_t lenerr : 1; /**< Frame was received with length error */
2744 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2745 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2746 uint64_t beperr : 1; /**< Parity Error in back end memory */
2747 uint64_t feperr : 1; /**< Parity Error in front end memory */
2748 uint64_t todoovr : 1; /**< Todo list overflow */
2749 uint64_t skprunt : 1; /**< Packet was engulfed by skipper
2750 This interrupt can occur with received PARTIAL
2751 packets that are truncated to SKIP bytes or
2752 smaller. */
2753 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2754 uint64_t prtnxa : 1; /**< Non-existent port */
2755 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2756 uint64_t reserved_1_1 : 1;
2757 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2758 #else
2759 uint64_t pktdrp : 1;
2760 uint64_t reserved_1_1 : 1;
2761 uint64_t bckprs : 1;
2762 uint64_t prtnxa : 1;
2763 uint64_t badtag : 1;
2764 uint64_t skprunt : 1;
2765 uint64_t todoovr : 1;
2766 uint64_t feperr : 1;
2767 uint64_t beperr : 1;
2768 uint64_t minerr : 1;
2769 uint64_t maxerr : 1;
2770 uint64_t lenerr : 1;
2771 uint64_t punyerr : 1;
2772 uint64_t reserved_13_63 : 51;
2773 #endif
2774 } cn52xx;
2775 struct cvmx_pip_int_reg_cn52xx cn52xxp1;
2776 struct cvmx_pip_int_reg_s cn56xx;
2777 struct cvmx_pip_int_reg_cn56xxp1 {
2778 #ifdef __BIG_ENDIAN_BITFIELD
2779 uint64_t reserved_12_63 : 52;
2780 uint64_t lenerr : 1; /**< Frame was received with length error */
2781 uint64_t maxerr : 1; /**< Frame was received with length > max_length */
2782 uint64_t minerr : 1; /**< Frame was received with length < min_length */
2783 uint64_t beperr : 1; /**< Parity Error in back end memory */
2784 uint64_t feperr : 1; /**< Parity Error in front end memory */
2785 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
2786 uint64_t skprunt : 1; /**< Packet was engulfed by skipper
2787 This interrupt can occur with received PARTIAL
2788 packets that are truncated to SKIP bytes or
2789 smaller. */
2790 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2791 uint64_t prtnxa : 1; /**< Non-existent port */
2792 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2793 uint64_t crcerr : 1; /**< PIP calculated bad CRC
2794 (Disabled in 56xx) */
2795 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2796 #else
2797 uint64_t pktdrp : 1;
2798 uint64_t crcerr : 1;
2799 uint64_t bckprs : 1;
2800 uint64_t prtnxa : 1;
2801 uint64_t badtag : 1;
2802 uint64_t skprunt : 1;
2803 uint64_t todoovr : 1;
2804 uint64_t feperr : 1;
2805 uint64_t beperr : 1;
2806 uint64_t minerr : 1;
2807 uint64_t maxerr : 1;
2808 uint64_t lenerr : 1;
2809 uint64_t reserved_12_63 : 52;
2810 #endif
2811 } cn56xxp1;
2812 struct cvmx_pip_int_reg_cn58xx {
2813 #ifdef __BIG_ENDIAN_BITFIELD
2814 uint64_t reserved_13_63 : 51;
2815 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC
2816 stripping in IPD is enable */
2817 uint64_t reserved_9_11 : 3;
2818 uint64_t beperr : 1; /**< Parity Error in back end memory */
2819 uint64_t feperr : 1; /**< Parity Error in front end memory */
2820 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
2821 uint64_t skprunt : 1; /**< Packet was engulfed by skipper
2822 This interrupt can occur with received PARTIAL
2823 packets that are truncated to SKIP bytes or
2824 smaller. */
2825 uint64_t badtag : 1; /**< A bad tag was sent from IPD */
2826 uint64_t prtnxa : 1; /**< Non-existent port */
2827 uint64_t bckprs : 1; /**< PIP asserted backpressure */
2828 uint64_t crcerr : 1; /**< PIP calculated bad CRC */
2829 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */
2830 #else
2831 uint64_t pktdrp : 1;
2832 uint64_t crcerr : 1;
2833 uint64_t bckprs : 1;
2834 uint64_t prtnxa : 1;
2835 uint64_t badtag : 1;
2836 uint64_t skprunt : 1;
2837 uint64_t todoovr : 1;
2838 uint64_t feperr : 1;
2839 uint64_t beperr : 1;
2840 uint64_t reserved_9_11 : 3;
2841 uint64_t punyerr : 1;
2842 uint64_t reserved_13_63 : 51;
2843 #endif
2844 } cn58xx;
2845 struct cvmx_pip_int_reg_cn30xx cn58xxp1;
2846 struct cvmx_pip_int_reg_s cn61xx;
2847 struct cvmx_pip_int_reg_s cn63xx;
2848 struct cvmx_pip_int_reg_s cn63xxp1;
2849 struct cvmx_pip_int_reg_s cn66xx;
2850 struct cvmx_pip_int_reg_s cn68xx;
2851 struct cvmx_pip_int_reg_s cn68xxp1;
2852 struct cvmx_pip_int_reg_s cnf71xx;
2853 };
2854 typedef union cvmx_pip_int_reg cvmx_pip_int_reg_t;
2855
2856 /**
2857 * cvmx_pip_ip_offset
2858 *
2859 * PIP_IP_OFFSET = Location of the IP in the workQ entry
2860 *
2861 * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires
2862 *
2863 * Notes:
2864 * In normal configurations, OFFSET must be set in the 0..4 range to allow the
2865 * entire IP and TCP/UDP headers to be buffered in HW and calculate the L4
2866 * checksum for TCP/UDP packets.
2867 *
2868 * The MAX value of OFFSET is determined by the the types of packets that can
2869 * be sent to PIP as follows...
2870 *
2871 * Packet Type MAX OFFSET
2872 * IPv4/TCP/UDP 7
2873 * IPv6/TCP/UDP 5
2874 * IPv6/without L4 parsing 6
2875 *
2876 * If the L4 can be ignored, then the MAX OFFSET for IPv6 packets can increase
2877 * to 6. Here are the following programming restrictions for IPv6 packets and
2878 * OFFSET==6:
2879 *
2880 * . PIP_GBL_CTL[TCP_FLAG] == 0
2881 * . PIP_GBL_CTL[L4_LEN] == 0
2882 * . PIP_GBL_CTL[L4_CHK] == 0
2883 * . PIP_GBL_CTL[L4_PRT] == 0
2884 * . PIP_GBL_CTL[L4_MAL] == 0
2885 * . PIP_DEC_IPSEC[TCP] == 0
2886 * . PIP_DEC_IPSEC[UDP] == 0
2887 * . PIP_PRT_TAG[IP6_DPRT] == 0
2888 * . PIP_PRT_TAG[IP6_SPRT] == 0
2889 * . PIP_PRT_TAG[TCP6_TAG] == 0
2890 * . PIP_GBL_CFG[TAG_SYN] == 0
2891 */
2892 union cvmx_pip_ip_offset {
2893 uint64_t u64;
2894 struct cvmx_pip_ip_offset_s {
2895 #ifdef __BIG_ENDIAN_BITFIELD
2896 uint64_t reserved_3_63 : 61;
2897 uint64_t offset : 3; /**< Number of 8B ticks to include in workQ entry
2898 prior to IP data
2899 - 0: 0 Bytes / IP start at WORD4 of workQ entry
2900 - 1: 8 Bytes / IP start at WORD5 of workQ entry
2901 - 2: 16 Bytes / IP start at WORD6 of workQ entry
2902 - 3: 24 Bytes / IP start at WORD7 of workQ entry
2903 - 4: 32 Bytes / IP start at WORD8 of workQ entry
2904 - 5: 40 Bytes / IP start at WORD9 of workQ entry
2905 - 6: 48 Bytes / IP start at WORD10 of workQ entry
2906 - 7: 56 Bytes / IP start at WORD11 of workQ entry */
2907 #else
2908 uint64_t offset : 3;
2909 uint64_t reserved_3_63 : 61;
2910 #endif
2911 } s;
2912 struct cvmx_pip_ip_offset_s cn30xx;
2913 struct cvmx_pip_ip_offset_s cn31xx;
2914 struct cvmx_pip_ip_offset_s cn38xx;
2915 struct cvmx_pip_ip_offset_s cn38xxp2;
2916 struct cvmx_pip_ip_offset_s cn50xx;
2917 struct cvmx_pip_ip_offset_s cn52xx;
2918 struct cvmx_pip_ip_offset_s cn52xxp1;
2919 struct cvmx_pip_ip_offset_s cn56xx;
2920 struct cvmx_pip_ip_offset_s cn56xxp1;
2921 struct cvmx_pip_ip_offset_s cn58xx;
2922 struct cvmx_pip_ip_offset_s cn58xxp1;
2923 struct cvmx_pip_ip_offset_s cn61xx;
2924 struct cvmx_pip_ip_offset_s cn63xx;
2925 struct cvmx_pip_ip_offset_s cn63xxp1;
2926 struct cvmx_pip_ip_offset_s cn66xx;
2927 struct cvmx_pip_ip_offset_s cn68xx;
2928 struct cvmx_pip_ip_offset_s cn68xxp1;
2929 struct cvmx_pip_ip_offset_s cnf71xx;
2930 };
2931 typedef union cvmx_pip_ip_offset cvmx_pip_ip_offset_t;
2932
2933 /**
2934 * cvmx_pip_pri_tbl#
2935 *
2936 * Notes:
2937 * The priority level from HiGig header is as follows
2938 *
2939 * HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]]
2940 * HiGig2 PRI = [DP[1:0], TC[3:0]]
2941 *
2942 * DSA PRI = WORD0[15:13]
2943 *
2944 * VLAN PRI = VLAN[15:13]
2945 *
2946 * DIFFSERV = IP.TOS/CLASS<7:2>
2947 */
2948 union cvmx_pip_pri_tblx {
2949 uint64_t u64;
2950 struct cvmx_pip_pri_tblx_s {
2951 #ifdef __BIG_ENDIAN_BITFIELD
2952 uint64_t diff2_padd : 8; /**< Diffserv port-add */
2953 uint64_t hg2_padd : 8; /**< HG_PRI port-add */
2954 uint64_t vlan2_padd : 8; /**< VLAN port-add */
2955 uint64_t reserved_38_39 : 2;
2956 uint64_t diff2_bpid : 6; /**< Diffserv backpressure ID */
2957 uint64_t reserved_30_31 : 2;
2958 uint64_t hg2_bpid : 6; /**< HG_PRI backpressure ID */
2959 uint64_t reserved_22_23 : 2;
2960 uint64_t vlan2_bpid : 6; /**< VLAN backpressure ID */
2961 uint64_t reserved_11_15 : 5;
2962 uint64_t diff2_qos : 3; /**< Diffserv QOS level */
2963 uint64_t reserved_7_7 : 1;
2964 uint64_t hg2_qos : 3; /**< HG_PRI QOS level */
2965 uint64_t reserved_3_3 : 1;
2966 uint64_t vlan2_qos : 3; /**< VLAN QOS level */
2967 #else
2968 uint64_t vlan2_qos : 3;
2969 uint64_t reserved_3_3 : 1;
2970 uint64_t hg2_qos : 3;
2971 uint64_t reserved_7_7 : 1;
2972 uint64_t diff2_qos : 3;
2973 uint64_t reserved_11_15 : 5;
2974 uint64_t vlan2_bpid : 6;
2975 uint64_t reserved_22_23 : 2;
2976 uint64_t hg2_bpid : 6;
2977 uint64_t reserved_30_31 : 2;
2978 uint64_t diff2_bpid : 6;
2979 uint64_t reserved_38_39 : 2;
2980 uint64_t vlan2_padd : 8;
2981 uint64_t hg2_padd : 8;
2982 uint64_t diff2_padd : 8;
2983 #endif
2984 } s;
2985 struct cvmx_pip_pri_tblx_s cn68xx;
2986 struct cvmx_pip_pri_tblx_s cn68xxp1;
2987 };
2988 typedef union cvmx_pip_pri_tblx cvmx_pip_pri_tblx_t;
2989
2990 /**
2991 * cvmx_pip_prt_cfg#
2992 *
2993 * PIP_PRT_CFGX = Per port config information
2994 *
2995 */
2996 union cvmx_pip_prt_cfgx {
2997 uint64_t u64;
2998 struct cvmx_pip_prt_cfgx_s {
2999 #ifdef __BIG_ENDIAN_BITFIELD
3000 uint64_t reserved_55_63 : 9;
3001 uint64_t ih_pri : 1; /**< Use the PRI/QOS field in the instruction header
3002 as the PRIORITY in BPID calculations. */
3003 uint64_t len_chk_sel : 1; /**< Selects which PIP_FRM_LEN_CHK register is used
3004 for this port-kind for MINERR and MAXERR checks.
3005 LEN_CHK_SEL=0, use PIP_FRM_LEN_CHK0
3006 LEN_CHK_SEL=1, use PIP_FRM_LEN_CHK1 */
3007 uint64_t pad_len : 1; /**< When set, disables the length check for pkts with
3008 padding in the client data */
3009 uint64_t vlan_len : 1; /**< When set, disables the length check for DSA/VLAN
3010 pkts */
3011 uint64_t lenerr_en : 1; /**< L2 length error check enable
3012 Frame was received with length error
3013 Typically, this check will not be enabled for
3014 incoming packets on the DPI and sRIO ports
3015 because the CRC bytes may not normally be
3016 present. */
3017 uint64_t maxerr_en : 1; /**< Max frame error check enable
3018 Frame was received with length > max_length
3019 max_length is defined by PIP_FRM_LEN_CHK[MAXLEN] */
3020 uint64_t minerr_en : 1; /**< Min frame error check enable
3021 Frame was received with length < min_length
3022 Typically, this check will not be enabled for
3023 incoming packets on the DPI and sRIO ports
3024 because the CRC bytes may not normally be
3025 present.
3026 min_length is defined by PIP_FRM_LEN_CHK[MINLEN] */
3027 uint64_t grp_wat_47 : 4; /**< GRP Watcher enable
3028 (Watchers 4-7) */
3029 uint64_t qos_wat_47 : 4; /**< QOS Watcher enable
3030 (Watchers 4-7) */
3031 uint64_t reserved_37_39 : 3;
3032 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet.
3033 Normally, IPD will never drop a packet that PIP
3034 indicates is RAW.
3035 0=never drop RAW packets based on RED algorithm
3036 1=allow RAW packet drops based on RED algorithm */
3037 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when
3038 calculating mask tag hash */
3039 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and
3040 configuration. If DYN_RS is set then
3041 PKT_INST_HDR[RS] is not used. When using 2-byte
3042 instruction header words, either DYN_RS or
3043 PIP_GBL_CTL[IGNRS] should be set. */
3044 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets
3045 Internally set for RAWFULL/RAWSCHED packets
3046 on the DPI ports (32-35).
3047 Internally cleared for all other packets on the
3048 DPI ports (32-35).
3049 Must be zero in DSA mode */
3050 uint64_t grp_wat : 4; /**< GRP Watcher enable */
3051 uint64_t hg_qos : 1; /**< When set, uses the HiGig priority bits as a
3052 lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
3053 to determine the QOS value
3054 HG_QOS must not be set when HIGIG_EN=0 */
3055 uint64_t qos : 3; /**< Default QOS level of the port */
3056 uint64_t qos_wat : 4; /**< QOS Watcher enable
3057 (Watchers 0-3) */
3058 uint64_t qos_vsel : 1; /**< Which QOS in PIP_QOS_VLAN to use
3059 0 = PIP_QOS_VLAN[QOS]
3060 1 = PIP_QOS_VLAN[QOS1] */
3061 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv
3062 if DSA/VLAN exists, it is used
3063 else if IP exists, Diffserv is used
3064 else the per port default is used
3065 Watchers are still highest priority */
3066 uint64_t qos_diff : 1; /**< QOS Diffserv */
3067 uint64_t qos_vlan : 1; /**< QOS VLAN */
3068 uint64_t reserved_13_15 : 3;
3069 uint64_t crc_en : 1; /**< CRC Checking enabled */
3070 uint64_t higig_en : 1; /**< Enable HiGig parsing
3071 Should not be set for DPI ports (ports 32-35)
3072 Should not be set for sRIO ports (ports 40-47)
3073 Should not be set for ports in which PTP_MODE=1
3074 When HIGIG_EN=1:
3075 DSA_EN field below must be zero
3076 PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
3077 SKIP field below is both Skip I size and the
3078 size of the HiGig* header (12 or 16 bytes) */
3079 uint64_t dsa_en : 1; /**< Enable DSA tag parsing
3080 Should not be set for sRIO (ports 40-47)
3081 Should not be set for ports in which PTP_MODE=1
3082 When DSA_EN=1:
3083 HIGIG_EN field above must be zero
3084 SKIP field below is size of DSA tag (4, 8, or
3085 12 bytes) rather than the size of Skip I
3086 total SKIP (Skip I + header + Skip II
3087 must be zero
3088 INST_HDR field above must be zero (non-DPI
3089 ports)
3090 PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
3091 For DPI ports, SLI_PKT*_INSTR_HEADER[USE_IHDR]
3092 and DPI_INST_HDR[R] should be clear
3093 MODE field below must be "skip to L2" */
3094 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode
3095 0 = no packet inspection (Uninterpreted)
3096 1 = L2 parsing / skip to L2
3097 2 = IP parsing / skip to L3
3098 3 = (illegal)
3099 Must be 2 ("skip to L2") when in DSA mode. */
3100 uint64_t reserved_7_7 : 1;
3101 uint64_t skip : 7; /**< Optional Skip I amount for packets.
3102 HW forces the SKIP to zero for packets on DPI
3103 ports (32-35) when a PKT_INST_HDR is present.
3104 See PIP_PRT_CFGB[ALT_SKP*] and PIP_ALT_SKIP_CFG.
3105 See HRM sections "Parse Mode and Skip Length
3106 Selection" and "Legal Skip Values"
3107 for further details.
3108 In DSA mode, indicates the DSA header length, not
3109 Skip I size. (Must be 4,8,or 12)
3110 In HIGIG mode, indicates both the Skip I size and
3111 the HiGig header size (Must be 12 or 16).
3112 If PTP_MODE, the 8B timestamp is prepended to the
3113 packet. SKIP should be increased by 8 to
3114 compensate for the additional timestamp field. */
3115 #else
3116 uint64_t skip : 7;
3117 uint64_t reserved_7_7 : 1;
3118 cvmx_pip_port_parse_mode_t mode : 2;
3119 uint64_t dsa_en : 1;
3120 uint64_t higig_en : 1;
3121 uint64_t crc_en : 1;
3122 uint64_t reserved_13_15 : 3;
3123 uint64_t qos_vlan : 1;
3124 uint64_t qos_diff : 1;
3125 uint64_t qos_vod : 1;
3126 uint64_t qos_vsel : 1;
3127 uint64_t qos_wat : 4;
3128 uint64_t qos : 3;
3129 uint64_t hg_qos : 1;
3130 uint64_t grp_wat : 4;
3131 uint64_t inst_hdr : 1;
3132 uint64_t dyn_rs : 1;
3133 uint64_t tag_inc : 2;
3134 uint64_t rawdrp : 1;
3135 uint64_t reserved_37_39 : 3;
3136 uint64_t qos_wat_47 : 4;
3137 uint64_t grp_wat_47 : 4;
3138 uint64_t minerr_en : 1;
3139 uint64_t maxerr_en : 1;
3140 uint64_t lenerr_en : 1;
3141 uint64_t vlan_len : 1;
3142 uint64_t pad_len : 1;
3143 uint64_t len_chk_sel : 1;
3144 uint64_t ih_pri : 1;
3145 uint64_t reserved_55_63 : 9;
3146 #endif
3147 } s;
3148 struct cvmx_pip_prt_cfgx_cn30xx {
3149 #ifdef __BIG_ENDIAN_BITFIELD
3150 uint64_t reserved_37_63 : 27;
3151 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet.
3152 Normally, IPD will never drop a packet that PIP
3153 indicates is RAW.
3154 0=never drop RAW packets based on RED algorithm
3155 1=allow RAW packet drops based on RED algorithm */
3156 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when
3157 calculating mask tag hash */
3158 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and
3159 configuration. If DYN_RS is set then
3160 PKT_INST_HDR[RS] is not used. When using 2-byte
3161 instruction header words, either DYN_RS or
3162 PIP_GBL_CTL[IGNRS] should be set. */
3163 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets
3164 (not for PCI prts, 32-35) */
3165 uint64_t grp_wat : 4; /**< GRP Watcher enable */
3166 uint64_t reserved_27_27 : 1;
3167 uint64_t qos : 3; /**< Default QOS level of the port */
3168 uint64_t qos_wat : 4; /**< QOS Watcher enable */
3169 uint64_t reserved_18_19 : 2;
3170 uint64_t qos_diff : 1; /**< QOS Diffserv */
3171 uint64_t qos_vlan : 1; /**< QOS VLAN */
3172 uint64_t reserved_10_15 : 6;
3173 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode
3174 0 = no packet inspection (Uninterpreted)
3175 1 = L2 parsing / skip to L2
3176 2 = IP parsing / skip to L3
3177 3 = PCI Raw (illegal for software to set) */
3178 uint64_t reserved_7_7 : 1;
3179 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not
3180 apply to packets on PCI ports when a PKT_INST_HDR
3181 is present. See section 7.2.7 - Legal Skip
3182 Values for further details. */
3183 #else
3184 uint64_t skip : 7;
3185 uint64_t reserved_7_7 : 1;
3186 cvmx_pip_port_parse_mode_t mode : 2;
3187 uint64_t reserved_10_15 : 6;
3188 uint64_t qos_vlan : 1;
3189 uint64_t qos_diff : 1;
3190 uint64_t reserved_18_19 : 2;
3191 uint64_t qos_wat : 4;
3192 uint64_t qos : 3;
3193 uint64_t reserved_27_27 : 1;
3194 uint64_t grp_wat : 4;
3195 uint64_t inst_hdr : 1;
3196 uint64_t dyn_rs : 1;
3197 uint64_t tag_inc : 2;
3198 uint64_t rawdrp : 1;
3199 uint64_t reserved_37_63 : 27;
3200 #endif
3201 } cn30xx;
3202 struct cvmx_pip_prt_cfgx_cn30xx cn31xx;
3203 struct cvmx_pip_prt_cfgx_cn38xx {
3204 #ifdef __BIG_ENDIAN_BITFIELD
3205 uint64_t reserved_37_63 : 27;
3206 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet.
3207 Normally, IPD will never drop a packet that PIP
3208 indicates is RAW.
3209 0=never drop RAW packets based on RED algorithm
3210 1=allow RAW packet drops based on RED algorithm */
3211 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when
3212 calculating mask tag hash */
3213 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and
3214 configuration. If DYN_RS is set then
3215 PKT_INST_HDR[RS] is not used. When using 2-byte
3216 instruction header words, either DYN_RS or
3217 PIP_GBL_CTL[IGNRS] should be set. */
3218 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets
3219 (not for PCI prts, 32-35) */
3220 uint64_t grp_wat : 4; /**< GRP Watcher enable */
3221 uint64_t reserved_27_27 : 1;
3222 uint64_t qos : 3; /**< Default QOS level of the port */
3223 uint64_t qos_wat : 4; /**< QOS Watcher enable */
3224 uint64_t reserved_18_19 : 2;
3225 uint64_t qos_diff : 1; /**< QOS Diffserv */
3226 uint64_t qos_vlan : 1; /**< QOS VLAN */
3227 uint64_t reserved_13_15 : 3;
3228 uint64_t crc_en : 1; /**< CRC Checking enabled (for ports 0-31 only) */
3229 uint64_t reserved_10_11 : 2;
3230 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode
3231 0 = no packet inspection (Uninterpreted)
3232 1 = L2 parsing / skip to L2
3233 2 = IP parsing / skip to L3
3234 3 = PCI Raw (illegal for software to set) */
3235 uint64_t reserved_7_7 : 1;
3236 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not
3237 apply to packets on PCI ports when a PKT_INST_HDR
3238 is present. See section 7.2.7 - Legal Skip
3239 Values for further details. */
3240 #else
3241 uint64_t skip : 7;
3242 uint64_t reserved_7_7 : 1;
3243 cvmx_pip_port_parse_mode_t mode : 2;
3244 uint64_t reserved_10_11 : 2;
3245 uint64_t crc_en : 1;
3246 uint64_t reserved_13_15 : 3;
3247 uint64_t qos_vlan : 1;
3248 uint64_t qos_diff : 1;
3249 uint64_t reserved_18_19 : 2;
3250 uint64_t qos_wat : 4;
3251 uint64_t qos : 3;
3252 uint64_t reserved_27_27 : 1;
3253 uint64_t grp_wat : 4;
3254 uint64_t inst_hdr : 1;
3255 uint64_t dyn_rs : 1;
3256 uint64_t tag_inc : 2;
3257 uint64_t rawdrp : 1;
3258 uint64_t reserved_37_63 : 27;
3259 #endif
3260 } cn38xx;
3261 struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;
3262 struct cvmx_pip_prt_cfgx_cn50xx {
3263 #ifdef __BIG_ENDIAN_BITFIELD
3264 uint64_t reserved_53_63 : 11;
3265 uint64_t pad_len : 1; /**< When set, disables the length check for pkts with
3266 padding in the client data */
3267 uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */
3268 uint64_t lenerr_en : 1; /**< L2 length error check enable
3269 Frame was received with length error */
3270 uint64_t maxerr_en : 1; /**< Max frame error check enable
3271 Frame was received with length > max_length */
3272 uint64_t minerr_en : 1; /**< Min frame error check enable
3273 Frame was received with length < min_length */
3274 uint64_t grp_wat_47 : 4; /**< GRP Watcher enable
3275 (Watchers 4-7) */
3276 uint64_t qos_wat_47 : 4; /**< QOS Watcher enable
3277 (Watchers 4-7) */
3278 uint64_t reserved_37_39 : 3;
3279 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet.
3280 Normally, IPD will never drop a packet that PIP
3281 indicates is RAW.
3282 0=never drop RAW packets based on RED algorithm
3283 1=allow RAW packet drops based on RED algorithm */
3284 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when
3285 calculating mask tag hash */
3286 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and
3287 configuration. If DYN_RS is set then
3288 PKT_INST_HDR[RS] is not used. When using 2-byte
3289 instruction header words, either DYN_RS or
3290 PIP_GBL_CTL[IGNRS] should be set. */
3291 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets
3292 (not for PCI prts, 32-35) */
3293 uint64_t grp_wat : 4; /**< GRP Watcher enable */
3294 uint64_t reserved_27_27 : 1;
3295 uint64_t qos : 3; /**< Default QOS level of the port */
3296 uint64_t qos_wat : 4; /**< QOS Watcher enable
3297 (Watchers 0-3) */
3298 uint64_t reserved_19_19 : 1;
3299 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv
3300 if VLAN exists, it is used
3301 else if IP exists, Diffserv is used
3302 else the per port default is used
3303 Watchers are still highest priority */
3304 uint64_t qos_diff : 1; /**< QOS Diffserv */
3305 uint64_t qos_vlan : 1; /**< QOS VLAN */
3306 uint64_t reserved_13_15 : 3;
3307 uint64_t crc_en : 1; /**< CRC Checking enabled
3308 (Disabled in 5020) */
3309 uint64_t reserved_10_11 : 2;
3310 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode
3311 0 = no packet inspection (Uninterpreted)
3312 1 = L2 parsing / skip to L2
3313 2 = IP parsing / skip to L3
3314 3 = PCI Raw (illegal for software to set) */
3315 uint64_t reserved_7_7 : 1;
3316 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not
3317 apply to packets on PCI ports when a PKT_INST_HDR
3318 is present. See section 7.2.7 - Legal Skip
3319 Values for further details. */
3320 #else
3321 uint64_t skip : 7;
3322 uint64_t reserved_7_7 : 1;
3323 cvmx_pip_port_parse_mode_t mode : 2;
3324 uint64_t reserved_10_11 : 2;
3325 uint64_t crc_en : 1;
3326 uint64_t reserved_13_15 : 3;
3327 uint64_t qos_vlan : 1;
3328 uint64_t qos_diff : 1;
3329 uint64_t qos_vod : 1;
3330 uint64_t reserved_19_19 : 1;
3331 uint64_t qos_wat : 4;
3332 uint64_t qos : 3;
3333 uint64_t reserved_27_27 : 1;
3334 uint64_t grp_wat : 4;
3335 uint64_t inst_hdr : 1;
3336 uint64_t dyn_rs : 1;
3337 uint64_t tag_inc : 2;
3338 uint64_t rawdrp : 1;
3339 uint64_t reserved_37_39 : 3;
3340 uint64_t qos_wat_47 : 4;
3341 uint64_t grp_wat_47 : 4;
3342 uint64_t minerr_en : 1;
3343 uint64_t maxerr_en : 1;
3344 uint64_t lenerr_en : 1;
3345 uint64_t vlan_len : 1;
3346 uint64_t pad_len : 1;
3347 uint64_t reserved_53_63 : 11;
3348 #endif
3349 } cn50xx;
3350 struct cvmx_pip_prt_cfgx_cn52xx {
3351 #ifdef __BIG_ENDIAN_BITFIELD
3352 uint64_t reserved_53_63 : 11;
3353 uint64_t pad_len : 1; /**< When set, disables the length check for pkts with
3354 padding in the client data */
3355 uint64_t vlan_len : 1; /**< When set, disables the length check for DSA/VLAN
3356 pkts */
3357 uint64_t lenerr_en : 1; /**< L2 length error check enable
3358 Frame was received with length error
3359 Typically, this check will not be enabled for
3360 incoming packets on the PCIe ports. */
3361 uint64_t maxerr_en : 1; /**< Max frame error check enable
3362 Frame was received with length > max_length */
3363 uint64_t minerr_en : 1; /**< Min frame error check enable
3364 Frame was received with length < min_length
3365 Typically, this check will not be enabled for
3366 incoming packets on the PCIe ports. */
3367 uint64_t grp_wat_47 : 4; /**< GRP Watcher enable
3368 (Watchers 4-7) */
3369 uint64_t qos_wat_47 : 4; /**< QOS Watcher enable
3370 (Watchers 4-7) */
3371 uint64_t reserved_37_39 : 3;
3372 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet.
3373 Normally, IPD will never drop a packet that PIP
3374 indicates is RAW.
3375 0=never drop RAW packets based on RED algorithm
3376 1=allow RAW packet drops based on RED algorithm */
3377 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when
3378 calculating mask tag hash */
3379 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and
3380 configuration. If DYN_RS is set then
3381 PKT_INST_HDR[RS] is not used. When using 2-byte
3382 instruction header words, either DYN_RS or
3383 PIP_GBL_CTL[IGNRS] should be set. */
3384 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets
3385 (not for PCI ports, 32-35)
3386 Must be zero in DSA mode */
3387 uint64_t grp_wat : 4; /**< GRP Watcher enable */
3388 uint64_t hg_qos : 1; /**< When set, uses the HiGig priority bits as a
3389 lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
3390 to determine the QOS value
3391 HG_QOS must not be set when HIGIG_EN=0 */
3392 uint64_t qos : 3; /**< Default QOS level of the port */
3393 uint64_t qos_wat : 4; /**< QOS Watcher enable
3394 (Watchers 0-3) */
3395 uint64_t qos_vsel : 1; /**< Which QOS in PIP_QOS_VLAN to use
3396 0 = PIP_QOS_VLAN[QOS]
3397 1 = PIP_QOS_VLAN[QOS1] */
3398 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv
3399 if DSA/VLAN exists, it is used
3400 else if IP exists, Diffserv is used
3401 else the per port default is used
3402 Watchers are still highest priority */
3403 uint64_t qos_diff : 1; /**< QOS Diffserv */
3404 uint64_t qos_vlan : 1; /**< QOS VLAN */
3405 uint64_t reserved_13_15 : 3;
3406 uint64_t crc_en : 1; /**< CRC Checking enabled
3407 (Disabled in 52xx) */
3408 uint64_t higig_en : 1; /**< Enable HiGig parsing
3409 When HIGIG_EN=1:
3410 DSA_EN field below must be zero
3411 SKIP field below is both Skip I size and the
3412 size of the HiGig* header (12 or 16 bytes) */
3413 uint64_t dsa_en : 1; /**< Enable DSA tag parsing
3414 When DSA_EN=1:
3415 HIGIG_EN field above must be zero
3416 SKIP field below is size of DSA tag (4, 8, or
3417 12 bytes) rather than the size of Skip I
3418 total SKIP (Skip I + header + Skip II
3419 must be zero
3420 INST_HDR field above must be zero
3421 MODE field below must be "skip to L2" */
3422 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode
3423 0 = no packet inspection (Uninterpreted)
3424 1 = L2 parsing / skip to L2
3425 2 = IP parsing / skip to L3
3426 3 = (illegal)
3427 Must be 2 ("skip to L2") when in DSA mode. */
3428 uint64_t reserved_7_7 : 1;
3429 uint64_t skip : 7; /**< Optional Skip I amount for packets.
3430 See section 7.2.7 - Legal Skip
3431 Values for further details.
3432 In DSA mode, indicates the DSA header length, not
3433 Skip I size. (Must be 4,8,or 12)
3434 In HIGIG mode, indicates both the Skip I size and
3435 the HiGig header size (Must be 12 or 16). */
3436 #else
3437 uint64_t skip : 7;
3438 uint64_t reserved_7_7 : 1;
3439 cvmx_pip_port_parse_mode_t mode : 2;
3440 uint64_t dsa_en : 1;
3441 uint64_t higig_en : 1;
3442 uint64_t crc_en : 1;
3443 uint64_t reserved_13_15 : 3;
3444 uint64_t qos_vlan : 1;
3445 uint64_t qos_diff : 1;
3446 uint64_t qos_vod : 1;
3447 uint64_t qos_vsel : 1;
3448 uint64_t qos_wat : 4;
3449 uint64_t qos : 3;
3450 uint64_t hg_qos : 1;
3451 uint64_t grp_wat : 4;
3452 uint64_t inst_hdr : 1;
3453 uint64_t dyn_rs : 1;
3454 uint64_t tag_inc : 2;
3455 uint64_t rawdrp : 1;
3456 uint64_t reserved_37_39 : 3;
3457 uint64_t qos_wat_47 : 4;
3458 uint64_t grp_wat_47 : 4;
3459 uint64_t minerr_en : 1;
3460 uint64_t maxerr_en : 1;
3461 uint64_t lenerr_en : 1;
3462 uint64_t vlan_len : 1;
3463 uint64_t pad_len : 1;
3464 uint64_t reserved_53_63 : 11;
3465 #endif
3466 } cn52xx;
3467 struct cvmx_pip_prt_cfgx_cn52xx cn52xxp1;
3468 struct cvmx_pip_prt_cfgx_cn52xx cn56xx;
3469 struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;
3470 struct cvmx_pip_prt_cfgx_cn58xx {
3471 #ifdef __BIG_ENDIAN_BITFIELD
3472 uint64_t reserved_37_63 : 27;
3473 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet.
3474 Normally, IPD will never drop a packet that PIP
3475 indicates is RAW.
3476 0=never drop RAW packets based on RED algorithm
3477 1=allow RAW packet drops based on RED algorithm */
3478 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when
3479 calculating mask tag hash */
3480 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and
3481 configuration. If DYN_RS is set then
3482 PKT_INST_HDR[RS] is not used. When using 2-byte
3483 instruction header words, either DYN_RS or
3484 PIP_GBL_CTL[IGNRS] should be set. */
3485 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets
3486 (not for PCI prts, 32-35) */
3487 uint64_t grp_wat : 4; /**< GRP Watcher enable */
3488 uint64_t reserved_27_27 : 1;
3489 uint64_t qos : 3; /**< Default QOS level of the port */
3490 uint64_t qos_wat : 4; /**< QOS Watcher enable */
3491 uint64_t reserved_19_19 : 1;
3492 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv
3493 if VLAN exists, it is used
3494 else if IP exists, Diffserv is used
3495 else the per port default is used
3496 Watchers are still highest priority */
3497 uint64_t qos_diff : 1; /**< QOS Diffserv */
3498 uint64_t qos_vlan : 1; /**< QOS VLAN */
3499 uint64_t reserved_13_15 : 3;
3500 uint64_t crc_en : 1; /**< CRC Checking enabled (for ports 0-31 only) */
3501 uint64_t reserved_10_11 : 2;
3502 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode
3503 0 = no packet inspection (Uninterpreted)
3504 1 = L2 parsing / skip to L2
3505 2 = IP parsing / skip to L3
3506 3 = PCI Raw (illegal for software to set) */
3507 uint64_t reserved_7_7 : 1;
3508 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not
3509 apply to packets on PCI ports when a PKT_INST_HDR
3510 is present. See section 7.2.7 - Legal Skip
3511 Values for further details. */
3512 #else
3513 uint64_t skip : 7;
3514 uint64_t reserved_7_7 : 1;
3515 cvmx_pip_port_parse_mode_t mode : 2;
3516 uint64_t reserved_10_11 : 2;
3517 uint64_t crc_en : 1;
3518 uint64_t reserved_13_15 : 3;
3519 uint64_t qos_vlan : 1;
3520 uint64_t qos_diff : 1;
3521 uint64_t qos_vod : 1;
3522 uint64_t reserved_19_19 : 1;
3523 uint64_t qos_wat : 4;
3524 uint64_t qos : 3;
3525 uint64_t reserved_27_27 : 1;
3526 uint64_t grp_wat : 4;
3527 uint64_t inst_hdr : 1;
3528 uint64_t dyn_rs : 1;
3529 uint64_t tag_inc : 2;
3530 uint64_t rawdrp : 1;
3531 uint64_t reserved_37_63 : 27;
3532 #endif
3533 } cn58xx;
3534 struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;
3535 struct cvmx_pip_prt_cfgx_cn52xx cn61xx;
3536 struct cvmx_pip_prt_cfgx_cn52xx cn63xx;
3537 struct cvmx_pip_prt_cfgx_cn52xx cn63xxp1;
3538 struct cvmx_pip_prt_cfgx_cn52xx cn66xx;
3539 struct cvmx_pip_prt_cfgx_cn68xx {
3540 #ifdef __BIG_ENDIAN_BITFIELD
3541 uint64_t reserved_55_63 : 9;
3542 uint64_t ih_pri : 1; /**< Use the PRI/QOS field in the instruction header
3543 as the PRIORITY in BPID calculations. */
3544 uint64_t len_chk_sel : 1; /**< Selects which PIP_FRM_LEN_CHK register is used
3545 for this port-kind for MINERR and MAXERR checks.
3546 LEN_CHK_SEL=0, use PIP_FRM_LEN_CHK0
3547 LEN_CHK_SEL=1, use PIP_FRM_LEN_CHK1 */
3548 uint64_t pad_len : 1; /**< When set, disables the length check for pkts with
3549 padding in the client data */
3550 uint64_t vlan_len : 1; /**< When set, disables the length check for DSA/VLAN
3551 pkts */
3552 uint64_t lenerr_en : 1; /**< L2 length error check enable
3553 Frame was received with length error
3554 Typically, this check will not be enabled for
3555 incoming packets on the DPI rings
3556 because the CRC bytes may not normally be
3557 present. */
3558 uint64_t maxerr_en : 1; /**< Max frame error check enable
3559 Frame was received with length > max_length
3560 max_length is defined by PIP_FRM_LEN_CHK[MAXLEN] */
3561 uint64_t minerr_en : 1; /**< Min frame error check enable
3562 Frame was received with length < min_length
3563 Typically, this check will not be enabled for
3564 incoming packets on the DPI rings
3565 because the CRC bytes may not normally be
3566 present.
3567 min_length is defined by PIP_FRM_LEN_CHK[MINLEN] */
3568 uint64_t grp_wat_47 : 4; /**< GRP Watcher enable
3569 (Watchers 4-7) */
3570 uint64_t qos_wat_47 : 4; /**< QOS Watcher enable
3571 (Watchers 4-7) */
3572 uint64_t reserved_37_39 : 3;
3573 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet.
3574 Normally, IPD will never drop a packet in which
3575 PKT_INST_HDR[R] is set.
3576 0=never drop RAW packets based on RED algorithm
3577 1=allow RAW packet drops based on RED algorithm */
3578 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when
3579 calculating mask tag hash */
3580 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and
3581 configuration. If DYN_RS is set then
3582 PKT_INST_HDR[RS] is not used. When using 2-byte
3583 instruction header words, either DYN_RS or
3584 PIP_GBL_CTL[IGNRS] should be set. */
3585 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets
3586 Normally INST_HDR should be set for packets that
3587 include a PKT_INST_HDR prepended by DPI hardware.
3588 (If SLI_PORTx_PKIND[RPK_ENB]=0, for packets that
3589 include a PKT_INST_HDR prepended by DPI,
3590 PIP internally sets INST_HDR before using it.)
3591 Must be zero in DSA mode */
3592 uint64_t grp_wat : 4; /**< GRP Watcher enable */
3593 uint64_t hg_qos : 1; /**< When set, uses the HiGig priority bits as a
3594 lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
3595 to determine the QOS value
3596 HG_QOS must not be set when HIGIG_EN=0 */
3597 uint64_t qos : 3; /**< Default QOS level of the port */
3598 uint64_t qos_wat : 4; /**< QOS Watcher enable
3599 (Watchers 0-3) */
3600 uint64_t reserved_19_19 : 1;
3601 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv
3602 if DSA/VLAN exists, it is used
3603 else if IP exists, Diffserv is used
3604 else the per port default is used
3605 Watchers are still highest priority */
3606 uint64_t qos_diff : 1; /**< QOS Diffserv */
3607 uint64_t qos_vlan : 1; /**< QOS VLAN */
3608 uint64_t reserved_13_15 : 3;
3609 uint64_t crc_en : 1; /**< CRC Checking enabled */
3610 uint64_t higig_en : 1; /**< Enable HiGig parsing
3611 Normally HIGIG_EN should be clear for packets that
3612 include a PKT_INST_HDR prepended by DPI hardware.
3613 (If SLI_PORTx_PKIND[RPK_ENB]=0, for packets that
3614 include a PKT_INST_HDR prepended by DPI,
3615 PIP internally clears HIGIG_EN before using it.)
3616 Should not be set for ports in which PTP_MODE=1
3617 When HIGIG_EN=1:
3618 DSA_EN field below must be zero
3619 PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
3620 SKIP field below is both Skip I size and the
3621 size of the HiGig* header (12 or 16 bytes) */
3622 uint64_t dsa_en : 1; /**< Enable DSA tag parsing
3623 Should not be set for ports in which PTP_MODE=1
3624 When DSA_EN=1:
3625 HIGIG_EN field above must be zero
3626 SKIP field below is size of DSA tag (4, 8, or
3627 12 bytes) rather than the size of Skip I
3628 total SKIP (Skip I + header + Skip II
3629 must be zero
3630 INST_HDR field above must be zero
3631 PIP_PRT_CFGB[ALT_SKP_EN] must be zero.
3632 For DPI rings, DPI hardware must not prepend
3633 a PKT_INST_HDR when DSA_EN=1.
3634 MODE field below must be "skip to L2" */
3635 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode
3636 0 = no packet inspection (Uninterpreted)
3637 1 = L2 parsing / skip to L2
3638 2 = IP parsing / skip to L3
3639 3 = (illegal)
3640 Must be 2 ("skip to L2") when in DSA mode. */
3641 uint64_t reserved_7_7 : 1;
3642 uint64_t skip : 7; /**< Optional Skip I amount for packets.
3643 Should normally be zero for packets on
3644 DPI rings when a PKT_INST_HDR is prepended by DPI
3645 hardware.
3646 See PIP_PRT_CFGB[ALT_SKP*] and PIP_ALT_SKIP_CFG.
3647 See HRM sections "Parse Mode and Skip Length
3648 Selection" and "Legal Skip Values"
3649 for further details.
3650 In DSA mode, indicates the DSA header length, not
3651 Skip I size. (Must be 4,8,or 12)
3652 In HIGIG mode, indicates both the Skip I size and
3653 the HiGig header size (Must be 12 or 16).
3654 If PTP_MODE, the 8B timestamp is prepended to the
3655 packet. SKIP should be increased by 8 to
3656 compensate for the additional timestamp field. */
3657 #else
3658 uint64_t skip : 7;
3659 uint64_t reserved_7_7 : 1;
3660 cvmx_pip_port_parse_mode_t mode : 2;
3661 uint64_t dsa_en : 1;
3662 uint64_t higig_en : 1;
3663 uint64_t crc_en : 1;
3664 uint64_t reserved_13_15 : 3;
3665 uint64_t qos_vlan : 1;
3666 uint64_t qos_diff : 1;
3667 uint64_t qos_vod : 1;
3668 uint64_t reserved_19_19 : 1;
3669 uint64_t qos_wat : 4;
3670 uint64_t qos : 3;
3671 uint64_t hg_qos : 1;
3672 uint64_t grp_wat : 4;
3673 uint64_t inst_hdr : 1;
3674 uint64_t dyn_rs : 1;
3675 uint64_t tag_inc : 2;
3676 uint64_t rawdrp : 1;
3677 uint64_t reserved_37_39 : 3;
3678 uint64_t qos_wat_47 : 4;
3679 uint64_t grp_wat_47 : 4;
3680 uint64_t minerr_en : 1;
3681 uint64_t maxerr_en : 1;
3682 uint64_t lenerr_en : 1;
3683 uint64_t vlan_len : 1;
3684 uint64_t pad_len : 1;
3685 uint64_t len_chk_sel : 1;
3686 uint64_t ih_pri : 1;
3687 uint64_t reserved_55_63 : 9;
3688 #endif
3689 } cn68xx;
3690 struct cvmx_pip_prt_cfgx_cn68xx cn68xxp1;
3691 struct cvmx_pip_prt_cfgx_cn52xx cnf71xx;
3692 };
3693 typedef union cvmx_pip_prt_cfgx cvmx_pip_prt_cfgx_t;
3694
3695 /**
3696 * cvmx_pip_prt_cfgb#
3697 *
3698 * Notes:
3699 * PIP_PRT_CFGB* does not exist prior to pass 1.2.
3700 *
3701 */
3702 union cvmx_pip_prt_cfgbx {
3703 uint64_t u64;
3704 struct cvmx_pip_prt_cfgbx_s {
3705 #ifdef __BIG_ENDIAN_BITFIELD
3706 uint64_t reserved_39_63 : 25;
3707 uint64_t alt_skp_sel : 2; /**< Alternate skip selector
3708 When enabled (ALT_SKP_EN), selects which of the
3709 four PIP_ALT_SKIP_CFGx to use with the packets
3710 arriving on the port-kind. */
3711 uint64_t alt_skp_en : 1; /**< Enable the alternate skip selector
3712 When enabled, the HW is able to recompute the
3713 SKIP I value based on the packet contents.
3714 Up to two of the initial 64 bits of the header
3715 are used along with four PIP_ALT_SKIP_CFGx to
3716 determine the updated SKIP I value.
3717 The bits of the packet used should be present in
3718 all packets.
3719 PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled
3720 when ALT_SKP_EN is set.
3721 ALT_SKP_EN must not be set for DPI ports (32-35)
3722 when a PKT_INST_HDR is present.
3723 ALT_SKP_EN should not be enabled for ports which
3724 have GMX_RX_FRM_CTL[PTP_MODE] set as the timestamp
3725 will be prepended onto the initial 64 bits of the
3726 packet. */
3727 uint64_t reserved_35_35 : 1;
3728 uint64_t bsel_num : 2; /**< Which of the 4 bit select extractors to use
3729 (Alias to PIP_PRT_CFG) */
3730 uint64_t bsel_en : 1; /**< Enable to turn on/off use of bit select extractor
3731 (Alias to PIP_PRT_CFG) */
3732 uint64_t reserved_24_31 : 8;
3733 uint64_t base : 8; /**< Base priority address into the table */
3734 uint64_t reserved_6_15 : 10;
3735 uint64_t bpid : 6; /**< Default BPID to use for packets on this port-kind. */
3736 #else
3737 uint64_t bpid : 6;
3738 uint64_t reserved_6_15 : 10;
3739 uint64_t base : 8;
3740 uint64_t reserved_24_31 : 8;
3741 uint64_t bsel_en : 1;
3742 uint64_t bsel_num : 2;
3743 uint64_t reserved_35_35 : 1;
3744 uint64_t alt_skp_en : 1;
3745 uint64_t alt_skp_sel : 2;
3746 uint64_t reserved_39_63 : 25;
3747 #endif
3748 } s;
3749 struct cvmx_pip_prt_cfgbx_cn61xx {
3750 #ifdef __BIG_ENDIAN_BITFIELD
3751 uint64_t reserved_39_63 : 25;
3752 uint64_t alt_skp_sel : 2; /**< Alternate skip selector
3753 When enabled (ALT_SKP_EN), selects which of the
3754 four PIP_ALT_SKIP_CFGx to use with the packets
3755 arriving on the port-kind. */
3756 uint64_t alt_skp_en : 1; /**< Enable the alternate skip selector
3757 When enabled, the HW is able to recompute the
3758 SKIP I value based on the packet contents.
3759 Up to two of the initial 64 bits of the header
3760 are used along with four PIP_ALT_SKIP_CFGx to
3761 determine the updated SKIP I value.
3762 The bits of the packet used should be present in
3763 all packets.
3764 PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled
3765 when ALT_SKP_EN is set.
3766 ALT_SKP_EN must not be set for DPI ports (32-35)
3767 when a PKT_INST_HDR is present.
3768 ALT_SKP_EN should not be enabled for ports which
3769 have GMX_RX_FRM_CTL[PTP_MODE] set as the timestamp
3770 will be prepended onto the initial 64 bits of the
3771 packet. */
3772 uint64_t reserved_35_35 : 1;
3773 uint64_t bsel_num : 2; /**< Which of the 4 bit select extractors to use
3774 (Alias to PIP_PRT_CFG) */
3775 uint64_t bsel_en : 1; /**< Enable to turn on/off use of bit select extractor
3776 (Alias to PIP_PRT_CFG) */
3777 uint64_t reserved_0_31 : 32;
3778 #else
3779 uint64_t reserved_0_31 : 32;
3780 uint64_t bsel_en : 1;
3781 uint64_t bsel_num : 2;
3782 uint64_t reserved_35_35 : 1;
3783 uint64_t alt_skp_en : 1;
3784 uint64_t alt_skp_sel : 2;
3785 uint64_t reserved_39_63 : 25;
3786 #endif
3787 } cn61xx;
3788 struct cvmx_pip_prt_cfgbx_cn66xx {
3789 #ifdef __BIG_ENDIAN_BITFIELD
3790 uint64_t reserved_39_63 : 25;
3791 uint64_t alt_skp_sel : 2; /**< Alternate skip selector
3792 When enabled (ALT_SKP_EN), selects which of the
3793 four PIP_ALT_SKIP_CFGx to use with the packets
3794 arriving on the port-kind. */
3795 uint64_t alt_skp_en : 1; /**< Enable the alternate skip selector
3796 When enabled, the HW is able to recompute the
3797 SKIP I value based on the packet contents.
3798 Up to two of the initial 64 bits of the header
3799 are used along with four PIP_ALT_SKIP_CFGx to
3800 determine the updated SKIP I value.
3801 The bits of the packet used should be present in
3802 all packets.
3803 PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled
3804 when ALT_SKP_EN is set.
3805 ALT_SKP_EN must not be set for DPI ports (32-35)
3806 when a PKT_INST_HDR is present. */
3807 uint64_t reserved_0_35 : 36;
3808 #else
3809 uint64_t reserved_0_35 : 36;
3810 uint64_t alt_skp_en : 1;
3811 uint64_t alt_skp_sel : 2;
3812 uint64_t reserved_39_63 : 25;
3813 #endif
3814 } cn66xx;
3815 struct cvmx_pip_prt_cfgbx_s cn68xx;
3816 struct cvmx_pip_prt_cfgbx_cn68xxp1 {
3817 #ifdef __BIG_ENDIAN_BITFIELD
3818 uint64_t reserved_24_63 : 40;
3819 uint64_t base : 8; /**< Base priority address into the table */
3820 uint64_t reserved_6_15 : 10;
3821 uint64_t bpid : 6; /**< Default BPID to use for packets on this port-kind. */
3822 #else
3823 uint64_t bpid : 6;
3824 uint64_t reserved_6_15 : 10;
3825 uint64_t base : 8;
3826 uint64_t reserved_24_63 : 40;
3827 #endif
3828 } cn68xxp1;
3829 struct cvmx_pip_prt_cfgbx_cn61xx cnf71xx;
3830 };
3831 typedef union cvmx_pip_prt_cfgbx cvmx_pip_prt_cfgbx_t;
3832
3833 /**
3834 * cvmx_pip_prt_tag#
3835 *
3836 * PIP_PRT_TAGX = Per port config information
3837 *
3838 */
3839 union cvmx_pip_prt_tagx {
3840 uint64_t u64;
3841 struct cvmx_pip_prt_tagx_s {
3842 #ifdef __BIG_ENDIAN_BITFIELD
3843 uint64_t reserved_54_63 : 10;
3844 uint64_t portadd_en : 1; /**< Enables PIP to optionally increment the incoming
3845 port from the MACs based on port-kind
3846 configuration and packet contents. */
3847 uint64_t inc_hwchk : 1; /**< Include the HW_checksum into WORD0 of the WQE
3848 instead of the L4PTR. This mode will be
3849 deprecated in future products. */
3850 uint64_t reserved_50_51 : 2;
3851 uint64_t grptagbase_msb : 2; /**< Most significant 2 bits of the GRPTAGBASE value. */
3852 uint64_t reserved_46_47 : 2;
3853 uint64_t grptagmask_msb : 2; /**< Most significant 2 bits of the GRPTAGMASK value.
3854 group when GRPTAG is set. */
3855 uint64_t reserved_42_43 : 2;
3856 uint64_t grp_msb : 2; /**< Most significant 2 bits of the 6-bit value
3857 indicating the group to schedule to. */
3858 uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits
3859 when GRPTAG is set. */
3860 uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing
3861 group when GRPTAG is set. */
3862 uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute
3863 the group in the work queue entry
3864 GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
3865 uint64_t grptag_mskip : 1; /**< When set, GRPTAG will be used regardless if the
3866 packet IS_IP. */
3867 uint64_t tag_mode : 2; /**< Which tag algorithm to use
3868 0 = always use tuple tag algorithm
3869 1 = always use mask tag algorithm
3870 2 = if packet is IP, use tuple else use mask
3871 3 = tuple XOR mask */
3872 uint64_t inc_vs : 2; /**< determines the DSA/VLAN ID (VID) to be included in
3873 tuple tag when VLAN stacking is detected
3874 0 = do not include VID in tuple tag generation
3875 1 = include VID (VLAN0) in hash
3876 2 = include VID (VLAN1) in hash
3877 3 = include VID ([VLAN0,VLAN1]) in hash */
3878 uint64_t inc_vlan : 1; /**< when set, the DSA/VLAN ID is included in tuple tag
3879 when VLAN stacking is not detected
3880 0 = do not include VID in tuple tag generation
3881 1 = include VID in hash */
3882 uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */
3883 uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
3884 included in tuple tag for IPv6 packets */
3885 uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
3886 included in tuple tag for IPv4 */
3887 uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
3888 included in tuple tag for IPv6 packets */
3889 uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
3890 included in tuple tag for IPv4 */
3891 uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple
3892 tag hash */
3893 uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple
3894 tag hash */
3895 uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple
3896 tag hash */
3897 uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple
3898 tag hash */
3899 uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple
3900 tag hash */
3901 uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple
3902 tag hash */
3903 cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6)
3904 0 = ordered tags
3905 1 = atomic tags
3906 2 = Null tags */
3907 cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4)
3908 0 = ordered tags
3909 1 = atomic tags
3910 2 = Null tags */
3911 cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type
3912 0 = ordered tags
3913 1 = atomic tags
3914 2 = Null tags */
3915 cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type
3916 0 = ordered tags
3917 1 = atomic tags
3918 2 = Null tags */
3919 cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type
3920 0 = ordered tags
3921 1 = atomic tags
3922 2 = Null tags */
3923 uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */
3924 #else
3925 uint64_t grp : 4;
3926 cvmx_pow_tag_type_t non_tag_type : 2;
3927 cvmx_pow_tag_type_t ip4_tag_type : 2;
3928 cvmx_pow_tag_type_t ip6_tag_type : 2;
3929 cvmx_pow_tag_type_t tcp4_tag_type : 2;
3930 cvmx_pow_tag_type_t tcp6_tag_type : 2;
3931 uint64_t ip4_src_flag : 1;
3932 uint64_t ip6_src_flag : 1;
3933 uint64_t ip4_dst_flag : 1;
3934 uint64_t ip6_dst_flag : 1;
3935 uint64_t ip4_pctl_flag : 1;
3936 uint64_t ip6_nxth_flag : 1;
3937 uint64_t ip4_sprt_flag : 1;
3938 uint64_t ip6_sprt_flag : 1;
3939 uint64_t ip4_dprt_flag : 1;
3940 uint64_t ip6_dprt_flag : 1;
3941 uint64_t inc_prt_flag : 1;
3942 uint64_t inc_vlan : 1;
3943 uint64_t inc_vs : 2;
3944 uint64_t tag_mode : 2;
3945 uint64_t grptag_mskip : 1;
3946 uint64_t grptag : 1;
3947 uint64_t grptagmask : 4;
3948 uint64_t grptagbase : 4;
3949 uint64_t grp_msb : 2;
3950 uint64_t reserved_42_43 : 2;
3951 uint64_t grptagmask_msb : 2;
3952 uint64_t reserved_46_47 : 2;
3953 uint64_t grptagbase_msb : 2;
3954 uint64_t reserved_50_51 : 2;
3955 uint64_t inc_hwchk : 1;
3956 uint64_t portadd_en : 1;
3957 uint64_t reserved_54_63 : 10;
3958 #endif
3959 } s;
3960 struct cvmx_pip_prt_tagx_cn30xx {
3961 #ifdef __BIG_ENDIAN_BITFIELD
3962 uint64_t reserved_40_63 : 24;
3963 uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits
3964 when GRPTAG is set. */
3965 uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing
3966 group when GRPTAG is set. */
3967 uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute
3968 the group in the work queue entry
3969 GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
3970 uint64_t reserved_30_30 : 1;
3971 uint64_t tag_mode : 2; /**< Which tag algorithm to use
3972 0 = always use tuple tag algorithm
3973 1 = always use mask tag algorithm
3974 2 = if packet is IP, use tuple else use mask
3975 3 = tuple XOR mask */
3976 uint64_t inc_vs : 2; /**< determines the VLAN ID (VID) to be included in
3977 tuple tag when VLAN stacking is detected
3978 0 = do not include VID in tuple tag generation
3979 1 = include VID (VLAN0) in hash
3980 2 = include VID (VLAN1) in hash
3981 3 = include VID ([VLAN0,VLAN1]) in hash */
3982 uint64_t inc_vlan : 1; /**< when set, the VLAN ID is included in tuple tag
3983 when VLAN stacking is not detected
3984 0 = do not include VID in tuple tag generation
3985 1 = include VID in hash */
3986 uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */
3987 uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
3988 included in tuple tag for IPv6 packets */
3989 uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
3990 included in tuple tag for IPv4 */
3991 uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
3992 included in tuple tag for IPv6 packets */
3993 uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
3994 included in tuple tag for IPv4 */
3995 uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple
3996 tag hash */
3997 uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple
3998 tag hash */
3999 uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple
4000 tag hash */
4001 uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple
4002 tag hash */
4003 uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple
4004 tag hash */
4005 uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple
4006 tag hash */
4007 cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6)
4008 0 = ordered tags
4009 1 = atomic tags
4010 2 = Null tags */
4011 cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4)
4012 0 = ordered tags
4013 1 = atomic tags
4014 2 = Null tags */
4015 cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type
4016 0 = ordered tags
4017 1 = atomic tags
4018 2 = Null tags */
4019 cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type
4020 0 = ordered tags
4021 1 = atomic tags
4022 2 = Null tags */
4023 cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type
4024 0 = ordered tags
4025 1 = atomic tags
4026 2 = Null tags */
4027 uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */
4028 #else
4029 uint64_t grp : 4;
4030 cvmx_pow_tag_type_t non_tag_type : 2;
4031 cvmx_pow_tag_type_t ip4_tag_type : 2;
4032 cvmx_pow_tag_type_t ip6_tag_type : 2;
4033 cvmx_pow_tag_type_t tcp4_tag_type : 2;
4034 cvmx_pow_tag_type_t tcp6_tag_type : 2;
4035 uint64_t ip4_src_flag : 1;
4036 uint64_t ip6_src_flag : 1;
4037 uint64_t ip4_dst_flag : 1;
4038 uint64_t ip6_dst_flag : 1;
4039 uint64_t ip4_pctl_flag : 1;
4040 uint64_t ip6_nxth_flag : 1;
4041 uint64_t ip4_sprt_flag : 1;
4042 uint64_t ip6_sprt_flag : 1;
4043 uint64_t ip4_dprt_flag : 1;
4044 uint64_t ip6_dprt_flag : 1;
4045 uint64_t inc_prt_flag : 1;
4046 uint64_t inc_vlan : 1;
4047 uint64_t inc_vs : 2;
4048 uint64_t tag_mode : 2;
4049 uint64_t reserved_30_30 : 1;
4050 uint64_t grptag : 1;
4051 uint64_t grptagmask : 4;
4052 uint64_t grptagbase : 4;
4053 uint64_t reserved_40_63 : 24;
4054 #endif
4055 } cn30xx;
4056 struct cvmx_pip_prt_tagx_cn30xx cn31xx;
4057 struct cvmx_pip_prt_tagx_cn30xx cn38xx;
4058 struct cvmx_pip_prt_tagx_cn30xx cn38xxp2;
4059 struct cvmx_pip_prt_tagx_cn50xx {
4060 #ifdef __BIG_ENDIAN_BITFIELD
4061 uint64_t reserved_40_63 : 24;
4062 uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits
4063 when GRPTAG is set. */
4064 uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing
4065 group when GRPTAG is set. */
4066 uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute
4067 the group in the work queue entry
4068 GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
4069 uint64_t grptag_mskip : 1; /**< When set, GRPTAG will be used regardless if the
4070 packet IS_IP. */
4071 uint64_t tag_mode : 2; /**< Which tag algorithm to use
4072 0 = always use tuple tag algorithm
4073 1 = always use mask tag algorithm
4074 2 = if packet is IP, use tuple else use mask
4075 3 = tuple XOR mask */
4076 uint64_t inc_vs : 2; /**< determines the VLAN ID (VID) to be included in
4077 tuple tag when VLAN stacking is detected
4078 0 = do not include VID in tuple tag generation
4079 1 = include VID (VLAN0) in hash
4080 2 = include VID (VLAN1) in hash
4081 3 = include VID ([VLAN0,VLAN1]) in hash */
4082 uint64_t inc_vlan : 1; /**< when set, the VLAN ID is included in tuple tag
4083 when VLAN stacking is not detected
4084 0 = do not include VID in tuple tag generation
4085 1 = include VID in hash */
4086 uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */
4087 uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
4088 included in tuple tag for IPv6 packets */
4089 uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
4090 included in tuple tag for IPv4 */
4091 uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
4092 included in tuple tag for IPv6 packets */
4093 uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
4094 included in tuple tag for IPv4 */
4095 uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple
4096 tag hash */
4097 uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple
4098 tag hash */
4099 uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple
4100 tag hash */
4101 uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple
4102 tag hash */
4103 uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple
4104 tag hash */
4105 uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple
4106 tag hash */
4107 cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6)
4108 0 = ordered tags
4109 1 = atomic tags
4110 2 = Null tags */
4111 cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4)
4112 0 = ordered tags
4113 1 = atomic tags
4114 2 = Null tags */
4115 cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type
4116 0 = ordered tags
4117 1 = atomic tags
4118 2 = Null tags */
4119 cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type
4120 0 = ordered tags
4121 1 = atomic tags
4122 2 = Null tags */
4123 cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type
4124 0 = ordered tags
4125 1 = atomic tags
4126 2 = Null tags */
4127 uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */
4128 #else
4129 uint64_t grp : 4;
4130 cvmx_pow_tag_type_t non_tag_type : 2;
4131 cvmx_pow_tag_type_t ip4_tag_type : 2;
4132 cvmx_pow_tag_type_t ip6_tag_type : 2;
4133 cvmx_pow_tag_type_t tcp4_tag_type : 2;
4134 cvmx_pow_tag_type_t tcp6_tag_type : 2;
4135 uint64_t ip4_src_flag : 1;
4136 uint64_t ip6_src_flag : 1;
4137 uint64_t ip4_dst_flag : 1;
4138 uint64_t ip6_dst_flag : 1;
4139 uint64_t ip4_pctl_flag : 1;
4140 uint64_t ip6_nxth_flag : 1;
4141 uint64_t ip4_sprt_flag : 1;
4142 uint64_t ip6_sprt_flag : 1;
4143 uint64_t ip4_dprt_flag : 1;
4144 uint64_t ip6_dprt_flag : 1;
4145 uint64_t inc_prt_flag : 1;
4146 uint64_t inc_vlan : 1;
4147 uint64_t inc_vs : 2;
4148 uint64_t tag_mode : 2;
4149 uint64_t grptag_mskip : 1;
4150 uint64_t grptag : 1;
4151 uint64_t grptagmask : 4;
4152 uint64_t grptagbase : 4;
4153 uint64_t reserved_40_63 : 24;
4154 #endif
4155 } cn50xx;
4156 struct cvmx_pip_prt_tagx_cn50xx cn52xx;
4157 struct cvmx_pip_prt_tagx_cn50xx cn52xxp1;
4158 struct cvmx_pip_prt_tagx_cn50xx cn56xx;
4159 struct cvmx_pip_prt_tagx_cn50xx cn56xxp1;
4160 struct cvmx_pip_prt_tagx_cn30xx cn58xx;
4161 struct cvmx_pip_prt_tagx_cn30xx cn58xxp1;
4162 struct cvmx_pip_prt_tagx_cn50xx cn61xx;
4163 struct cvmx_pip_prt_tagx_cn50xx cn63xx;
4164 struct cvmx_pip_prt_tagx_cn50xx cn63xxp1;
4165 struct cvmx_pip_prt_tagx_cn50xx cn66xx;
4166 struct cvmx_pip_prt_tagx_s cn68xx;
4167 struct cvmx_pip_prt_tagx_s cn68xxp1;
4168 struct cvmx_pip_prt_tagx_cn50xx cnf71xx;
4169 };
4170 typedef union cvmx_pip_prt_tagx cvmx_pip_prt_tagx_t;
4171
4172 /**
4173 * cvmx_pip_qos_diff#
4174 *
4175 * PIP_QOS_DIFFX = QOS Diffserv Tables
4176 *
4177 */
4178 union cvmx_pip_qos_diffx {
4179 uint64_t u64;
4180 struct cvmx_pip_qos_diffx_s {
4181 #ifdef __BIG_ENDIAN_BITFIELD
4182 uint64_t reserved_3_63 : 61;
4183 uint64_t qos : 3; /**< Diffserv QOS level */
4184 #else
4185 uint64_t qos : 3;
4186 uint64_t reserved_3_63 : 61;
4187 #endif
4188 } s;
4189 struct cvmx_pip_qos_diffx_s cn30xx;
4190 struct cvmx_pip_qos_diffx_s cn31xx;
4191 struct cvmx_pip_qos_diffx_s cn38xx;
4192 struct cvmx_pip_qos_diffx_s cn38xxp2;
4193 struct cvmx_pip_qos_diffx_s cn50xx;
4194 struct cvmx_pip_qos_diffx_s cn52xx;
4195 struct cvmx_pip_qos_diffx_s cn52xxp1;
4196 struct cvmx_pip_qos_diffx_s cn56xx;
4197 struct cvmx_pip_qos_diffx_s cn56xxp1;
4198 struct cvmx_pip_qos_diffx_s cn58xx;
4199 struct cvmx_pip_qos_diffx_s cn58xxp1;
4200 struct cvmx_pip_qos_diffx_s cn61xx;
4201 struct cvmx_pip_qos_diffx_s cn63xx;
4202 struct cvmx_pip_qos_diffx_s cn63xxp1;
4203 struct cvmx_pip_qos_diffx_s cn66xx;
4204 struct cvmx_pip_qos_diffx_s cnf71xx;
4205 };
4206 typedef union cvmx_pip_qos_diffx cvmx_pip_qos_diffx_t;
4207
4208 /**
4209 * cvmx_pip_qos_vlan#
4210 *
4211 * PIP_QOS_VLANX = QOS VLAN Tables
4212 *
4213 * If the PIP indentifies a packet is DSA/VLAN tagged, then the QOS
4214 * can be set based on the DSA/VLAN user priority. These eight register
4215 * comprise the QOS values for all DSA/VLAN user priority values.
4216 */
4217 union cvmx_pip_qos_vlanx {
4218 uint64_t u64;
4219 struct cvmx_pip_qos_vlanx_s {
4220 #ifdef __BIG_ENDIAN_BITFIELD
4221 uint64_t reserved_7_63 : 57;
4222 uint64_t qos1 : 3; /**< DSA/VLAN QOS level
4223 Selected when PIP_PRT_CFGx[QOS_VSEL] = 1 */
4224 uint64_t reserved_3_3 : 1;
4225 uint64_t qos : 3; /**< DSA/VLAN QOS level
4226 Selected when PIP_PRT_CFGx[QOS_VSEL] = 0 */
4227 #else
4228 uint64_t qos : 3;
4229 uint64_t reserved_3_3 : 1;
4230 uint64_t qos1 : 3;
4231 uint64_t reserved_7_63 : 57;
4232 #endif
4233 } s;
4234 struct cvmx_pip_qos_vlanx_cn30xx {
4235 #ifdef __BIG_ENDIAN_BITFIELD
4236 uint64_t reserved_3_63 : 61;
4237 uint64_t qos : 3; /**< VLAN QOS level */
4238 #else
4239 uint64_t qos : 3;
4240 uint64_t reserved_3_63 : 61;
4241 #endif
4242 } cn30xx;
4243 struct cvmx_pip_qos_vlanx_cn30xx cn31xx;
4244 struct cvmx_pip_qos_vlanx_cn30xx cn38xx;
4245 struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;
4246 struct cvmx_pip_qos_vlanx_cn30xx cn50xx;
4247 struct cvmx_pip_qos_vlanx_s cn52xx;
4248 struct cvmx_pip_qos_vlanx_s cn52xxp1;
4249 struct cvmx_pip_qos_vlanx_s cn56xx;
4250 struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;
4251 struct cvmx_pip_qos_vlanx_cn30xx cn58xx;
4252 struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;
4253 struct cvmx_pip_qos_vlanx_s cn61xx;
4254 struct cvmx_pip_qos_vlanx_s cn63xx;
4255 struct cvmx_pip_qos_vlanx_s cn63xxp1;
4256 struct cvmx_pip_qos_vlanx_s cn66xx;
4257 struct cvmx_pip_qos_vlanx_s cnf71xx;
4258 };
4259 typedef union cvmx_pip_qos_vlanx cvmx_pip_qos_vlanx_t;
4260
4261 /**
4262 * cvmx_pip_qos_watch#
4263 *
4264 * PIP_QOS_WATCHX = QOS Watcher Tables
4265 *
4266 * Sets up the Configuration CSRs for the four QOS Watchers.
4267 * Each Watcher can be set to look for a specific protocol,
4268 * TCP/UDP destination port, or Ethertype to override the
4269 * default QOS value.
4270 */
4271 union cvmx_pip_qos_watchx {
4272 uint64_t u64;
4273 struct cvmx_pip_qos_watchx_s {
4274 #ifdef __BIG_ENDIAN_BITFIELD
4275 uint64_t reserved_48_63 : 16;
4276 uint64_t mask : 16; /**< Mask off a range of values */
4277 uint64_t reserved_30_31 : 2;
4278 uint64_t grp : 6; /**< The GRP number of the watcher */
4279 uint64_t reserved_23_23 : 1;
4280 uint64_t qos : 3; /**< The QOS level of the watcher */
4281 uint64_t reserved_19_19 : 1;
4282 cvmx_pip_qos_watch_types match_type : 3; /**< The field for the watcher match against
4283 0 = disable across all ports
4284 1 = protocol (ipv4)
4285 = next_header (ipv6)
4286 2 = TCP destination port
4287 3 = UDP destination port
4288 4 = Ether type
4289 5-7 = Reserved */
4290 uint64_t match_value : 16; /**< The value to watch for */
4291 #else
4292 uint64_t match_value : 16;
4293 cvmx_pip_qos_watch_types match_type : 3;
4294 uint64_t reserved_19_19 : 1;
4295 uint64_t qos : 3;
4296 uint64_t reserved_23_23 : 1;
4297 uint64_t grp : 6;
4298 uint64_t reserved_30_31 : 2;
4299 uint64_t mask : 16;
4300 uint64_t reserved_48_63 : 16;
4301 #endif
4302 } s;
4303 struct cvmx_pip_qos_watchx_cn30xx {
4304 #ifdef __BIG_ENDIAN_BITFIELD
4305 uint64_t reserved_48_63 : 16;
4306 uint64_t mask : 16; /**< Mask off a range of values */
4307 uint64_t reserved_28_31 : 4;
4308 uint64_t grp : 4; /**< The GRP number of the watcher */
4309 uint64_t reserved_23_23 : 1;
4310 uint64_t qos : 3; /**< The QOS level of the watcher */
4311 uint64_t reserved_18_19 : 2;
4312 cvmx_pip_qos_watch_types match_type : 2; /**< The field for the watcher match against
4313 0 = disable across all ports
4314 1 = protocol (ipv4)
4315 = next_header (ipv6)
4316 2 = TCP destination port
4317 3 = UDP destination port */
4318 uint64_t match_value : 16; /**< The value to watch for */
4319 #else
4320 uint64_t match_value : 16;
4321 cvmx_pip_qos_watch_types match_type : 2;
4322 uint64_t reserved_18_19 : 2;
4323 uint64_t qos : 3;
4324 uint64_t reserved_23_23 : 1;
4325 uint64_t grp : 4;
4326 uint64_t reserved_28_31 : 4;
4327 uint64_t mask : 16;
4328 uint64_t reserved_48_63 : 16;
4329 #endif
4330 } cn30xx;
4331 struct cvmx_pip_qos_watchx_cn30xx cn31xx;
4332 struct cvmx_pip_qos_watchx_cn30xx cn38xx;
4333 struct cvmx_pip_qos_watchx_cn30xx cn38xxp2;
4334 struct cvmx_pip_qos_watchx_cn50xx {
4335 #ifdef __BIG_ENDIAN_BITFIELD
4336 uint64_t reserved_48_63 : 16;
4337 uint64_t mask : 16; /**< Mask off a range of values */
4338 uint64_t reserved_28_31 : 4;
4339 uint64_t grp : 4; /**< The GRP number of the watcher */
4340 uint64_t reserved_23_23 : 1;
4341 uint64_t qos : 3; /**< The QOS level of the watcher */
4342 uint64_t reserved_19_19 : 1;
4343 cvmx_pip_qos_watch_types match_type : 3; /**< The field for the watcher match against
4344 0 = disable across all ports
4345 1 = protocol (ipv4)
4346 = next_header (ipv6)
4347 2 = TCP destination port
4348 3 = UDP destination port
4349 4 = Ether type
4350 5-7 = Reserved */
4351 uint64_t match_value : 16; /**< The value to watch for */
4352 #else
4353 uint64_t match_value : 16;
4354 cvmx_pip_qos_watch_types match_type : 3;
4355 uint64_t reserved_19_19 : 1;
4356 uint64_t qos : 3;
4357 uint64_t reserved_23_23 : 1;
4358 uint64_t grp : 4;
4359 uint64_t reserved_28_31 : 4;
4360 uint64_t mask : 16;
4361 uint64_t reserved_48_63 : 16;
4362 #endif
4363 } cn50xx;
4364 struct cvmx_pip_qos_watchx_cn50xx cn52xx;
4365 struct cvmx_pip_qos_watchx_cn50xx cn52xxp1;
4366 struct cvmx_pip_qos_watchx_cn50xx cn56xx;
4367 struct cvmx_pip_qos_watchx_cn50xx cn56xxp1;
4368 struct cvmx_pip_qos_watchx_cn30xx cn58xx;
4369 struct cvmx_pip_qos_watchx_cn30xx cn58xxp1;
4370 struct cvmx_pip_qos_watchx_cn50xx cn61xx;
4371 struct cvmx_pip_qos_watchx_cn50xx cn63xx;
4372 struct cvmx_pip_qos_watchx_cn50xx cn63xxp1;
4373 struct cvmx_pip_qos_watchx_cn50xx cn66xx;
4374 struct cvmx_pip_qos_watchx_s cn68xx;
4375 struct cvmx_pip_qos_watchx_s cn68xxp1;
4376 struct cvmx_pip_qos_watchx_cn50xx cnf71xx;
4377 };
4378 typedef union cvmx_pip_qos_watchx cvmx_pip_qos_watchx_t;
4379
4380 /**
4381 * cvmx_pip_raw_word
4382 *
4383 * PIP_RAW_WORD = The RAW Word2 of the workQ entry.
4384 *
4385 * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets.
4386 */
4387 union cvmx_pip_raw_word {
4388 uint64_t u64;
4389 struct cvmx_pip_raw_word_s {
4390 #ifdef __BIG_ENDIAN_BITFIELD
4391 uint64_t reserved_56_63 : 8;
4392 uint64_t word : 56; /**< Word2 of the workQ entry
4393 The 8-bit bufs field is still set by HW (IPD) */
4394 #else
4395 uint64_t word : 56;
4396 uint64_t reserved_56_63 : 8;
4397 #endif
4398 } s;
4399 struct cvmx_pip_raw_word_s cn30xx;
4400 struct cvmx_pip_raw_word_s cn31xx;
4401 struct cvmx_pip_raw_word_s cn38xx;
4402 struct cvmx_pip_raw_word_s cn38xxp2;
4403 struct cvmx_pip_raw_word_s cn50xx;
4404 struct cvmx_pip_raw_word_s cn52xx;
4405 struct cvmx_pip_raw_word_s cn52xxp1;
4406 struct cvmx_pip_raw_word_s cn56xx;
4407 struct cvmx_pip_raw_word_s cn56xxp1;
4408 struct cvmx_pip_raw_word_s cn58xx;
4409 struct cvmx_pip_raw_word_s cn58xxp1;
4410 struct cvmx_pip_raw_word_s cn61xx;
4411 struct cvmx_pip_raw_word_s cn63xx;
4412 struct cvmx_pip_raw_word_s cn63xxp1;
4413 struct cvmx_pip_raw_word_s cn66xx;
4414 struct cvmx_pip_raw_word_s cn68xx;
4415 struct cvmx_pip_raw_word_s cn68xxp1;
4416 struct cvmx_pip_raw_word_s cnf71xx;
4417 };
4418 typedef union cvmx_pip_raw_word cvmx_pip_raw_word_t;
4419
4420 /**
4421 * cvmx_pip_sft_rst
4422 *
4423 * PIP_SFT_RST = PIP Soft Reset
4424 *
4425 * When written to a '1', resets the pip block
4426 *
4427 * Notes:
4428 * When RST is set to a '1' by SW, PIP will get a short reset pulse (3 cycles
4429 * in duration). Although this will reset much of PIP's internal state, some
4430 * CSRs will not reset.
4431 *
4432 * . PIP_BIST_STATUS
4433 * . PIP_STAT0_PRT*
4434 * . PIP_STAT1_PRT*
4435 * . PIP_STAT2_PRT*
4436 * . PIP_STAT3_PRT*
4437 * . PIP_STAT4_PRT*
4438 * . PIP_STAT5_PRT*
4439 * . PIP_STAT6_PRT*
4440 * . PIP_STAT7_PRT*
4441 * . PIP_STAT8_PRT*
4442 * . PIP_STAT9_PRT*
4443 * . PIP_XSTAT0_PRT*
4444 * . PIP_XSTAT1_PRT*
4445 * . PIP_XSTAT2_PRT*
4446 * . PIP_XSTAT3_PRT*
4447 * . PIP_XSTAT4_PRT*
4448 * . PIP_XSTAT5_PRT*
4449 * . PIP_XSTAT6_PRT*
4450 * . PIP_XSTAT7_PRT*
4451 * . PIP_XSTAT8_PRT*
4452 * . PIP_XSTAT9_PRT*
4453 * . PIP_STAT_INB_PKTS*
4454 * . PIP_STAT_INB_OCTS*
4455 * . PIP_STAT_INB_ERRS*
4456 * . PIP_TAG_INC*
4457 */
4458 union cvmx_pip_sft_rst {
4459 uint64_t u64;
4460 struct cvmx_pip_sft_rst_s {
4461 #ifdef __BIG_ENDIAN_BITFIELD
4462 uint64_t reserved_1_63 : 63;
4463 uint64_t rst : 1; /**< Soft Reset */
4464 #else
4465 uint64_t rst : 1;
4466 uint64_t reserved_1_63 : 63;
4467 #endif
4468 } s;
4469 struct cvmx_pip_sft_rst_s cn30xx;
4470 struct cvmx_pip_sft_rst_s cn31xx;
4471 struct cvmx_pip_sft_rst_s cn38xx;
4472 struct cvmx_pip_sft_rst_s cn50xx;
4473 struct cvmx_pip_sft_rst_s cn52xx;
4474 struct cvmx_pip_sft_rst_s cn52xxp1;
4475 struct cvmx_pip_sft_rst_s cn56xx;
4476 struct cvmx_pip_sft_rst_s cn56xxp1;
4477 struct cvmx_pip_sft_rst_s cn58xx;
4478 struct cvmx_pip_sft_rst_s cn58xxp1;
4479 struct cvmx_pip_sft_rst_s cn61xx;
4480 struct cvmx_pip_sft_rst_s cn63xx;
4481 struct cvmx_pip_sft_rst_s cn63xxp1;
4482 struct cvmx_pip_sft_rst_s cn66xx;
4483 struct cvmx_pip_sft_rst_s cn68xx;
4484 struct cvmx_pip_sft_rst_s cn68xxp1;
4485 struct cvmx_pip_sft_rst_s cnf71xx;
4486 };
4487 typedef union cvmx_pip_sft_rst cvmx_pip_sft_rst_t;
4488
4489 /**
4490 * cvmx_pip_stat0_#
4491 *
4492 * PIP Statistics Counters
4493 *
4494 * Note: special stat counter behavior
4495 *
4496 * 1) Read and write operations must arbitrate for the statistics resources
4497 * along with the packet engines which are incrementing the counters.
4498 * In order to not drop packet information, the packet HW is always a
4499 * higher priority and the CSR requests will only be satisified when
4500 * there are idle cycles. This can potentially cause long delays if the
4501 * system becomes full.
4502 *
4503 * 2) stat counters can be cleared in two ways. If PIP_STAT_CTL[RDCLR] is
4504 * set, then all read accesses will clear the register. In addition,
4505 * any write to a stats register will also reset the register to zero.
4506 * Please note that the clearing operations must obey rule \#1 above.
4507 *
4508 * 3) all counters are wrapping - software must ensure they are read periodically
4509 *
4510 * 4) The counters accumulate statistics for packets that are sent to PKI. If
4511 * PTP_MODE is enabled, the 8B timestamp is prepended to the packet. This
4512 * additional 8B of data is captured in the octet counts.
4513 *
4514 * 5) X represents either the packet's port-kind or backpressure ID as
4515 * determined by PIP_STAT_CTL[MODE]
4516 * PIP_STAT0_X = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS
4517 */
4518 union cvmx_pip_stat0_x {
4519 uint64_t u64;
4520 struct cvmx_pip_stat0_x_s {
4521 #ifdef __BIG_ENDIAN_BITFIELD
4522 uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD
4523 QOS widget per port */
4524 uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD
4525 QOS widget per port */
4526 #else
4527 uint64_t drp_octs : 32;
4528 uint64_t drp_pkts : 32;
4529 #endif
4530 } s;
4531 struct cvmx_pip_stat0_x_s cn68xx;
4532 struct cvmx_pip_stat0_x_s cn68xxp1;
4533 };
4534 typedef union cvmx_pip_stat0_x cvmx_pip_stat0_x_t;
4535
4536 /**
4537 * cvmx_pip_stat0_prt#
4538 *
4539 * PIP Statistics Counters
4540 *
4541 * Note: special stat counter behavior
4542 *
4543 * 1) Read and write operations must arbitrate for the statistics resources
4544 * along with the packet engines which are incrementing the counters.
4545 * In order to not drop packet information, the packet HW is always a
4546 * higher priority and the CSR requests will only be satisified when
4547 * there are idle cycles. This can potentially cause long delays if the
4548 * system becomes full.
4549 *
4550 * 2) stat counters can be cleared in two ways. If PIP_STAT_CTL[RDCLR] is
4551 * set, then all read accesses will clear the register. In addition,
4552 * any write to a stats register will also reset the register to zero.
4553 * Please note that the clearing operations must obey rule \#1 above.
4554 *
4555 * 3) all counters are wrapping - software must ensure they are read periodically
4556 *
4557 * 4) The counters accumulate statistics for packets that are sent to PKI. If
4558 * PTP_MODE is enabled, the 8B timestamp is prepended to the packet. This
4559 * additional 8B of data is captured in the octet counts.
4560 * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS
4561 */
4562 union cvmx_pip_stat0_prtx {
4563 uint64_t u64;
4564 struct cvmx_pip_stat0_prtx_s {
4565 #ifdef __BIG_ENDIAN_BITFIELD
4566 uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD
4567 QOS widget per port */
4568 uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD
4569 QOS widget per port */
4570 #else
4571 uint64_t drp_octs : 32;
4572 uint64_t drp_pkts : 32;
4573 #endif
4574 } s;
4575 struct cvmx_pip_stat0_prtx_s cn30xx;
4576 struct cvmx_pip_stat0_prtx_s cn31xx;
4577 struct cvmx_pip_stat0_prtx_s cn38xx;
4578 struct cvmx_pip_stat0_prtx_s cn38xxp2;
4579 struct cvmx_pip_stat0_prtx_s cn50xx;
4580 struct cvmx_pip_stat0_prtx_s cn52xx;
4581 struct cvmx_pip_stat0_prtx_s cn52xxp1;
4582 struct cvmx_pip_stat0_prtx_s cn56xx;
4583 struct cvmx_pip_stat0_prtx_s cn56xxp1;
4584 struct cvmx_pip_stat0_prtx_s cn58xx;
4585 struct cvmx_pip_stat0_prtx_s cn58xxp1;
4586 struct cvmx_pip_stat0_prtx_s cn61xx;
4587 struct cvmx_pip_stat0_prtx_s cn63xx;
4588 struct cvmx_pip_stat0_prtx_s cn63xxp1;
4589 struct cvmx_pip_stat0_prtx_s cn66xx;
4590 struct cvmx_pip_stat0_prtx_s cnf71xx;
4591 };
4592 typedef union cvmx_pip_stat0_prtx cvmx_pip_stat0_prtx_t;
4593
4594 /**
4595 * cvmx_pip_stat10_#
4596 *
4597 * PIP_STAT10_X = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST
4598 *
4599 */
4600 union cvmx_pip_stat10_x {
4601 uint64_t u64;
4602 struct cvmx_pip_stat10_x_s {
4603 #ifdef __BIG_ENDIAN_BITFIELD
4604 uint64_t bcast : 32; /**< Number of packets with L2 Broadcast DMAC
4605 that were dropped due to RED.
4606 The HW will consider a packet to be an L2
4607 broadcast packet when the 48-bit DMAC is all 1's.
4608 Only applies when the parse mode for the packet
4609 is SKIP-TO-L2. */
4610 uint64_t mcast : 32; /**< Number of packets with L2 Mulitcast DMAC
4611 that were dropped due to RED.
4612 The HW will consider a packet to be an L2
4613 multicast packet when the least-significant bit
4614 of the first byte of the DMAC is set and the
4615 packet is not an L2 broadcast packet.
4616 Only applies when the parse mode for the packet
4617 is SKIP-TO-L2. */
4618 #else
4619 uint64_t mcast : 32;
4620 uint64_t bcast : 32;
4621 #endif
4622 } s;
4623 struct cvmx_pip_stat10_x_s cn68xx;
4624 struct cvmx_pip_stat10_x_s cn68xxp1;
4625 };
4626 typedef union cvmx_pip_stat10_x cvmx_pip_stat10_x_t;
4627
4628 /**
4629 * cvmx_pip_stat10_prt#
4630 *
4631 * PIP_STAT10_PRTX = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST
4632 *
4633 */
4634 union cvmx_pip_stat10_prtx {
4635 uint64_t u64;
4636 struct cvmx_pip_stat10_prtx_s {
4637 #ifdef __BIG_ENDIAN_BITFIELD
4638 uint64_t bcast : 32; /**< Number of packets with L2 Broadcast DMAC
4639 that were dropped due to RED.
4640 The HW will consider a packet to be an L2
4641 broadcast packet when the 48-bit DMAC is all 1's.
4642 Only applies when the parse mode for the packet
4643 is SKIP-TO-L2. */
4644 uint64_t mcast : 32; /**< Number of packets with L2 Mulitcast DMAC
4645 that were dropped due to RED.
4646 The HW will consider a packet to be an L2
4647 multicast packet when the least-significant bit
4648 of the first byte of the DMAC is set and the
4649 packet is not an L2 broadcast packet.
4650 Only applies when the parse mode for the packet
4651 is SKIP-TO-L2. */
4652 #else
4653 uint64_t mcast : 32;
4654 uint64_t bcast : 32;
4655 #endif
4656 } s;
4657 struct cvmx_pip_stat10_prtx_s cn52xx;
4658 struct cvmx_pip_stat10_prtx_s cn52xxp1;
4659 struct cvmx_pip_stat10_prtx_s cn56xx;
4660 struct cvmx_pip_stat10_prtx_s cn56xxp1;
4661 struct cvmx_pip_stat10_prtx_s cn61xx;
4662 struct cvmx_pip_stat10_prtx_s cn63xx;
4663 struct cvmx_pip_stat10_prtx_s cn63xxp1;
4664 struct cvmx_pip_stat10_prtx_s cn66xx;
4665 struct cvmx_pip_stat10_prtx_s cnf71xx;
4666 };
4667 typedef union cvmx_pip_stat10_prtx cvmx_pip_stat10_prtx_t;
4668
4669 /**
4670 * cvmx_pip_stat11_#
4671 *
4672 * PIP_STAT11_X = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST
4673 *
4674 */
4675 union cvmx_pip_stat11_x {
4676 uint64_t u64;
4677 struct cvmx_pip_stat11_x_s {
4678 #ifdef __BIG_ENDIAN_BITFIELD
4679 uint64_t bcast : 32; /**< Number of packets with L3 Broadcast Dest Address
4680 that were dropped due to RED.
4681 The HW considers an IPv4 packet to be broadcast
4682 when all bits are set in the MSB of the
4683 destination address. IPv6 does not have the
4684 concept of a broadcast packets.
4685 Only applies when the parse mode for the packet
4686 is SKIP-TO-L2 and the packet is IP or the parse
4687 mode for the packet is SKIP-TO-IP. */
4688 uint64_t mcast : 32; /**< Number of packets with L3 Multicast Dest Address
4689 that were dropped due to RED.
4690 The HW considers an IPv4 packet to be multicast
4691 when the most-significant nibble of the 32-bit
4692 destination address is 0xE (i.e. it is a class D
4693 address). The HW considers an IPv6 packet to be
4694 multicast when the most-significant byte of the
4695 128-bit destination address is all 1's.
4696 Only applies when the parse mode for the packet
4697 is SKIP-TO-L2 and the packet is IP or the parse
4698 mode for the packet is SKIP-TO-IP. */
4699 #else
4700 uint64_t mcast : 32;
4701 uint64_t bcast : 32;
4702 #endif
4703 } s;
4704 struct cvmx_pip_stat11_x_s cn68xx;
4705 struct cvmx_pip_stat11_x_s cn68xxp1;
4706 };
4707 typedef union cvmx_pip_stat11_x cvmx_pip_stat11_x_t;
4708
4709 /**
4710 * cvmx_pip_stat11_prt#
4711 *
4712 * PIP_STAT11_PRTX = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST
4713 *
4714 */
4715 union cvmx_pip_stat11_prtx {
4716 uint64_t u64;
4717 struct cvmx_pip_stat11_prtx_s {
4718 #ifdef __BIG_ENDIAN_BITFIELD
4719 uint64_t bcast : 32; /**< Number of packets with L3 Broadcast Dest Address
4720 that were dropped due to RED.
4721 The HW considers an IPv4 packet to be broadcast
4722 when all bits are set in the MSB of the
4723 destination address. IPv6 does not have the
4724 concept of a broadcast packets.
4725 Only applies when the parse mode for the packet
4726 is SKIP-TO-L2 and the packet is IP or the parse
4727 mode for the packet is SKIP-TO-IP. */
4728 uint64_t mcast : 32; /**< Number of packets with L3 Multicast Dest Address
4729 that were dropped due to RED.
4730 The HW considers an IPv4 packet to be multicast
4731 when the most-significant nibble of the 32-bit
4732 destination address is 0xE (i.e. it is a class D
4733 address). The HW considers an IPv6 packet to be
4734 multicast when the most-significant byte of the
4735 128-bit destination address is all 1's.
4736 Only applies when the parse mode for the packet
4737 is SKIP-TO-L2 and the packet is IP or the parse
4738 mode for the packet is SKIP-TO-IP. */
4739 #else
4740 uint64_t mcast : 32;
4741 uint64_t bcast : 32;
4742 #endif
4743 } s;
4744 struct cvmx_pip_stat11_prtx_s cn52xx;
4745 struct cvmx_pip_stat11_prtx_s cn52xxp1;
4746 struct cvmx_pip_stat11_prtx_s cn56xx;
4747 struct cvmx_pip_stat11_prtx_s cn56xxp1;
4748 struct cvmx_pip_stat11_prtx_s cn61xx;
4749 struct cvmx_pip_stat11_prtx_s cn63xx;
4750 struct cvmx_pip_stat11_prtx_s cn63xxp1;
4751 struct cvmx_pip_stat11_prtx_s cn66xx;
4752 struct cvmx_pip_stat11_prtx_s cnf71xx;
4753 };
4754 typedef union cvmx_pip_stat11_prtx cvmx_pip_stat11_prtx_t;
4755
4756 /**
4757 * cvmx_pip_stat1_#
4758 *
4759 * PIP_STAT1_X = PIP_STAT_OCTS
4760 *
4761 */
4762 union cvmx_pip_stat1_x {
4763 uint64_t u64;
4764 struct cvmx_pip_stat1_x_s {
4765 #ifdef __BIG_ENDIAN_BITFIELD
4766 uint64_t reserved_48_63 : 16;
4767 uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */
4768 #else
4769 uint64_t octs : 48;
4770 uint64_t reserved_48_63 : 16;
4771 #endif
4772 } s;
4773 struct cvmx_pip_stat1_x_s cn68xx;
4774 struct cvmx_pip_stat1_x_s cn68xxp1;
4775 };
4776 typedef union cvmx_pip_stat1_x cvmx_pip_stat1_x_t;
4777
4778 /**
4779 * cvmx_pip_stat1_prt#
4780 *
4781 * PIP_STAT1_PRTX = PIP_STAT_OCTS
4782 *
4783 */
4784 union cvmx_pip_stat1_prtx {
4785 uint64_t u64;
4786 struct cvmx_pip_stat1_prtx_s {
4787 #ifdef __BIG_ENDIAN_BITFIELD
4788 uint64_t reserved_48_63 : 16;
4789 uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */
4790 #else
4791 uint64_t octs : 48;
4792 uint64_t reserved_48_63 : 16;
4793 #endif
4794 } s;
4795 struct cvmx_pip_stat1_prtx_s cn30xx;
4796 struct cvmx_pip_stat1_prtx_s cn31xx;
4797 struct cvmx_pip_stat1_prtx_s cn38xx;
4798 struct cvmx_pip_stat1_prtx_s cn38xxp2;
4799 struct cvmx_pip_stat1_prtx_s cn50xx;
4800 struct cvmx_pip_stat1_prtx_s cn52xx;
4801 struct cvmx_pip_stat1_prtx_s cn52xxp1;
4802 struct cvmx_pip_stat1_prtx_s cn56xx;
4803 struct cvmx_pip_stat1_prtx_s cn56xxp1;
4804 struct cvmx_pip_stat1_prtx_s cn58xx;
4805 struct cvmx_pip_stat1_prtx_s cn58xxp1;
4806 struct cvmx_pip_stat1_prtx_s cn61xx;
4807 struct cvmx_pip_stat1_prtx_s cn63xx;
4808 struct cvmx_pip_stat1_prtx_s cn63xxp1;
4809 struct cvmx_pip_stat1_prtx_s cn66xx;
4810 struct cvmx_pip_stat1_prtx_s cnf71xx;
4811 };
4812 typedef union cvmx_pip_stat1_prtx cvmx_pip_stat1_prtx_t;
4813
4814 /**
4815 * cvmx_pip_stat2_#
4816 *
4817 * PIP_STAT2_X = PIP_STAT_PKTS / PIP_STAT_RAW
4818 *
4819 */
4820 union cvmx_pip_stat2_x {
4821 uint64_t u64;
4822 struct cvmx_pip_stat2_x_s {
4823 #ifdef __BIG_ENDIAN_BITFIELD
4824 uint64_t pkts : 32; /**< Number of packets processed by PIP */
4825 uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
4826 received by PIP per port */
4827 #else
4828 uint64_t raw : 32;
4829 uint64_t pkts : 32;
4830 #endif
4831 } s;
4832 struct cvmx_pip_stat2_x_s cn68xx;
4833 struct cvmx_pip_stat2_x_s cn68xxp1;
4834 };
4835 typedef union cvmx_pip_stat2_x cvmx_pip_stat2_x_t;
4836
4837 /**
4838 * cvmx_pip_stat2_prt#
4839 *
4840 * PIP_STAT2_PRTX = PIP_STAT_PKTS / PIP_STAT_RAW
4841 *
4842 */
4843 union cvmx_pip_stat2_prtx {
4844 uint64_t u64;
4845 struct cvmx_pip_stat2_prtx_s {
4846 #ifdef __BIG_ENDIAN_BITFIELD
4847 uint64_t pkts : 32; /**< Number of packets processed by PIP */
4848 uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
4849 received by PIP per port */
4850 #else
4851 uint64_t raw : 32;
4852 uint64_t pkts : 32;
4853 #endif
4854 } s;
4855 struct cvmx_pip_stat2_prtx_s cn30xx;
4856 struct cvmx_pip_stat2_prtx_s cn31xx;
4857 struct cvmx_pip_stat2_prtx_s cn38xx;
4858 struct cvmx_pip_stat2_prtx_s cn38xxp2;
4859 struct cvmx_pip_stat2_prtx_s cn50xx;
4860 struct cvmx_pip_stat2_prtx_s cn52xx;
4861 struct cvmx_pip_stat2_prtx_s cn52xxp1;
4862 struct cvmx_pip_stat2_prtx_s cn56xx;
4863 struct cvmx_pip_stat2_prtx_s cn56xxp1;
4864 struct cvmx_pip_stat2_prtx_s cn58xx;
4865 struct cvmx_pip_stat2_prtx_s cn58xxp1;
4866 struct cvmx_pip_stat2_prtx_s cn61xx;
4867 struct cvmx_pip_stat2_prtx_s cn63xx;
4868 struct cvmx_pip_stat2_prtx_s cn63xxp1;
4869 struct cvmx_pip_stat2_prtx_s cn66xx;
4870 struct cvmx_pip_stat2_prtx_s cnf71xx;
4871 };
4872 typedef union cvmx_pip_stat2_prtx cvmx_pip_stat2_prtx_t;
4873
4874 /**
4875 * cvmx_pip_stat3_#
4876 *
4877 * PIP_STAT3_X = PIP_STAT_BCST / PIP_STAT_MCST
4878 *
4879 */
4880 union cvmx_pip_stat3_x {
4881 uint64_t u64;
4882 struct cvmx_pip_stat3_x_s {
4883 #ifdef __BIG_ENDIAN_BITFIELD
4884 uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets
4885 Does not include multicast packets
4886 Only includes packets whose parse mode is
4887 SKIP_TO_L2. */
4888 uint64_t mcst : 32; /**< Number of indentified L2 multicast packets
4889 Does not include broadcast packets
4890 Only includes packets whose parse mode is
4891 SKIP_TO_L2. */
4892 #else
4893 uint64_t mcst : 32;
4894 uint64_t bcst : 32;
4895 #endif
4896 } s;
4897 struct cvmx_pip_stat3_x_s cn68xx;
4898 struct cvmx_pip_stat3_x_s cn68xxp1;
4899 };
4900 typedef union cvmx_pip_stat3_x cvmx_pip_stat3_x_t;
4901
4902 /**
4903 * cvmx_pip_stat3_prt#
4904 *
4905 * PIP_STAT3_PRTX = PIP_STAT_BCST / PIP_STAT_MCST
4906 *
4907 */
4908 union cvmx_pip_stat3_prtx {
4909 uint64_t u64;
4910 struct cvmx_pip_stat3_prtx_s {
4911 #ifdef __BIG_ENDIAN_BITFIELD
4912 uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets
4913 Does not include multicast packets
4914 Only includes packets whose parse mode is
4915 SKIP_TO_L2. */
4916 uint64_t mcst : 32; /**< Number of indentified L2 multicast packets
4917 Does not include broadcast packets
4918 Only includes packets whose parse mode is
4919 SKIP_TO_L2. */
4920 #else
4921 uint64_t mcst : 32;
4922 uint64_t bcst : 32;
4923 #endif
4924 } s;
4925 struct cvmx_pip_stat3_prtx_s cn30xx;
4926 struct cvmx_pip_stat3_prtx_s cn31xx;
4927 struct cvmx_pip_stat3_prtx_s cn38xx;
4928 struct cvmx_pip_stat3_prtx_s cn38xxp2;
4929 struct cvmx_pip_stat3_prtx_s cn50xx;
4930 struct cvmx_pip_stat3_prtx_s cn52xx;
4931 struct cvmx_pip_stat3_prtx_s cn52xxp1;
4932 struct cvmx_pip_stat3_prtx_s cn56xx;
4933 struct cvmx_pip_stat3_prtx_s cn56xxp1;
4934 struct cvmx_pip_stat3_prtx_s cn58xx;
4935 struct cvmx_pip_stat3_prtx_s cn58xxp1;
4936 struct cvmx_pip_stat3_prtx_s cn61xx;
4937 struct cvmx_pip_stat3_prtx_s cn63xx;
4938 struct cvmx_pip_stat3_prtx_s cn63xxp1;
4939 struct cvmx_pip_stat3_prtx_s cn66xx;
4940 struct cvmx_pip_stat3_prtx_s cnf71xx;
4941 };
4942 typedef union cvmx_pip_stat3_prtx cvmx_pip_stat3_prtx_t;
4943
4944 /**
4945 * cvmx_pip_stat4_#
4946 *
4947 * PIP_STAT4_X = PIP_STAT_HIST1 / PIP_STAT_HIST0
4948 *
4949 */
4950 union cvmx_pip_stat4_x {
4951 uint64_t u64;
4952 struct cvmx_pip_stat4_x_s {
4953 #ifdef __BIG_ENDIAN_BITFIELD
4954 uint64_t h65to127 : 32; /**< Number of 65-127B packets */
4955 uint64_t h64 : 32; /**< Number of 1-64B packets */
4956 #else
4957 uint64_t h64 : 32;
4958 uint64_t h65to127 : 32;
4959 #endif
4960 } s;
4961 struct cvmx_pip_stat4_x_s cn68xx;
4962 struct cvmx_pip_stat4_x_s cn68xxp1;
4963 };
4964 typedef union cvmx_pip_stat4_x cvmx_pip_stat4_x_t;
4965
4966 /**
4967 * cvmx_pip_stat4_prt#
4968 *
4969 * PIP_STAT4_PRTX = PIP_STAT_HIST1 / PIP_STAT_HIST0
4970 *
4971 */
4972 union cvmx_pip_stat4_prtx {
4973 uint64_t u64;
4974 struct cvmx_pip_stat4_prtx_s {
4975 #ifdef __BIG_ENDIAN_BITFIELD
4976 uint64_t h65to127 : 32; /**< Number of 65-127B packets */
4977 uint64_t h64 : 32; /**< Number of 1-64B packets */
4978 #else
4979 uint64_t h64 : 32;
4980 uint64_t h65to127 : 32;
4981 #endif
4982 } s;
4983 struct cvmx_pip_stat4_prtx_s cn30xx;
4984 struct cvmx_pip_stat4_prtx_s cn31xx;
4985 struct cvmx_pip_stat4_prtx_s cn38xx;
4986 struct cvmx_pip_stat4_prtx_s cn38xxp2;
4987 struct cvmx_pip_stat4_prtx_s cn50xx;
4988 struct cvmx_pip_stat4_prtx_s cn52xx;
4989 struct cvmx_pip_stat4_prtx_s cn52xxp1;
4990 struct cvmx_pip_stat4_prtx_s cn56xx;
4991 struct cvmx_pip_stat4_prtx_s cn56xxp1;
4992 struct cvmx_pip_stat4_prtx_s cn58xx;
4993 struct cvmx_pip_stat4_prtx_s cn58xxp1;
4994 struct cvmx_pip_stat4_prtx_s cn61xx;
4995 struct cvmx_pip_stat4_prtx_s cn63xx;
4996 struct cvmx_pip_stat4_prtx_s cn63xxp1;
4997 struct cvmx_pip_stat4_prtx_s cn66xx;
4998 struct cvmx_pip_stat4_prtx_s cnf71xx;
4999 };
5000 typedef union cvmx_pip_stat4_prtx cvmx_pip_stat4_prtx_t;
5001
5002 /**
5003 * cvmx_pip_stat5_#
5004 *
5005 * PIP_STAT5_X = PIP_STAT_HIST3 / PIP_STAT_HIST2
5006 *
5007 */
5008 union cvmx_pip_stat5_x {
5009 uint64_t u64;
5010 struct cvmx_pip_stat5_x_s {
5011 #ifdef __BIG_ENDIAN_BITFIELD
5012 uint64_t h256to511 : 32; /**< Number of 256-511B packets */
5013 uint64_t h128to255 : 32; /**< Number of 128-255B packets */
5014 #else
5015 uint64_t h128to255 : 32;
5016 uint64_t h256to511 : 32;
5017 #endif
5018 } s;
5019 struct cvmx_pip_stat5_x_s cn68xx;
5020 struct cvmx_pip_stat5_x_s cn68xxp1;
5021 };
5022 typedef union cvmx_pip_stat5_x cvmx_pip_stat5_x_t;
5023
5024 /**
5025 * cvmx_pip_stat5_prt#
5026 *
5027 * PIP_STAT5_PRTX = PIP_STAT_HIST3 / PIP_STAT_HIST2
5028 *
5029 */
5030 union cvmx_pip_stat5_prtx {
5031 uint64_t u64;
5032 struct cvmx_pip_stat5_prtx_s {
5033 #ifdef __BIG_ENDIAN_BITFIELD
5034 uint64_t h256to511 : 32; /**< Number of 256-511B packets */
5035 uint64_t h128to255 : 32; /**< Number of 128-255B packets */
5036 #else
5037 uint64_t h128to255 : 32;
5038 uint64_t h256to511 : 32;
5039 #endif
5040 } s;
5041 struct cvmx_pip_stat5_prtx_s cn30xx;
5042 struct cvmx_pip_stat5_prtx_s cn31xx;
5043 struct cvmx_pip_stat5_prtx_s cn38xx;
5044 struct cvmx_pip_stat5_prtx_s cn38xxp2;
5045 struct cvmx_pip_stat5_prtx_s cn50xx;
5046 struct cvmx_pip_stat5_prtx_s cn52xx;
5047 struct cvmx_pip_stat5_prtx_s cn52xxp1;
5048 struct cvmx_pip_stat5_prtx_s cn56xx;
5049 struct cvmx_pip_stat5_prtx_s cn56xxp1;
5050 struct cvmx_pip_stat5_prtx_s cn58xx;
5051 struct cvmx_pip_stat5_prtx_s cn58xxp1;
5052 struct cvmx_pip_stat5_prtx_s cn61xx;
5053 struct cvmx_pip_stat5_prtx_s cn63xx;
5054 struct cvmx_pip_stat5_prtx_s cn63xxp1;
5055 struct cvmx_pip_stat5_prtx_s cn66xx;
5056 struct cvmx_pip_stat5_prtx_s cnf71xx;
5057 };
5058 typedef union cvmx_pip_stat5_prtx cvmx_pip_stat5_prtx_t;
5059
5060 /**
5061 * cvmx_pip_stat6_#
5062 *
5063 * PIP_STAT6_X = PIP_STAT_HIST5 / PIP_STAT_HIST4
5064 *
5065 */
5066 union cvmx_pip_stat6_x {
5067 uint64_t u64;
5068 struct cvmx_pip_stat6_x_s {
5069 #ifdef __BIG_ENDIAN_BITFIELD
5070 uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */
5071 uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */
5072 #else
5073 uint64_t h512to1023 : 32;
5074 uint64_t h1024to1518 : 32;
5075 #endif
5076 } s;
5077 struct cvmx_pip_stat6_x_s cn68xx;
5078 struct cvmx_pip_stat6_x_s cn68xxp1;
5079 };
5080 typedef union cvmx_pip_stat6_x cvmx_pip_stat6_x_t;
5081
5082 /**
5083 * cvmx_pip_stat6_prt#
5084 *
5085 * PIP_STAT6_PRTX = PIP_STAT_HIST5 / PIP_STAT_HIST4
5086 *
5087 */
5088 union cvmx_pip_stat6_prtx {
5089 uint64_t u64;
5090 struct cvmx_pip_stat6_prtx_s {
5091 #ifdef __BIG_ENDIAN_BITFIELD
5092 uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */
5093 uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */
5094 #else
5095 uint64_t h512to1023 : 32;
5096 uint64_t h1024to1518 : 32;
5097 #endif
5098 } s;
5099 struct cvmx_pip_stat6_prtx_s cn30xx;
5100 struct cvmx_pip_stat6_prtx_s cn31xx;
5101 struct cvmx_pip_stat6_prtx_s cn38xx;
5102 struct cvmx_pip_stat6_prtx_s cn38xxp2;
5103 struct cvmx_pip_stat6_prtx_s cn50xx;
5104 struct cvmx_pip_stat6_prtx_s cn52xx;
5105 struct cvmx_pip_stat6_prtx_s cn52xxp1;
5106 struct cvmx_pip_stat6_prtx_s cn56xx;
5107 struct cvmx_pip_stat6_prtx_s cn56xxp1;
5108 struct cvmx_pip_stat6_prtx_s cn58xx;
5109 struct cvmx_pip_stat6_prtx_s cn58xxp1;
5110 struct cvmx_pip_stat6_prtx_s cn61xx;
5111 struct cvmx_pip_stat6_prtx_s cn63xx;
5112 struct cvmx_pip_stat6_prtx_s cn63xxp1;
5113 struct cvmx_pip_stat6_prtx_s cn66xx;
5114 struct cvmx_pip_stat6_prtx_s cnf71xx;
5115 };
5116 typedef union cvmx_pip_stat6_prtx cvmx_pip_stat6_prtx_t;
5117
5118 /**
5119 * cvmx_pip_stat7_#
5120 *
5121 * PIP_STAT7_X = PIP_STAT_FCS / PIP_STAT_HIST6
5122 *
5123 */
5124 union cvmx_pip_stat7_x {
5125 uint64_t u64;
5126 struct cvmx_pip_stat7_x_s {
5127 #ifdef __BIG_ENDIAN_BITFIELD
5128 uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */
5129 uint64_t h1519 : 32; /**< Number of 1519-max packets */
5130 #else
5131 uint64_t h1519 : 32;
5132 uint64_t fcs : 32;
5133 #endif
5134 } s;
5135 struct cvmx_pip_stat7_x_s cn68xx;
5136 struct cvmx_pip_stat7_x_s cn68xxp1;
5137 };
5138 typedef union cvmx_pip_stat7_x cvmx_pip_stat7_x_t;
5139
5140 /**
5141 * cvmx_pip_stat7_prt#
5142 *
5143 * PIP_STAT7_PRTX = PIP_STAT_FCS / PIP_STAT_HIST6
5144 *
5145 *
5146 * Notes:
5147 * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35
5148 * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47
5149 */
5150 union cvmx_pip_stat7_prtx {
5151 uint64_t u64;
5152 struct cvmx_pip_stat7_prtx_s {
5153 #ifdef __BIG_ENDIAN_BITFIELD
5154 uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */
5155 uint64_t h1519 : 32; /**< Number of 1519-max packets */
5156 #else
5157 uint64_t h1519 : 32;
5158 uint64_t fcs : 32;
5159 #endif
5160 } s;
5161 struct cvmx_pip_stat7_prtx_s cn30xx;
5162 struct cvmx_pip_stat7_prtx_s cn31xx;
5163 struct cvmx_pip_stat7_prtx_s cn38xx;
5164 struct cvmx_pip_stat7_prtx_s cn38xxp2;
5165 struct cvmx_pip_stat7_prtx_s cn50xx;
5166 struct cvmx_pip_stat7_prtx_s cn52xx;
5167 struct cvmx_pip_stat7_prtx_s cn52xxp1;
5168 struct cvmx_pip_stat7_prtx_s cn56xx;
5169 struct cvmx_pip_stat7_prtx_s cn56xxp1;
5170 struct cvmx_pip_stat7_prtx_s cn58xx;
5171 struct cvmx_pip_stat7_prtx_s cn58xxp1;
5172 struct cvmx_pip_stat7_prtx_s cn61xx;
5173 struct cvmx_pip_stat7_prtx_s cn63xx;
5174 struct cvmx_pip_stat7_prtx_s cn63xxp1;
5175 struct cvmx_pip_stat7_prtx_s cn66xx;
5176 struct cvmx_pip_stat7_prtx_s cnf71xx;
5177 };
5178 typedef union cvmx_pip_stat7_prtx cvmx_pip_stat7_prtx_t;
5179
5180 /**
5181 * cvmx_pip_stat8_#
5182 *
5183 * PIP_STAT8_X = PIP_STAT_FRAG / PIP_STAT_UNDER
5184 *
5185 */
5186 union cvmx_pip_stat8_x {
5187 uint64_t u64;
5188 struct cvmx_pip_stat8_x_s {
5189 #ifdef __BIG_ENDIAN_BITFIELD
5190 uint64_t frag : 32; /**< Number of packets with length < min and FCS error */
5191 uint64_t undersz : 32; /**< Number of packets with length < min */
5192 #else
5193 uint64_t undersz : 32;
5194 uint64_t frag : 32;
5195 #endif
5196 } s;
5197 struct cvmx_pip_stat8_x_s cn68xx;
5198 struct cvmx_pip_stat8_x_s cn68xxp1;
5199 };
5200 typedef union cvmx_pip_stat8_x cvmx_pip_stat8_x_t;
5201
5202 /**
5203 * cvmx_pip_stat8_prt#
5204 *
5205 * PIP_STAT8_PRTX = PIP_STAT_FRAG / PIP_STAT_UNDER
5206 *
5207 *
5208 * Notes:
5209 * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35
5210 * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47
5211 */
5212 union cvmx_pip_stat8_prtx {
5213 uint64_t u64;
5214 struct cvmx_pip_stat8_prtx_s {
5215 #ifdef __BIG_ENDIAN_BITFIELD
5216 uint64_t frag : 32; /**< Number of packets with length < min and FCS error */
5217 uint64_t undersz : 32; /**< Number of packets with length < min */
5218 #else
5219 uint64_t undersz : 32;
5220 uint64_t frag : 32;
5221 #endif
5222 } s;
5223 struct cvmx_pip_stat8_prtx_s cn30xx;
5224 struct cvmx_pip_stat8_prtx_s cn31xx;
5225 struct cvmx_pip_stat8_prtx_s cn38xx;
5226 struct cvmx_pip_stat8_prtx_s cn38xxp2;
5227 struct cvmx_pip_stat8_prtx_s cn50xx;
5228 struct cvmx_pip_stat8_prtx_s cn52xx;
5229 struct cvmx_pip_stat8_prtx_s cn52xxp1;
5230 struct cvmx_pip_stat8_prtx_s cn56xx;
5231 struct cvmx_pip_stat8_prtx_s cn56xxp1;
5232 struct cvmx_pip_stat8_prtx_s cn58xx;
5233 struct cvmx_pip_stat8_prtx_s cn58xxp1;
5234 struct cvmx_pip_stat8_prtx_s cn61xx;
5235 struct cvmx_pip_stat8_prtx_s cn63xx;
5236 struct cvmx_pip_stat8_prtx_s cn63xxp1;
5237 struct cvmx_pip_stat8_prtx_s cn66xx;
5238 struct cvmx_pip_stat8_prtx_s cnf71xx;
5239 };
5240 typedef union cvmx_pip_stat8_prtx cvmx_pip_stat8_prtx_t;
5241
5242 /**
5243 * cvmx_pip_stat9_#
5244 *
5245 * PIP_STAT9_X = PIP_STAT_JABBER / PIP_STAT_OVER
5246 *
5247 */
5248 union cvmx_pip_stat9_x {
5249 uint64_t u64;
5250 struct cvmx_pip_stat9_x_s {
5251 #ifdef __BIG_ENDIAN_BITFIELD
5252 uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */
5253 uint64_t oversz : 32; /**< Number of packets with length > max */
5254 #else
5255 uint64_t oversz : 32;
5256 uint64_t jabber : 32;
5257 #endif
5258 } s;
5259 struct cvmx_pip_stat9_x_s cn68xx;
5260 struct cvmx_pip_stat9_x_s cn68xxp1;
5261 };
5262 typedef union cvmx_pip_stat9_x cvmx_pip_stat9_x_t;
5263
5264 /**
5265 * cvmx_pip_stat9_prt#
5266 *
5267 * PIP_STAT9_PRTX = PIP_STAT_JABBER / PIP_STAT_OVER
5268 *
5269 *
5270 * Notes:
5271 * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35
5272 * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors
5273 * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions
5274 */
5275 union cvmx_pip_stat9_prtx {
5276 uint64_t u64;
5277 struct cvmx_pip_stat9_prtx_s {
5278 #ifdef __BIG_ENDIAN_BITFIELD
5279 uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */
5280 uint64_t oversz : 32; /**< Number of packets with length > max */
5281 #else
5282 uint64_t oversz : 32;
5283 uint64_t jabber : 32;
5284 #endif
5285 } s;
5286 struct cvmx_pip_stat9_prtx_s cn30xx;
5287 struct cvmx_pip_stat9_prtx_s cn31xx;
5288 struct cvmx_pip_stat9_prtx_s cn38xx;
5289 struct cvmx_pip_stat9_prtx_s cn38xxp2;
5290 struct cvmx_pip_stat9_prtx_s cn50xx;
5291 struct cvmx_pip_stat9_prtx_s cn52xx;
5292 struct cvmx_pip_stat9_prtx_s cn52xxp1;
5293 struct cvmx_pip_stat9_prtx_s cn56xx;
5294 struct cvmx_pip_stat9_prtx_s cn56xxp1;
5295 struct cvmx_pip_stat9_prtx_s cn58xx;
5296 struct cvmx_pip_stat9_prtx_s cn58xxp1;
5297 struct cvmx_pip_stat9_prtx_s cn61xx;
5298 struct cvmx_pip_stat9_prtx_s cn63xx;
5299 struct cvmx_pip_stat9_prtx_s cn63xxp1;
5300 struct cvmx_pip_stat9_prtx_s cn66xx;
5301 struct cvmx_pip_stat9_prtx_s cnf71xx;
5302 };
5303 typedef union cvmx_pip_stat9_prtx cvmx_pip_stat9_prtx_t;
5304
5305 /**
5306 * cvmx_pip_stat_ctl
5307 *
5308 * PIP_STAT_CTL = PIP's Stat Control Register
5309 *
5310 * Controls how the PIP statistics counters are handled.
5311 */
5312 union cvmx_pip_stat_ctl {
5313 uint64_t u64;
5314 struct cvmx_pip_stat_ctl_s {
5315 #ifdef __BIG_ENDIAN_BITFIELD
5316 uint64_t reserved_9_63 : 55;
5317 uint64_t mode : 1; /**< The PIP_STAT*_X registers can be indexed either by
5318 port-kind or backpressure ID.
5319 Does not apply to the PIP_STAT_INB* registers.
5320 0 = X represents the packet's port-kind
5321 1 = X represents the packet's backpressure ID */
5322 uint64_t reserved_1_7 : 7;
5323 uint64_t rdclr : 1; /**< Stat registers are read and clear
5324 0 = stat registers hold value when read
5325 1 = stat registers are cleared when read */
5326 #else
5327 uint64_t rdclr : 1;
5328 uint64_t reserved_1_7 : 7;
5329 uint64_t mode : 1;
5330 uint64_t reserved_9_63 : 55;
5331 #endif
5332 } s;
5333 struct cvmx_pip_stat_ctl_cn30xx {
5334 #ifdef __BIG_ENDIAN_BITFIELD
5335 uint64_t reserved_1_63 : 63;
5336 uint64_t rdclr : 1; /**< Stat registers are read and clear
5337 0 = stat registers hold value when read
5338 1 = stat registers are cleared when read */
5339 #else
5340 uint64_t rdclr : 1;
5341 uint64_t reserved_1_63 : 63;
5342 #endif
5343 } cn30xx;
5344 struct cvmx_pip_stat_ctl_cn30xx cn31xx;
5345 struct cvmx_pip_stat_ctl_cn30xx cn38xx;
5346 struct cvmx_pip_stat_ctl_cn30xx cn38xxp2;
5347 struct cvmx_pip_stat_ctl_cn30xx cn50xx;
5348 struct cvmx_pip_stat_ctl_cn30xx cn52xx;
5349 struct cvmx_pip_stat_ctl_cn30xx cn52xxp1;
5350 struct cvmx_pip_stat_ctl_cn30xx cn56xx;
5351 struct cvmx_pip_stat_ctl_cn30xx cn56xxp1;
5352 struct cvmx_pip_stat_ctl_cn30xx cn58xx;
5353 struct cvmx_pip_stat_ctl_cn30xx cn58xxp1;
5354 struct cvmx_pip_stat_ctl_cn30xx cn61xx;
5355 struct cvmx_pip_stat_ctl_cn30xx cn63xx;
5356 struct cvmx_pip_stat_ctl_cn30xx cn63xxp1;
5357 struct cvmx_pip_stat_ctl_cn30xx cn66xx;
5358 struct cvmx_pip_stat_ctl_s cn68xx;
5359 struct cvmx_pip_stat_ctl_s cn68xxp1;
5360 struct cvmx_pip_stat_ctl_cn30xx cnf71xx;
5361 };
5362 typedef union cvmx_pip_stat_ctl cvmx_pip_stat_ctl_t;
5363
5364 /**
5365 * cvmx_pip_stat_inb_errs#
5366 *
5367 * PIP_STAT_INB_ERRSX = Inbound error packets received by PIP per port
5368 *
5369 * Inbound stats collect all data sent to PIP from all packet interfaces.
5370 * Its the raw counts of everything that comes into the block. The counts
5371 * will reflect all error packets and packets dropped by the PKI RED engine.
5372 * These counts are intended for system debug, but could convey useful
5373 * information in production systems.
5374 */
5375 union cvmx_pip_stat_inb_errsx {
5376 uint64_t u64;
5377 struct cvmx_pip_stat_inb_errsx_s {
5378 #ifdef __BIG_ENDIAN_BITFIELD
5379 uint64_t reserved_16_63 : 48;
5380 uint64_t errs : 16; /**< Number of packets with errors
5381 received by PIP */
5382 #else
5383 uint64_t errs : 16;
5384 uint64_t reserved_16_63 : 48;
5385 #endif
5386 } s;
5387 struct cvmx_pip_stat_inb_errsx_s cn30xx;
5388 struct cvmx_pip_stat_inb_errsx_s cn31xx;
5389 struct cvmx_pip_stat_inb_errsx_s cn38xx;
5390 struct cvmx_pip_stat_inb_errsx_s cn38xxp2;
5391 struct cvmx_pip_stat_inb_errsx_s cn50xx;
5392 struct cvmx_pip_stat_inb_errsx_s cn52xx;
5393 struct cvmx_pip_stat_inb_errsx_s cn52xxp1;
5394 struct cvmx_pip_stat_inb_errsx_s cn56xx;
5395 struct cvmx_pip_stat_inb_errsx_s cn56xxp1;
5396 struct cvmx_pip_stat_inb_errsx_s cn58xx;
5397 struct cvmx_pip_stat_inb_errsx_s cn58xxp1;
5398 struct cvmx_pip_stat_inb_errsx_s cn61xx;
5399 struct cvmx_pip_stat_inb_errsx_s cn63xx;
5400 struct cvmx_pip_stat_inb_errsx_s cn63xxp1;
5401 struct cvmx_pip_stat_inb_errsx_s cn66xx;
5402 struct cvmx_pip_stat_inb_errsx_s cnf71xx;
5403 };
5404 typedef union cvmx_pip_stat_inb_errsx cvmx_pip_stat_inb_errsx_t;
5405
5406 /**
5407 * cvmx_pip_stat_inb_errs_pknd#
5408 *
5409 * PIP_STAT_INB_ERRS_PKNDX = Inbound error packets received by PIP per pkind
5410 *
5411 * Inbound stats collect all data sent to PIP from all packet interfaces.
5412 * Its the raw counts of everything that comes into the block. The counts
5413 * will reflect all error packets and packets dropped by the PKI RED engine.
5414 * These counts are intended for system debug, but could convey useful
5415 * information in production systems.
5416 */
5417 union cvmx_pip_stat_inb_errs_pkndx {
5418 uint64_t u64;
5419 struct cvmx_pip_stat_inb_errs_pkndx_s {
5420 #ifdef __BIG_ENDIAN_BITFIELD
5421 uint64_t reserved_16_63 : 48;
5422 uint64_t errs : 16; /**< Number of packets with errors
5423 received by PIP */
5424 #else
5425 uint64_t errs : 16;
5426 uint64_t reserved_16_63 : 48;
5427 #endif
5428 } s;
5429 struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx;
5430 struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1;
5431 };
5432 typedef union cvmx_pip_stat_inb_errs_pkndx cvmx_pip_stat_inb_errs_pkndx_t;
5433
5434 /**
5435 * cvmx_pip_stat_inb_octs#
5436 *
5437 * PIP_STAT_INB_OCTSX = Inbound octets received by PIP per port
5438 *
5439 * Inbound stats collect all data sent to PIP from all packet interfaces.
5440 * Its the raw counts of everything that comes into the block. The counts
5441 * will reflect all error packets and packets dropped by the PKI RED engine.
5442 * These counts are intended for system debug, but could convey useful
5443 * information in production systems. The OCTS will include the bytes from
5444 * timestamp fields in PTP_MODE.
5445 */
5446 union cvmx_pip_stat_inb_octsx {
5447 uint64_t u64;
5448 struct cvmx_pip_stat_inb_octsx_s {
5449 #ifdef __BIG_ENDIAN_BITFIELD
5450 uint64_t reserved_48_63 : 16;
5451 uint64_t octs : 48; /**< Total number of octets from all packets received
5452 by PIP */
5453 #else
5454 uint64_t octs : 48;
5455 uint64_t reserved_48_63 : 16;
5456 #endif
5457 } s;
5458 struct cvmx_pip_stat_inb_octsx_s cn30xx;
5459 struct cvmx_pip_stat_inb_octsx_s cn31xx;
5460 struct cvmx_pip_stat_inb_octsx_s cn38xx;
5461 struct cvmx_pip_stat_inb_octsx_s cn38xxp2;
5462 struct cvmx_pip_stat_inb_octsx_s cn50xx;
5463 struct cvmx_pip_stat_inb_octsx_s cn52xx;
5464 struct cvmx_pip_stat_inb_octsx_s cn52xxp1;
5465 struct cvmx_pip_stat_inb_octsx_s cn56xx;
5466 struct cvmx_pip_stat_inb_octsx_s cn56xxp1;
5467 struct cvmx_pip_stat_inb_octsx_s cn58xx;
5468 struct cvmx_pip_stat_inb_octsx_s cn58xxp1;
5469 struct cvmx_pip_stat_inb_octsx_s cn61xx;
5470 struct cvmx_pip_stat_inb_octsx_s cn63xx;
5471 struct cvmx_pip_stat_inb_octsx_s cn63xxp1;
5472 struct cvmx_pip_stat_inb_octsx_s cn66xx;
5473 struct cvmx_pip_stat_inb_octsx_s cnf71xx;
5474 };
5475 typedef union cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_octsx_t;
5476
5477 /**
5478 * cvmx_pip_stat_inb_octs_pknd#
5479 *
5480 * PIP_STAT_INB_OCTS_PKNDX = Inbound octets received by PIP per pkind
5481 *
5482 * Inbound stats collect all data sent to PIP from all packet interfaces.
5483 * Its the raw counts of everything that comes into the block. The counts
5484 * will reflect all error packets and packets dropped by the PKI RED engine.
5485 * These counts are intended for system debug, but could convey useful
5486 * information in production systems. The OCTS will include the bytes from
5487 * timestamp fields in PTP_MODE.
5488 */
5489 union cvmx_pip_stat_inb_octs_pkndx {
5490 uint64_t u64;
5491 struct cvmx_pip_stat_inb_octs_pkndx_s {
5492 #ifdef __BIG_ENDIAN_BITFIELD
5493 uint64_t reserved_48_63 : 16;
5494 uint64_t octs : 48; /**< Total number of octets from all packets received
5495 by PIP */
5496 #else
5497 uint64_t octs : 48;
5498 uint64_t reserved_48_63 : 16;
5499 #endif
5500 } s;
5501 struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx;
5502 struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1;
5503 };
5504 typedef union cvmx_pip_stat_inb_octs_pkndx cvmx_pip_stat_inb_octs_pkndx_t;
5505
5506 /**
5507 * cvmx_pip_stat_inb_pkts#
5508 *
5509 * PIP_STAT_INB_PKTSX = Inbound packets received by PIP per port
5510 *
5511 * Inbound stats collect all data sent to PIP from all packet interfaces.
5512 * Its the raw counts of everything that comes into the block. The counts
5513 * will reflect all error packets and packets dropped by the PKI RED engine.
5514 * These counts are intended for system debug, but could convey useful
5515 * information in production systems.
5516 */
5517 union cvmx_pip_stat_inb_pktsx {
5518 uint64_t u64;
5519 struct cvmx_pip_stat_inb_pktsx_s {
5520 #ifdef __BIG_ENDIAN_BITFIELD
5521 uint64_t reserved_32_63 : 32;
5522 uint64_t pkts : 32; /**< Number of packets without errors
5523 received by PIP */
5524 #else
5525 uint64_t pkts : 32;
5526 uint64_t reserved_32_63 : 32;
5527 #endif
5528 } s;
5529 struct cvmx_pip_stat_inb_pktsx_s cn30xx;
5530 struct cvmx_pip_stat_inb_pktsx_s cn31xx;
5531 struct cvmx_pip_stat_inb_pktsx_s cn38xx;
5532 struct cvmx_pip_stat_inb_pktsx_s cn38xxp2;
5533 struct cvmx_pip_stat_inb_pktsx_s cn50xx;
5534 struct cvmx_pip_stat_inb_pktsx_s cn52xx;
5535 struct cvmx_pip_stat_inb_pktsx_s cn52xxp1;
5536 struct cvmx_pip_stat_inb_pktsx_s cn56xx;
5537 struct cvmx_pip_stat_inb_pktsx_s cn56xxp1;
5538 struct cvmx_pip_stat_inb_pktsx_s cn58xx;
5539 struct cvmx_pip_stat_inb_pktsx_s cn58xxp1;
5540 struct cvmx_pip_stat_inb_pktsx_s cn61xx;
5541 struct cvmx_pip_stat_inb_pktsx_s cn63xx;
5542 struct cvmx_pip_stat_inb_pktsx_s cn63xxp1;
5543 struct cvmx_pip_stat_inb_pktsx_s cn66xx;
5544 struct cvmx_pip_stat_inb_pktsx_s cnf71xx;
5545 };
5546 typedef union cvmx_pip_stat_inb_pktsx cvmx_pip_stat_inb_pktsx_t;
5547
5548 /**
5549 * cvmx_pip_stat_inb_pkts_pknd#
5550 *
5551 * PIP_STAT_INB_PKTS_PKNDX = Inbound packets received by PIP per pkind
5552 *
5553 * Inbound stats collect all data sent to PIP from all packet interfaces.
5554 * Its the raw counts of everything that comes into the block. The counts
5555 * will reflect all error packets and packets dropped by the PKI RED engine.
5556 * These counts are intended for system debug, but could convey useful
5557 * information in production systems.
5558 */
5559 union cvmx_pip_stat_inb_pkts_pkndx {
5560 uint64_t u64;
5561 struct cvmx_pip_stat_inb_pkts_pkndx_s {
5562 #ifdef __BIG_ENDIAN_BITFIELD
5563 uint64_t reserved_32_63 : 32;
5564 uint64_t pkts : 32; /**< Number of packets without errors
5565 received by PIP */
5566 #else
5567 uint64_t pkts : 32;
5568 uint64_t reserved_32_63 : 32;
5569 #endif
5570 } s;
5571 struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx;
5572 struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1;
5573 };
5574 typedef union cvmx_pip_stat_inb_pkts_pkndx cvmx_pip_stat_inb_pkts_pkndx_t;
5575
5576 /**
5577 * cvmx_pip_sub_pkind_fcs#
5578 */
5579 union cvmx_pip_sub_pkind_fcsx {
5580 uint64_t u64;
5581 struct cvmx_pip_sub_pkind_fcsx_s {
5582 #ifdef __BIG_ENDIAN_BITFIELD
5583 uint64_t port_bit : 64; /**< When set '1', the pkind corresponding to the bit
5584 position set, will subtract the FCS for packets
5585 on that pkind. */
5586 #else
5587 uint64_t port_bit : 64;
5588 #endif
5589 } s;
5590 struct cvmx_pip_sub_pkind_fcsx_s cn68xx;
5591 struct cvmx_pip_sub_pkind_fcsx_s cn68xxp1;
5592 };
5593 typedef union cvmx_pip_sub_pkind_fcsx cvmx_pip_sub_pkind_fcsx_t;
5594
5595 /**
5596 * cvmx_pip_tag_inc#
5597 *
5598 * PIP_TAG_INC = Which bytes to include in the new tag hash algorithm
5599 *
5600 * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask)
5601 */
5602 union cvmx_pip_tag_incx {
5603 uint64_t u64;
5604 struct cvmx_pip_tag_incx_s {
5605 #ifdef __BIG_ENDIAN_BITFIELD
5606 uint64_t reserved_8_63 : 56;
5607 uint64_t en : 8; /**< Which bytes to include in mask tag algorithm
5608 Broken into 4, 16-entry masks to cover 128B
5609 PIP_PRT_CFG[TAG_INC] selects 1 of 4 to use
5610 registers 0-15 map to PIP_PRT_CFG[TAG_INC] == 0
5611 registers 16-31 map to PIP_PRT_CFG[TAG_INC] == 1
5612 registers 32-47 map to PIP_PRT_CFG[TAG_INC] == 2
5613 registers 48-63 map to PIP_PRT_CFG[TAG_INC] == 3
5614 [7] coresponds to the MSB of the 8B word
5615 [0] coresponds to the LSB of the 8B word
5616 If PTP_MODE, the 8B timestamp is prepended to the
5617 packet. The EN byte masks should be adjusted to
5618 compensate for the additional timestamp field. */
5619 #else
5620 uint64_t en : 8;
5621 uint64_t reserved_8_63 : 56;
5622 #endif
5623 } s;
5624 struct cvmx_pip_tag_incx_s cn30xx;
5625 struct cvmx_pip_tag_incx_s cn31xx;
5626 struct cvmx_pip_tag_incx_s cn38xx;
5627 struct cvmx_pip_tag_incx_s cn38xxp2;
5628 struct cvmx_pip_tag_incx_s cn50xx;
5629 struct cvmx_pip_tag_incx_s cn52xx;
5630 struct cvmx_pip_tag_incx_s cn52xxp1;
5631 struct cvmx_pip_tag_incx_s cn56xx;
5632 struct cvmx_pip_tag_incx_s cn56xxp1;
5633 struct cvmx_pip_tag_incx_s cn58xx;
5634 struct cvmx_pip_tag_incx_s cn58xxp1;
5635 struct cvmx_pip_tag_incx_s cn61xx;
5636 struct cvmx_pip_tag_incx_s cn63xx;
5637 struct cvmx_pip_tag_incx_s cn63xxp1;
5638 struct cvmx_pip_tag_incx_s cn66xx;
5639 struct cvmx_pip_tag_incx_s cn68xx;
5640 struct cvmx_pip_tag_incx_s cn68xxp1;
5641 struct cvmx_pip_tag_incx_s cnf71xx;
5642 };
5643 typedef union cvmx_pip_tag_incx cvmx_pip_tag_incx_t;
5644
5645 /**
5646 * cvmx_pip_tag_mask
5647 *
5648 * PIP_TAG_MASK = Mask bit in the tag generation
5649 *
5650 */
5651 union cvmx_pip_tag_mask {
5652 uint64_t u64;
5653 struct cvmx_pip_tag_mask_s {
5654 #ifdef __BIG_ENDIAN_BITFIELD
5655 uint64_t reserved_16_63 : 48;
5656 uint64_t mask : 16; /**< When set, MASK clears individual bits of lower 16
5657 bits of the computed tag. Does not effect RAW
5658 or INSTR HDR packets. */
5659 #else
5660 uint64_t mask : 16;
5661 uint64_t reserved_16_63 : 48;
5662 #endif
5663 } s;
5664 struct cvmx_pip_tag_mask_s cn30xx;
5665 struct cvmx_pip_tag_mask_s cn31xx;
5666 struct cvmx_pip_tag_mask_s cn38xx;
5667 struct cvmx_pip_tag_mask_s cn38xxp2;
5668 struct cvmx_pip_tag_mask_s cn50xx;
5669 struct cvmx_pip_tag_mask_s cn52xx;
5670 struct cvmx_pip_tag_mask_s cn52xxp1;
5671 struct cvmx_pip_tag_mask_s cn56xx;
5672 struct cvmx_pip_tag_mask_s cn56xxp1;
5673 struct cvmx_pip_tag_mask_s cn58xx;
5674 struct cvmx_pip_tag_mask_s cn58xxp1;
5675 struct cvmx_pip_tag_mask_s cn61xx;
5676 struct cvmx_pip_tag_mask_s cn63xx;
5677 struct cvmx_pip_tag_mask_s cn63xxp1;
5678 struct cvmx_pip_tag_mask_s cn66xx;
5679 struct cvmx_pip_tag_mask_s cn68xx;
5680 struct cvmx_pip_tag_mask_s cn68xxp1;
5681 struct cvmx_pip_tag_mask_s cnf71xx;
5682 };
5683 typedef union cvmx_pip_tag_mask cvmx_pip_tag_mask_t;
5684
5685 /**
5686 * cvmx_pip_tag_secret
5687 *
5688 * PIP_TAG_SECRET = Initial value in tag generation
5689 *
5690 * The source and destination IV's provide a mechanism for each Octeon to be unique.
5691 */
5692 union cvmx_pip_tag_secret {
5693 uint64_t u64;
5694 struct cvmx_pip_tag_secret_s {
5695 #ifdef __BIG_ENDIAN_BITFIELD
5696 uint64_t reserved_32_63 : 32;
5697 uint64_t dst : 16; /**< Secret for the destination tuple tag CRC calc */
5698 uint64_t src : 16; /**< Secret for the source tuple tag CRC calc */
5699 #else
5700 uint64_t src : 16;
5701 uint64_t dst : 16;
5702 uint64_t reserved_32_63 : 32;
5703 #endif
5704 } s;
5705 struct cvmx_pip_tag_secret_s cn30xx;
5706 struct cvmx_pip_tag_secret_s cn31xx;
5707 struct cvmx_pip_tag_secret_s cn38xx;
5708 struct cvmx_pip_tag_secret_s cn38xxp2;
5709 struct cvmx_pip_tag_secret_s cn50xx;
5710 struct cvmx_pip_tag_secret_s cn52xx;
5711 struct cvmx_pip_tag_secret_s cn52xxp1;
5712 struct cvmx_pip_tag_secret_s cn56xx;
5713 struct cvmx_pip_tag_secret_s cn56xxp1;
5714 struct cvmx_pip_tag_secret_s cn58xx;
5715 struct cvmx_pip_tag_secret_s cn58xxp1;
5716 struct cvmx_pip_tag_secret_s cn61xx;
5717 struct cvmx_pip_tag_secret_s cn63xx;
5718 struct cvmx_pip_tag_secret_s cn63xxp1;
5719 struct cvmx_pip_tag_secret_s cn66xx;
5720 struct cvmx_pip_tag_secret_s cn68xx;
5721 struct cvmx_pip_tag_secret_s cn68xxp1;
5722 struct cvmx_pip_tag_secret_s cnf71xx;
5723 };
5724 typedef union cvmx_pip_tag_secret cvmx_pip_tag_secret_t;
5725
5726 /**
5727 * cvmx_pip_todo_entry
5728 *
5729 * PIP_TODO_ENTRY = Head entry of the Todo list (debug only)
5730 *
5731 * Summary of the current packet that has completed and waiting to be processed
5732 */
5733 union cvmx_pip_todo_entry {
5734 uint64_t u64;
5735 struct cvmx_pip_todo_entry_s {
5736 #ifdef __BIG_ENDIAN_BITFIELD
5737 uint64_t val : 1; /**< Entry is valid */
5738 uint64_t reserved_62_62 : 1;
5739 uint64_t entry : 62; /**< Todo list entry summary */
5740 #else
5741 uint64_t entry : 62;
5742 uint64_t reserved_62_62 : 1;
5743 uint64_t val : 1;
5744 #endif
5745 } s;
5746 struct cvmx_pip_todo_entry_s cn30xx;
5747 struct cvmx_pip_todo_entry_s cn31xx;
5748 struct cvmx_pip_todo_entry_s cn38xx;
5749 struct cvmx_pip_todo_entry_s cn38xxp2;
5750 struct cvmx_pip_todo_entry_s cn50xx;
5751 struct cvmx_pip_todo_entry_s cn52xx;
5752 struct cvmx_pip_todo_entry_s cn52xxp1;
5753 struct cvmx_pip_todo_entry_s cn56xx;
5754 struct cvmx_pip_todo_entry_s cn56xxp1;
5755 struct cvmx_pip_todo_entry_s cn58xx;
5756 struct cvmx_pip_todo_entry_s cn58xxp1;
5757 struct cvmx_pip_todo_entry_s cn61xx;
5758 struct cvmx_pip_todo_entry_s cn63xx;
5759 struct cvmx_pip_todo_entry_s cn63xxp1;
5760 struct cvmx_pip_todo_entry_s cn66xx;
5761 struct cvmx_pip_todo_entry_s cn68xx;
5762 struct cvmx_pip_todo_entry_s cn68xxp1;
5763 struct cvmx_pip_todo_entry_s cnf71xx;
5764 };
5765 typedef union cvmx_pip_todo_entry cvmx_pip_todo_entry_t;
5766
5767 /**
5768 * cvmx_pip_vlan_etypes#
5769 */
5770 union cvmx_pip_vlan_etypesx {
5771 uint64_t u64;
5772 struct cvmx_pip_vlan_etypesx_s {
5773 #ifdef __BIG_ENDIAN_BITFIELD
5774 uint64_t type3 : 16; /**< VLAN Ethertype */
5775 uint64_t type2 : 16; /**< VLAN Ethertype */
5776 uint64_t type1 : 16; /**< VLAN Ethertype */
5777 uint64_t type0 : 16; /**< VLAN Ethertype
5778 Specifies ethertypes that will be parsed as
5779 containing VLAN information. Each TYPE is
5780 orthagonal; if all eight are not required, set
5781 multiple TYPEs to the same value (as in the
5782 0x8100 default value). */
5783 #else
5784 uint64_t type0 : 16;
5785 uint64_t type1 : 16;
5786 uint64_t type2 : 16;
5787 uint64_t type3 : 16;
5788 #endif
5789 } s;
5790 struct cvmx_pip_vlan_etypesx_s cn61xx;
5791 struct cvmx_pip_vlan_etypesx_s cn66xx;
5792 struct cvmx_pip_vlan_etypesx_s cn68xx;
5793 struct cvmx_pip_vlan_etypesx_s cnf71xx;
5794 };
5795 typedef union cvmx_pip_vlan_etypesx cvmx_pip_vlan_etypesx_t;
5796
5797 /**
5798 * cvmx_pip_xstat0_prt#
5799 *
5800 * PIP_XSTAT0_PRT = PIP_XSTAT_DRP_PKTS / PIP_XSTAT_DRP_OCTS
5801 *
5802 */
5803 union cvmx_pip_xstat0_prtx {
5804 uint64_t u64;
5805 struct cvmx_pip_xstat0_prtx_s {
5806 #ifdef __BIG_ENDIAN_BITFIELD
5807 uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD
5808 QOS widget per port */
5809 uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD
5810 QOS widget per port */
5811 #else
5812 uint64_t drp_octs : 32;
5813 uint64_t drp_pkts : 32;
5814 #endif
5815 } s;
5816 struct cvmx_pip_xstat0_prtx_s cn63xx;
5817 struct cvmx_pip_xstat0_prtx_s cn63xxp1;
5818 struct cvmx_pip_xstat0_prtx_s cn66xx;
5819 };
5820 typedef union cvmx_pip_xstat0_prtx cvmx_pip_xstat0_prtx_t;
5821
5822 /**
5823 * cvmx_pip_xstat10_prt#
5824 *
5825 * PIP_XSTAT10_PRTX = PIP_XSTAT_L2_MCAST / PIP_XSTAT_L2_BCAST
5826 *
5827 */
5828 union cvmx_pip_xstat10_prtx {
5829 uint64_t u64;
5830 struct cvmx_pip_xstat10_prtx_s {
5831 #ifdef __BIG_ENDIAN_BITFIELD
5832 uint64_t bcast : 32; /**< Number of packets with L2 Broadcast DMAC
5833 that were dropped due to RED.
5834 The HW will consider a packet to be an L2
5835 broadcast packet when the 48-bit DMAC is all 1's.
5836 Only applies when the parse mode for the packet
5837 is SKIP-TO-L2. */
5838 uint64_t mcast : 32; /**< Number of packets with L2 Mulitcast DMAC
5839 that were dropped due to RED.
5840 The HW will consider a packet to be an L2
5841 multicast packet when the least-significant bit
5842 of the first byte of the DMAC is set and the
5843 packet is not an L2 broadcast packet.
5844 Only applies when the parse mode for the packet
5845 is SKIP-TO-L2. */
5846 #else
5847 uint64_t mcast : 32;
5848 uint64_t bcast : 32;
5849 #endif
5850 } s;
5851 struct cvmx_pip_xstat10_prtx_s cn63xx;
5852 struct cvmx_pip_xstat10_prtx_s cn63xxp1;
5853 struct cvmx_pip_xstat10_prtx_s cn66xx;
5854 };
5855 typedef union cvmx_pip_xstat10_prtx cvmx_pip_xstat10_prtx_t;
5856
5857 /**
5858 * cvmx_pip_xstat11_prt#
5859 *
5860 * PIP_XSTAT11_PRTX = PIP_XSTAT_L3_MCAST / PIP_XSTAT_L3_BCAST
5861 *
5862 */
5863 union cvmx_pip_xstat11_prtx {
5864 uint64_t u64;
5865 struct cvmx_pip_xstat11_prtx_s {
5866 #ifdef __BIG_ENDIAN_BITFIELD
5867 uint64_t bcast : 32; /**< Number of packets with L3 Broadcast Dest Address
5868 that were dropped due to RED.
5869 The HW considers an IPv4 packet to be broadcast
5870 when all bits are set in the MSB of the
5871 destination address. IPv6 does not have the
5872 concept of a broadcast packets.
5873 Only applies when the parse mode for the packet
5874 is SKIP-TO-L2 and the packet is IP or the parse
5875 mode for the packet is SKIP-TO-IP. */
5876 uint64_t mcast : 32; /**< Number of packets with L3 Multicast Dest Address
5877 that were dropped due to RED.
5878 The HW considers an IPv4 packet to be multicast
5879 when the most-significant nibble of the 32-bit
5880 destination address is 0xE (i.e. it is a class D
5881 address). The HW considers an IPv6 packet to be
5882 multicast when the most-significant byte of the
5883 128-bit destination address is all 1's.
5884 Only applies when the parse mode for the packet
5885 is SKIP-TO-L2 and the packet is IP or the parse
5886 mode for the packet is SKIP-TO-IP. */
5887 #else
5888 uint64_t mcast : 32;
5889 uint64_t bcast : 32;
5890 #endif
5891 } s;
5892 struct cvmx_pip_xstat11_prtx_s cn63xx;
5893 struct cvmx_pip_xstat11_prtx_s cn63xxp1;
5894 struct cvmx_pip_xstat11_prtx_s cn66xx;
5895 };
5896 typedef union cvmx_pip_xstat11_prtx cvmx_pip_xstat11_prtx_t;
5897
5898 /**
5899 * cvmx_pip_xstat1_prt#
5900 *
5901 * PIP_XSTAT1_PRTX = PIP_XSTAT_OCTS
5902 *
5903 */
5904 union cvmx_pip_xstat1_prtx {
5905 uint64_t u64;
5906 struct cvmx_pip_xstat1_prtx_s {
5907 #ifdef __BIG_ENDIAN_BITFIELD
5908 uint64_t reserved_48_63 : 16;
5909 uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */
5910 #else
5911 uint64_t octs : 48;
5912 uint64_t reserved_48_63 : 16;
5913 #endif
5914 } s;
5915 struct cvmx_pip_xstat1_prtx_s cn63xx;
5916 struct cvmx_pip_xstat1_prtx_s cn63xxp1;
5917 struct cvmx_pip_xstat1_prtx_s cn66xx;
5918 };
5919 typedef union cvmx_pip_xstat1_prtx cvmx_pip_xstat1_prtx_t;
5920
5921 /**
5922 * cvmx_pip_xstat2_prt#
5923 *
5924 * PIP_XSTAT2_PRTX = PIP_XSTAT_PKTS / PIP_XSTAT_RAW
5925 *
5926 */
5927 union cvmx_pip_xstat2_prtx {
5928 uint64_t u64;
5929 struct cvmx_pip_xstat2_prtx_s {
5930 #ifdef __BIG_ENDIAN_BITFIELD
5931 uint64_t pkts : 32; /**< Number of packets processed by PIP */
5932 uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error
5933 received by PIP per port */
5934 #else
5935 uint64_t raw : 32;
5936 uint64_t pkts : 32;
5937 #endif
5938 } s;
5939 struct cvmx_pip_xstat2_prtx_s cn63xx;
5940 struct cvmx_pip_xstat2_prtx_s cn63xxp1;
5941 struct cvmx_pip_xstat2_prtx_s cn66xx;
5942 };
5943 typedef union cvmx_pip_xstat2_prtx cvmx_pip_xstat2_prtx_t;
5944
5945 /**
5946 * cvmx_pip_xstat3_prt#
5947 *
5948 * PIP_XSTAT3_PRTX = PIP_XSTAT_BCST / PIP_XSTAT_MCST
5949 *
5950 */
5951 union cvmx_pip_xstat3_prtx {
5952 uint64_t u64;
5953 struct cvmx_pip_xstat3_prtx_s {
5954 #ifdef __BIG_ENDIAN_BITFIELD
5955 uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets
5956 Does not include multicast packets
5957 Only includes packets whose parse mode is
5958 SKIP_TO_L2. */
5959 uint64_t mcst : 32; /**< Number of indentified L2 multicast packets
5960 Does not include broadcast packets
5961 Only includes packets whose parse mode is
5962 SKIP_TO_L2. */
5963 #else
5964 uint64_t mcst : 32;
5965 uint64_t bcst : 32;
5966 #endif
5967 } s;
5968 struct cvmx_pip_xstat3_prtx_s cn63xx;
5969 struct cvmx_pip_xstat3_prtx_s cn63xxp1;
5970 struct cvmx_pip_xstat3_prtx_s cn66xx;
5971 };
5972 typedef union cvmx_pip_xstat3_prtx cvmx_pip_xstat3_prtx_t;
5973
5974 /**
5975 * cvmx_pip_xstat4_prt#
5976 *
5977 * PIP_XSTAT4_PRTX = PIP_XSTAT_HIST1 / PIP_XSTAT_HIST0
5978 *
5979 */
5980 union cvmx_pip_xstat4_prtx {
5981 uint64_t u64;
5982 struct cvmx_pip_xstat4_prtx_s {
5983 #ifdef __BIG_ENDIAN_BITFIELD
5984 uint64_t h65to127 : 32; /**< Number of 65-127B packets */
5985 uint64_t h64 : 32; /**< Number of 1-64B packets */
5986 #else
5987 uint64_t h64 : 32;
5988 uint64_t h65to127 : 32;
5989 #endif
5990 } s;
5991 struct cvmx_pip_xstat4_prtx_s cn63xx;
5992 struct cvmx_pip_xstat4_prtx_s cn63xxp1;
5993 struct cvmx_pip_xstat4_prtx_s cn66xx;
5994 };
5995 typedef union cvmx_pip_xstat4_prtx cvmx_pip_xstat4_prtx_t;
5996
5997 /**
5998 * cvmx_pip_xstat5_prt#
5999 *
6000 * PIP_XSTAT5_PRTX = PIP_XSTAT_HIST3 / PIP_XSTAT_HIST2
6001 *
6002 */
6003 union cvmx_pip_xstat5_prtx {
6004 uint64_t u64;
6005 struct cvmx_pip_xstat5_prtx_s {
6006 #ifdef __BIG_ENDIAN_BITFIELD
6007 uint64_t h256to511 : 32; /**< Number of 256-511B packets */
6008 uint64_t h128to255 : 32; /**< Number of 128-255B packets */
6009 #else
6010 uint64_t h128to255 : 32;
6011 uint64_t h256to511 : 32;
6012 #endif
6013 } s;
6014 struct cvmx_pip_xstat5_prtx_s cn63xx;
6015 struct cvmx_pip_xstat5_prtx_s cn63xxp1;
6016 struct cvmx_pip_xstat5_prtx_s cn66xx;
6017 };
6018 typedef union cvmx_pip_xstat5_prtx cvmx_pip_xstat5_prtx_t;
6019
6020 /**
6021 * cvmx_pip_xstat6_prt#
6022 *
6023 * PIP_XSTAT6_PRTX = PIP_XSTAT_HIST5 / PIP_XSTAT_HIST4
6024 *
6025 */
6026 union cvmx_pip_xstat6_prtx {
6027 uint64_t u64;
6028 struct cvmx_pip_xstat6_prtx_s {
6029 #ifdef __BIG_ENDIAN_BITFIELD
6030 uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */
6031 uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */
6032 #else
6033 uint64_t h512to1023 : 32;
6034 uint64_t h1024to1518 : 32;
6035 #endif
6036 } s;
6037 struct cvmx_pip_xstat6_prtx_s cn63xx;
6038 struct cvmx_pip_xstat6_prtx_s cn63xxp1;
6039 struct cvmx_pip_xstat6_prtx_s cn66xx;
6040 };
6041 typedef union cvmx_pip_xstat6_prtx cvmx_pip_xstat6_prtx_t;
6042
6043 /**
6044 * cvmx_pip_xstat7_prt#
6045 *
6046 * PIP_XSTAT7_PRTX = PIP_XSTAT_FCS / PIP_XSTAT_HIST6
6047 *
6048 *
6049 * Notes:
6050 * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35
6051 * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47
6052 */
6053 union cvmx_pip_xstat7_prtx {
6054 uint64_t u64;
6055 struct cvmx_pip_xstat7_prtx_s {
6056 #ifdef __BIG_ENDIAN_BITFIELD
6057 uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */
6058 uint64_t h1519 : 32; /**< Number of 1519-max packets */
6059 #else
6060 uint64_t h1519 : 32;
6061 uint64_t fcs : 32;
6062 #endif
6063 } s;
6064 struct cvmx_pip_xstat7_prtx_s cn63xx;
6065 struct cvmx_pip_xstat7_prtx_s cn63xxp1;
6066 struct cvmx_pip_xstat7_prtx_s cn66xx;
6067 };
6068 typedef union cvmx_pip_xstat7_prtx cvmx_pip_xstat7_prtx_t;
6069
6070 /**
6071 * cvmx_pip_xstat8_prt#
6072 *
6073 * PIP_XSTAT8_PRTX = PIP_XSTAT_FRAG / PIP_XSTAT_UNDER
6074 *
6075 *
6076 * Notes:
6077 * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35
6078 * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47
6079 */
6080 union cvmx_pip_xstat8_prtx {
6081 uint64_t u64;
6082 struct cvmx_pip_xstat8_prtx_s {
6083 #ifdef __BIG_ENDIAN_BITFIELD
6084 uint64_t frag : 32; /**< Number of packets with length < min and FCS error */
6085 uint64_t undersz : 32; /**< Number of packets with length < min */
6086 #else
6087 uint64_t undersz : 32;
6088 uint64_t frag : 32;
6089 #endif
6090 } s;
6091 struct cvmx_pip_xstat8_prtx_s cn63xx;
6092 struct cvmx_pip_xstat8_prtx_s cn63xxp1;
6093 struct cvmx_pip_xstat8_prtx_s cn66xx;
6094 };
6095 typedef union cvmx_pip_xstat8_prtx cvmx_pip_xstat8_prtx_t;
6096
6097 /**
6098 * cvmx_pip_xstat9_prt#
6099 *
6100 * PIP_XSTAT9_PRTX = PIP_XSTAT_JABBER / PIP_XSTAT_OVER
6101 *
6102 *
6103 * Notes:
6104 * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35
6105 * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors
6106 * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions
6107 */
6108 union cvmx_pip_xstat9_prtx {
6109 uint64_t u64;
6110 struct cvmx_pip_xstat9_prtx_s {
6111 #ifdef __BIG_ENDIAN_BITFIELD
6112 uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */
6113 uint64_t oversz : 32; /**< Number of packets with length > max */
6114 #else
6115 uint64_t oversz : 32;
6116 uint64_t jabber : 32;
6117 #endif
6118 } s;
6119 struct cvmx_pip_xstat9_prtx_s cn63xx;
6120 struct cvmx_pip_xstat9_prtx_s cn63xxp1;
6121 struct cvmx_pip_xstat9_prtx_s cn66xx;
6122 };
6123 typedef union cvmx_pip_xstat9_prtx cvmx_pip_xstat9_prtx_t;
6124
6125 #endif
6126