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39
40
41 /**
42 * cvmx-pexp-defs.h
43 *
44 * Configuration and status register (CSR) definitions for
45 * OCTEON PEXP.
46 *
47 * <hr>$Revision$<hr>
48 */
49 #ifndef __CVMX_PEXP_DEFS_H__
50 #define __CVMX_PEXP_DEFS_H__
51
52 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)53 static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
54 {
55 if (!(
56 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
57 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
58 cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
60 }
61 #else
62 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
63 #endif
64 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
65 #define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)66 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
67 {
68 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
69 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
70 return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
71 }
72 #else
73 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
74 #endif
75 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
76 #define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)77 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
78 {
79 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
80 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
81 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
82 }
83 #else
84 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
85 #endif
86 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
87 #define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)88 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
89 {
90 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
91 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
92 return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
93 }
94 #else
95 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
96 #endif
97 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
98 #define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)99 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
100 {
101 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
102 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
103 return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
104 }
105 #else
106 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
107 #endif
108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
109 #define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)110 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
111 {
112 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
113 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
114 return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
115 }
116 #else
117 #define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
118 #endif
119 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
120 #define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)121 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
122 {
123 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
124 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
125 return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
126 }
127 #else
128 #define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
129 #endif
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
131 #define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)132 static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
133 {
134 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
135 cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
136 return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
137 }
138 #else
139 #define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
140 #endif
141 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
142 #define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)143 static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
144 {
145 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
146 cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
147 return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
148 }
149 #else
150 #define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
151 #endif
152 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
153 #define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)154 static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
155 {
156 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
157 cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
158 return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
159 }
160 #else
161 #define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
162 #endif
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)165 static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
166 {
167 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
168 cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
169 return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
170 }
171 #else
172 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
173 #endif
174 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
175 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)176 static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
177 {
178 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
179 cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
180 return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
181 }
182 #else
183 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
184 #endif
185 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)186 static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
187 {
188 if (!(
189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
191 cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
192 return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16;
193 }
194 #else
195 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
196 #endif
197 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)198 static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
199 {
200 if (!(
201 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
203 cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
204 return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16;
205 }
206 #else
207 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
208 #endif
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)210 static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
211 {
212 if (!(
213 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
214 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
215 cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
216 return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16;
217 }
218 #else
219 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
220 #endif
221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)222 static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
223 {
224 if (!(
225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
227 cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
228 return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16;
229 }
230 #else
231 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
232 #endif
233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
234 #define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)235 static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
236 {
237 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
238 cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
239 return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
240 }
241 #else
242 #define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
243 #endif
244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
245 #define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)246 static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
247 {
248 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
249 cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
250 return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
251 }
252 #else
253 #define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
254 #endif
255 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
256 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC()
CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)257 static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
258 {
259 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
260 cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
261 return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
262 }
263 #else
264 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
265 #endif
266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
267 #define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC()
CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)268 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)
269 {
270 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
271 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n");
272 return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
273 }
274 #else
275 #define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
276 #endif
277 #define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
278 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
279 #define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC()
CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)280 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)
281 {
282 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
283 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n");
284 return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
285 }
286 #else
287 #define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
288 #endif
289 #define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
290 #define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
291 #define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
292 #define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
293 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
294 #define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)295 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
296 {
297 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
298 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
299 return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
300 }
301 #else
302 #define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
303 #endif
304 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
305 #define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)306 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
307 {
308 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
309 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
310 return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
311 }
312 #else
313 #define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
314 #endif
315 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
316 #define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)317 static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
318 {
319 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
320 cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
321 return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
322 }
323 #else
324 #define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
325 #endif
326 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
327 #define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
CVMX_PEXP_NPEI_INT_ENB_FUNC(void)328 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
329 {
330 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
331 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
332 return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
333 }
334 #else
335 #define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
336 #endif
337 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
338 #define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)339 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
340 {
341 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
342 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
343 return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
344 }
345 #else
346 #define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
347 #endif
348 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
349 #define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
CVMX_PEXP_NPEI_INT_INFO_FUNC(void)350 static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
351 {
352 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
353 cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
354 return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
355 }
356 #else
357 #define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
358 #endif
359 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
360 #define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
CVMX_PEXP_NPEI_INT_SUM_FUNC(void)361 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
362 {
363 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
364 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
365 return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
366 }
367 #else
368 #define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
369 #endif
370 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
371 #define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)372 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
373 {
374 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
375 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
376 return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
377 }
378 #else
379 #define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
380 #endif
381 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
382 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)383 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
384 {
385 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
386 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
387 return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
388 }
389 #else
390 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
391 #endif
392 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
393 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)394 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
395 {
396 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
397 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
398 return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
399 }
400 #else
401 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
402 #endif
403 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
404 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)405 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
406 {
407 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
408 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
409 return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
410 }
411 #else
412 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
413 #endif
414 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)415 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
416 {
417 if (!(
418 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
419 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
420 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
421 return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12;
422 }
423 #else
424 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
425 #endif
426 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
427 #define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)428 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
429 {
430 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
431 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
432 return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
433 }
434 #else
435 #define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
436 #endif
437 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
438 #define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)439 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
440 {
441 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
442 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
443 return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
444 }
445 #else
446 #define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
447 #endif
448 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
449 #define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)450 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
451 {
452 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
453 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
454 return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
455 }
456 #else
457 #define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
458 #endif
459 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
460 #define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)461 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
462 {
463 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
464 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
465 return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
466 }
467 #else
468 #define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
469 #endif
470 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
471 #define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)472 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
473 {
474 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
475 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
476 return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
477 }
478 #else
479 #define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
480 #endif
481 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
482 #define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)483 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
484 {
485 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
486 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
487 return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
488 }
489 #else
490 #define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
491 #endif
492 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
493 #define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)494 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
495 {
496 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
497 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
498 return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
499 }
500 #else
501 #define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
502 #endif
503 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
504 #define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)505 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
506 {
507 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
508 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
509 return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
510 }
511 #else
512 #define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
513 #endif
514 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
515 #define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)516 static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
517 {
518 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
519 cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
520 return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
521 }
522 #else
523 #define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
524 #endif
525 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
526 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)527 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
528 {
529 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
530 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
531 return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
532 }
533 #else
534 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
535 #endif
536 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
537 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)538 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
539 {
540 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
541 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
542 return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
543 }
544 #else
545 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
546 #endif
547 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
548 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)549 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
550 {
551 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
552 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
553 return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
554 }
555 #else
556 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
557 #endif
558 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
559 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)560 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
561 {
562 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
563 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
564 return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
565 }
566 #else
567 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
568 #endif
569 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
570 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)571 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
572 {
573 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
574 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
575 return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
576 }
577 #else
578 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
579 #endif
580 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
581 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)582 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
583 {
584 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
585 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
586 return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
587 }
588 #else
589 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
590 #endif
591 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
592 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)593 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
594 {
595 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
596 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
597 return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
598 }
599 #else
600 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
601 #endif
602 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
603 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)604 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
605 {
606 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
607 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
608 return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
609 }
610 #else
611 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
612 #endif
613 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
614 #define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)615 static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
616 {
617 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
618 cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
619 return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
620 }
621 #else
622 #define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
623 #endif
624 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
625 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)626 static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
627 {
628 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
629 cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
630 return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
631 }
632 #else
633 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
634 #endif
635 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
636 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)637 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
638 {
639 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
640 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
641 return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
642 }
643 #else
644 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
645 #endif
646 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
647 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)648 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
649 {
650 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
651 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
652 return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
653 }
654 #else
655 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
656 #endif
657 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
658 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)659 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
660 {
661 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
662 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
663 return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
664 }
665 #else
666 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
667 #endif
668 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
669 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)670 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
671 {
672 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
673 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
674 return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
675 }
676 #else
677 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
678 #endif
679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)680 static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
681 {
682 if (!(
683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
685 cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
686 return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16;
687 }
688 #else
689 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
690 #endif
691 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)692 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
693 {
694 if (!(
695 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
696 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
697 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
698 return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16;
699 }
700 #else
701 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
702 #endif
703 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)704 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
705 {
706 if (!(
707 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
709 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
710 return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16;
711 }
712 #else
713 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
714 #endif
715 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)716 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
717 {
718 if (!(
719 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
720 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
721 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
722 return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16;
723 }
724 #else
725 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
726 #endif
727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)728 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
729 {
730 if (!(
731 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
732 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
733 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
734 return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16;
735 }
736 #else
737 #define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
738 #endif
739 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)740 static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
741 {
742 if (!(
743 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
744 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
745 cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
746 return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16;
747 }
748 #else
749 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
750 #endif
751 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)752 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
753 {
754 if (!(
755 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
757 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
758 return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16;
759 }
760 #else
761 #define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
762 #endif
763 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)764 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
765 {
766 if (!(
767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
769 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
770 return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16;
771 }
772 #else
773 #define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
774 #endif
775 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)776 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
777 {
778 if (!(
779 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
780 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
781 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
782 return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16;
783 }
784 #else
785 #define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
786 #endif
787 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
788 #define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)789 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
790 {
791 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
792 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
793 return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
794 }
795 #else
796 #define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
797 #endif
798 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
799 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)800 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
801 {
802 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
803 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
804 return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
805 }
806 #else
807 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
808 #endif
809 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
810 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)811 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
812 {
813 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
814 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
815 return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
816 }
817 #else
818 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
819 #endif
820 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
821 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)822 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
823 {
824 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
825 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
826 return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
827 }
828 #else
829 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
830 #endif
831 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
832 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)833 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
834 {
835 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
836 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
837 return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
838 }
839 #else
840 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
841 #endif
842 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
843 #define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)844 static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
845 {
846 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
847 cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
848 return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
849 }
850 #else
851 #define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
852 #endif
853 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
854 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)855 static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
856 {
857 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
858 cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
859 return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
860 }
861 #else
862 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
863 #endif
864 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
865 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)866 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
867 {
868 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
869 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
870 return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
871 }
872 #else
873 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
874 #endif
875 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
876 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)877 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
878 {
879 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
880 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
881 return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
882 }
883 #else
884 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
885 #endif
886 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
887 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)888 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
889 {
890 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
891 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
892 return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
893 }
894 #else
895 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
896 #endif
897 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
898 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)899 static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
900 {
901 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
902 cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
903 return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
904 }
905 #else
906 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
907 #endif
908 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
909 #define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)910 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
911 {
912 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
913 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
914 return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
915 }
916 #else
917 #define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
918 #endif
919 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)920 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
921 {
922 if (!(
923 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
924 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
925 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
926 return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16;
927 }
928 #else
929 #define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
930 #endif
931 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
932 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)933 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
934 {
935 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
936 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
937 return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
938 }
939 #else
940 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
941 #endif
942 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
943 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)944 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
945 {
946 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
947 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
948 return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
949 }
950 #else
951 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
952 #endif
953 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
954 #define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)955 static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
956 {
957 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
958 cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
959 return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
960 }
961 #else
962 #define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
963 #endif
964 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
965 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)966 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
967 {
968 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
969 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
970 return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
971 }
972 #else
973 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
974 #endif
975 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
976 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)977 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
978 {
979 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
980 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
981 return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
982 }
983 #else
984 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
985 #endif
986 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
987 #define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)988 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
989 {
990 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
991 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
992 return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
993 }
994 #else
995 #define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
996 #endif
997 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
998 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)999 static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
1000 {
1001 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1002 cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
1003 return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
1004 }
1005 #else
1006 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
1007 #endif
1008 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1009 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)1010 static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
1011 {
1012 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1013 cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
1014 return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
1015 }
1016 #else
1017 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
1018 #endif
1019 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1020 #define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)1021 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
1022 {
1023 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1024 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
1025 return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
1026 }
1027 #else
1028 #define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
1029 #endif
1030 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1031 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)1032 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
1033 {
1034 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1035 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
1036 return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
1037 }
1038 #else
1039 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
1040 #endif
1041 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1042 #define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)1043 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
1044 {
1045 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1046 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
1047 return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
1048 }
1049 #else
1050 #define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
1051 #endif
1052 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1053 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)1054 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
1055 {
1056 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1057 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
1058 return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
1059 }
1060 #else
1061 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
1062 #endif
1063 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1064 #define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)1065 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
1066 {
1067 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1068 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
1069 return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
1070 }
1071 #else
1072 #define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
1073 #endif
1074 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1075 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)1076 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
1077 {
1078 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1079 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
1080 return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
1081 }
1082 #else
1083 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
1084 #endif
1085 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1086 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)1087 static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
1088 {
1089 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1090 cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
1091 return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
1092 }
1093 #else
1094 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
1095 #endif
1096 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1097 #define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)1098 static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
1099 {
1100 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1101 cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
1102 return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
1103 }
1104 #else
1105 #define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
1106 #endif
1107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1108 #define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
CVMX_PEXP_NPEI_STATE1_FUNC(void)1109 static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
1110 {
1111 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1112 cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
1113 return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
1114 }
1115 #else
1116 #define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
1117 #endif
1118 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1119 #define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
CVMX_PEXP_NPEI_STATE2_FUNC(void)1120 static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
1121 {
1122 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1123 cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
1124 return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
1125 }
1126 #else
1127 #define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
1128 #endif
1129 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1130 #define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
CVMX_PEXP_NPEI_STATE3_FUNC(void)1131 static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
1132 {
1133 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1134 cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
1135 return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
1136 }
1137 #else
1138 #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
1139 #endif
1140 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1141 #define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)1142 static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
1143 {
1144 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1145 cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
1146 return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
1147 }
1148 #else
1149 #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
1150 #endif
1151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1152 #define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC()
CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)1153 static inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)
1154 {
1155 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1156 cvmx_warn("CVMX_PEXP_SLI_BIST_STATUS not supported on this chip\n");
1157 return CVMX_ADD_IO_SEG(0x00011F0000010580ull);
1158 }
1159 #else
1160 #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
1161 #endif
1162 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)1163 static inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
1164 {
1165 if (!(
1166 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
1169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1170 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1171 cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
1172 return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16;
1173 }
1174 #else
1175 #define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
1176 #endif
1177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1178 #define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC()
CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)1179 static inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)
1180 {
1181 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1182 cvmx_warn("CVMX_PEXP_SLI_CTL_STATUS not supported on this chip\n");
1183 return CVMX_ADD_IO_SEG(0x00011F0000010570ull);
1184 }
1185 #else
1186 #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
1187 #endif
1188 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1189 #define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC()
CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)1190 static inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)
1191 {
1192 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1193 cvmx_warn("CVMX_PEXP_SLI_DATA_OUT_CNT not supported on this chip\n");
1194 return CVMX_ADD_IO_SEG(0x00011F00000105F0ull);
1195 }
1196 #else
1197 #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
1198 #endif
1199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1200 #define CVMX_PEXP_SLI_DBG_DATA CVMX_PEXP_SLI_DBG_DATA_FUNC()
CVMX_PEXP_SLI_DBG_DATA_FUNC(void)1201 static inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void)
1202 {
1203 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1204 cvmx_warn("CVMX_PEXP_SLI_DBG_DATA not supported on this chip\n");
1205 return CVMX_ADD_IO_SEG(0x00011F0000010310ull);
1206 }
1207 #else
1208 #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
1209 #endif
1210 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1211 #define CVMX_PEXP_SLI_DBG_SELECT CVMX_PEXP_SLI_DBG_SELECT_FUNC()
CVMX_PEXP_SLI_DBG_SELECT_FUNC(void)1212 static inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void)
1213 {
1214 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1215 cvmx_warn("CVMX_PEXP_SLI_DBG_SELECT not supported on this chip\n");
1216 return CVMX_ADD_IO_SEG(0x00011F0000010300ull);
1217 }
1218 #else
1219 #define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
1220 #endif
1221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)1222 static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
1223 {
1224 if (!(
1225 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1226 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1227 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1228 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1229 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1230 cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
1231 return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16;
1232 }
1233 #else
1234 #define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
1235 #endif
1236 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)1237 static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
1238 {
1239 if (!(
1240 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1241 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1242 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1243 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1244 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1245 cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
1246 return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16;
1247 }
1248 #else
1249 #define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
1250 #endif
1251 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)1252 static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
1253 {
1254 if (!(
1255 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1256 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1257 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1258 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1259 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1260 cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
1261 return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16;
1262 }
1263 #else
1264 #define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
1265 #endif
1266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1267 #define CVMX_PEXP_SLI_INT_ENB_CIU CVMX_PEXP_SLI_INT_ENB_CIU_FUNC()
CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void)1268 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void)
1269 {
1270 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1271 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_CIU not supported on this chip\n");
1272 return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull);
1273 }
1274 #else
1275 #define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
1276 #endif
1277 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)1278 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)
1279 {
1280 if (!(
1281 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1282 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1283 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1284 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1285 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1286 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
1287 return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16;
1288 }
1289 #else
1290 #define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
1291 #endif
1292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1293 #define CVMX_PEXP_SLI_INT_SUM CVMX_PEXP_SLI_INT_SUM_FUNC()
CVMX_PEXP_SLI_INT_SUM_FUNC(void)1294 static inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void)
1295 {
1296 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1297 cvmx_warn("CVMX_PEXP_SLI_INT_SUM not supported on this chip\n");
1298 return CVMX_ADD_IO_SEG(0x00011F0000010330ull);
1299 }
1300 #else
1301 #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
1302 #endif
1303 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1304 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC()
CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void)1305 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void)
1306 {
1307 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1308 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
1309 return CVMX_ADD_IO_SEG(0x00011F0000010600ull);
1310 }
1311 #else
1312 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
1313 #endif
1314 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1315 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC()
CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void)1316 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void)
1317 {
1318 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1319 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
1320 return CVMX_ADD_IO_SEG(0x00011F0000010610ull);
1321 }
1322 #else
1323 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
1324 #endif
1325 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1326 #define CVMX_PEXP_SLI_LAST_WIN_RDATA2 CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC()
CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC(void)1327 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC(void)
1328 {
1329 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1330 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA2 not supported on this chip\n");
1331 return CVMX_ADD_IO_SEG(0x00011F00000106C0ull);
1332 }
1333 #else
1334 #define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
1335 #endif
1336 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1337 #define CVMX_PEXP_SLI_LAST_WIN_RDATA3 CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC()
CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC(void)1338 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC(void)
1339 {
1340 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1341 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA3 not supported on this chip\n");
1342 return CVMX_ADD_IO_SEG(0x00011F00000106D0ull);
1343 }
1344 #else
1345 #define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
1346 #endif
1347 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1348 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC()
CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)1349 static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)
1350 {
1351 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1352 cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT not supported on this chip\n");
1353 return CVMX_ADD_IO_SEG(0x00011F0000013D70ull);
1354 }
1355 #else
1356 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
1357 #endif
1358 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1359 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC()
CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC(void)1360 static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC(void)
1361 {
1362 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1363 cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT2 not supported on this chip\n");
1364 return CVMX_ADD_IO_SEG(0x00011F0000013E10ull);
1365 }
1366 #else
1367 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
1368 #endif
1369 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1370 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC()
CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)1371 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)
1372 {
1373 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1374 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_CTL not supported on this chip\n");
1375 return CVMX_ADD_IO_SEG(0x00011F00000102F0ull);
1376 }
1377 #else
1378 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
1379 #endif
1380 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)1381 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
1382 {
1383 if (!(
1384 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
1385 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
1386 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
1387 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
1388 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
1389 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
1390 return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12;
1391 }
1392 #else
1393 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
1394 #endif
1395 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1396 #define CVMX_PEXP_SLI_MSI_ENB0 CVMX_PEXP_SLI_MSI_ENB0_FUNC()
CVMX_PEXP_SLI_MSI_ENB0_FUNC(void)1397 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void)
1398 {
1399 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1400 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB0 not supported on this chip\n");
1401 return CVMX_ADD_IO_SEG(0x00011F0000013C50ull);
1402 }
1403 #else
1404 #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
1405 #endif
1406 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1407 #define CVMX_PEXP_SLI_MSI_ENB1 CVMX_PEXP_SLI_MSI_ENB1_FUNC()
CVMX_PEXP_SLI_MSI_ENB1_FUNC(void)1408 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void)
1409 {
1410 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1411 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB1 not supported on this chip\n");
1412 return CVMX_ADD_IO_SEG(0x00011F0000013C60ull);
1413 }
1414 #else
1415 #define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
1416 #endif
1417 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1418 #define CVMX_PEXP_SLI_MSI_ENB2 CVMX_PEXP_SLI_MSI_ENB2_FUNC()
CVMX_PEXP_SLI_MSI_ENB2_FUNC(void)1419 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void)
1420 {
1421 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1422 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB2 not supported on this chip\n");
1423 return CVMX_ADD_IO_SEG(0x00011F0000013C70ull);
1424 }
1425 #else
1426 #define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
1427 #endif
1428 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1429 #define CVMX_PEXP_SLI_MSI_ENB3 CVMX_PEXP_SLI_MSI_ENB3_FUNC()
CVMX_PEXP_SLI_MSI_ENB3_FUNC(void)1430 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void)
1431 {
1432 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1433 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB3 not supported on this chip\n");
1434 return CVMX_ADD_IO_SEG(0x00011F0000013C80ull);
1435 }
1436 #else
1437 #define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
1438 #endif
1439 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1440 #define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC()
CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)1441 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)
1442 {
1443 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1444 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV0 not supported on this chip\n");
1445 return CVMX_ADD_IO_SEG(0x00011F0000013C10ull);
1446 }
1447 #else
1448 #define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
1449 #endif
1450 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1451 #define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC()
CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)1452 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)
1453 {
1454 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1455 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV1 not supported on this chip\n");
1456 return CVMX_ADD_IO_SEG(0x00011F0000013C20ull);
1457 }
1458 #else
1459 #define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
1460 #endif
1461 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1462 #define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC()
CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)1463 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)
1464 {
1465 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1466 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV2 not supported on this chip\n");
1467 return CVMX_ADD_IO_SEG(0x00011F0000013C30ull);
1468 }
1469 #else
1470 #define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
1471 #endif
1472 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1473 #define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC()
CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)1474 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)
1475 {
1476 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1477 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV3 not supported on this chip\n");
1478 return CVMX_ADD_IO_SEG(0x00011F0000013C40ull);
1479 }
1480 #else
1481 #define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
1482 #endif
1483 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1484 #define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC()
CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)1485 static inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)
1486 {
1487 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1488 cvmx_warn("CVMX_PEXP_SLI_MSI_RD_MAP not supported on this chip\n");
1489 return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull);
1490 }
1491 #else
1492 #define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
1493 #endif
1494 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1495 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC()
CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void)1496 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void)
1497 {
1498 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1499 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB0 not supported on this chip\n");
1500 return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull);
1501 }
1502 #else
1503 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
1504 #endif
1505 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1506 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC()
CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void)1507 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void)
1508 {
1509 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1510 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB1 not supported on this chip\n");
1511 return CVMX_ADD_IO_SEG(0x00011F0000013D00ull);
1512 }
1513 #else
1514 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
1515 #endif
1516 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1517 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC()
CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void)1518 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void)
1519 {
1520 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1521 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB2 not supported on this chip\n");
1522 return CVMX_ADD_IO_SEG(0x00011F0000013D10ull);
1523 }
1524 #else
1525 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
1526 #endif
1527 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1528 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC()
CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void)1529 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void)
1530 {
1531 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1532 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB3 not supported on this chip\n");
1533 return CVMX_ADD_IO_SEG(0x00011F0000013D20ull);
1534 }
1535 #else
1536 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
1537 #endif
1538 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1539 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC()
CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void)1540 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void)
1541 {
1542 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1543 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB0 not supported on this chip\n");
1544 return CVMX_ADD_IO_SEG(0x00011F0000013D30ull);
1545 }
1546 #else
1547 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
1548 #endif
1549 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1550 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC()
CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void)1551 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void)
1552 {
1553 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1554 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB1 not supported on this chip\n");
1555 return CVMX_ADD_IO_SEG(0x00011F0000013D40ull);
1556 }
1557 #else
1558 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
1559 #endif
1560 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1561 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC()
CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void)1562 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void)
1563 {
1564 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1565 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB2 not supported on this chip\n");
1566 return CVMX_ADD_IO_SEG(0x00011F0000013D50ull);
1567 }
1568 #else
1569 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
1570 #endif
1571 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1572 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC()
CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void)1573 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void)
1574 {
1575 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1576 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB3 not supported on this chip\n");
1577 return CVMX_ADD_IO_SEG(0x00011F0000013D60ull);
1578 }
1579 #else
1580 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
1581 #endif
1582 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1583 #define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC()
CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)1584 static inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)
1585 {
1586 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1587 cvmx_warn("CVMX_PEXP_SLI_MSI_WR_MAP not supported on this chip\n");
1588 return CVMX_ADD_IO_SEG(0x00011F0000013C90ull);
1589 }
1590 #else
1591 #define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
1592 #endif
1593 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1594 #define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC()
CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)1595 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)
1596 {
1597 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1598 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV not supported on this chip\n");
1599 return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull);
1600 }
1601 #else
1602 #define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
1603 #endif
1604 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1605 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC()
CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)1606 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)
1607 {
1608 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1609 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
1610 return CVMX_ADD_IO_SEG(0x00011F0000010650ull);
1611 }
1612 #else
1613 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
1614 #endif
1615 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1616 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC()
CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)1617 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)
1618 {
1619 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1620 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
1621 return CVMX_ADD_IO_SEG(0x00011F0000010660ull);
1622 }
1623 #else
1624 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
1625 #endif
1626 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1627 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC()
CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)1628 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)
1629 {
1630 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1631 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
1632 return CVMX_ADD_IO_SEG(0x00011F0000010670ull);
1633 }
1634 #else
1635 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
1636 #endif
1637 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)1638 static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
1639 {
1640 if (!(
1641 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1642 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1643 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1644 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1645 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1646 cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
1647 return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16;
1648 }
1649 #else
1650 #define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
1651 #endif
1652 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)1653 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
1654 {
1655 if (!(
1656 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1657 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1658 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1659 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1660 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1661 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
1662 return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16;
1663 }
1664 #else
1665 #define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
1666 #endif
1667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)1668 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
1669 {
1670 if (!(
1671 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1672 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1673 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1674 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1675 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1676 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1677 return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16;
1678 }
1679 #else
1680 #define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
1681 #endif
1682 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)1683 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
1684 {
1685 if (!(
1686 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1687 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1688 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1689 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1690 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1691 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1692 return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16;
1693 }
1694 #else
1695 #define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
1696 #endif
1697 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)1698 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)
1699 {
1700 if (!(
1701 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1702 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1703 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1704 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1705 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1706 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
1707 return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16;
1708 }
1709 #else
1710 #define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
1711 #endif
1712 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)1713 static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)
1714 {
1715 if (!(
1716 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1717 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1718 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1719 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1720 cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
1721 return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16;
1722 }
1723 #else
1724 #define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
1725 #endif
1726 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)1727 static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
1728 {
1729 if (!(
1730 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1731 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1732 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1733 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1734 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1735 cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
1736 return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16;
1737 }
1738 #else
1739 #define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
1740 #endif
1741 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)1742 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
1743 {
1744 if (!(
1745 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1746 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1747 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1748 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1749 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1750 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
1751 return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16;
1752 }
1753 #else
1754 #define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
1755 #endif
1756 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)1757 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
1758 {
1759 if (!(
1760 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1761 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1762 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1763 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1764 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1765 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1766 return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16;
1767 }
1768 #else
1769 #define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
1770 #endif
1771 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)1772 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
1773 {
1774 if (!(
1775 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1776 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1777 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1778 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1779 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1780 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1781 return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16;
1782 }
1783 #else
1784 #define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
1785 #endif
1786 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1787 #define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC()
CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)1788 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)
1789 {
1790 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1791 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT not supported on this chip\n");
1792 return CVMX_ADD_IO_SEG(0x00011F0000011130ull);
1793 }
1794 #else
1795 #define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
1796 #endif
1797 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1798 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC()
CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void)1799 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void)
1800 {
1801 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1802 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
1803 return CVMX_ADD_IO_SEG(0x00011F0000011150ull);
1804 }
1805 #else
1806 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
1807 #endif
1808 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1809 #define CVMX_PEXP_SLI_PKT_CTL CVMX_PEXP_SLI_PKT_CTL_FUNC()
CVMX_PEXP_SLI_PKT_CTL_FUNC(void)1810 static inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void)
1811 {
1812 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1813 cvmx_warn("CVMX_PEXP_SLI_PKT_CTL not supported on this chip\n");
1814 return CVMX_ADD_IO_SEG(0x00011F0000011220ull);
1815 }
1816 #else
1817 #define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
1818 #endif
1819 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1820 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC()
CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void)1821 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void)
1822 {
1823 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1824 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
1825 return CVMX_ADD_IO_SEG(0x00011F00000110B0ull);
1826 }
1827 #else
1828 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
1829 #endif
1830 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1831 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC()
CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void)1832 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void)
1833 {
1834 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1835 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
1836 return CVMX_ADD_IO_SEG(0x00011F00000110A0ull);
1837 }
1838 #else
1839 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
1840 #endif
1841 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1842 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC()
CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void)1843 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void)
1844 {
1845 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1846 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
1847 return CVMX_ADD_IO_SEG(0x00011F0000011090ull);
1848 }
1849 #else
1850 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
1851 #endif
1852 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1853 #define CVMX_PEXP_SLI_PKT_DPADDR CVMX_PEXP_SLI_PKT_DPADDR_FUNC()
CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void)1854 static inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void)
1855 {
1856 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1857 cvmx_warn("CVMX_PEXP_SLI_PKT_DPADDR not supported on this chip\n");
1858 return CVMX_ADD_IO_SEG(0x00011F0000011080ull);
1859 }
1860 #else
1861 #define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
1862 #endif
1863 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1864 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC()
CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void)1865 static inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void)
1866 {
1867 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1868 cvmx_warn("CVMX_PEXP_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
1869 return CVMX_ADD_IO_SEG(0x00011F0000011170ull);
1870 }
1871 #else
1872 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
1873 #endif
1874 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1875 #define CVMX_PEXP_SLI_PKT_INSTR_ENB CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC()
CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void)1876 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void)
1877 {
1878 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1879 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_ENB not supported on this chip\n");
1880 return CVMX_ADD_IO_SEG(0x00011F0000011000ull);
1881 }
1882 #else
1883 #define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
1884 #endif
1885 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1886 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC()
CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void)1887 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
1888 {
1889 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1890 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
1891 return CVMX_ADD_IO_SEG(0x00011F00000111A0ull);
1892 }
1893 #else
1894 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
1895 #endif
1896 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1897 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC()
CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void)1898 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void)
1899 {
1900 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1901 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_SIZE not supported on this chip\n");
1902 return CVMX_ADD_IO_SEG(0x00011F0000011020ull);
1903 }
1904 #else
1905 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
1906 #endif
1907 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1908 #define CVMX_PEXP_SLI_PKT_INT_LEVELS CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC()
CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void)1909 static inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void)
1910 {
1911 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1912 cvmx_warn("CVMX_PEXP_SLI_PKT_INT_LEVELS not supported on this chip\n");
1913 return CVMX_ADD_IO_SEG(0x00011F0000011120ull);
1914 }
1915 #else
1916 #define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
1917 #endif
1918 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1919 #define CVMX_PEXP_SLI_PKT_IN_BP CVMX_PEXP_SLI_PKT_IN_BP_FUNC()
CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void)1920 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void)
1921 {
1922 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1923 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_BP not supported on this chip\n");
1924 return CVMX_ADD_IO_SEG(0x00011F0000011210ull);
1925 }
1926 #else
1927 #define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
1928 #endif
1929 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)1930 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
1931 {
1932 if (!(
1933 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1934 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1935 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1936 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1937 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1938 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
1939 return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16;
1940 }
1941 #else
1942 #define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
1943 #endif
1944 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1945 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC()
CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)1946 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
1947 {
1948 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1949 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
1950 return CVMX_ADD_IO_SEG(0x00011F0000011200ull);
1951 }
1952 #else
1953 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
1954 #endif
1955 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1956 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC()
CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void)1957 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void)
1958 {
1959 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1960 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
1961 return CVMX_ADD_IO_SEG(0x00011F00000111B0ull);
1962 }
1963 #else
1964 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
1965 #endif
1966 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1967 #define CVMX_PEXP_SLI_PKT_IPTR CVMX_PEXP_SLI_PKT_IPTR_FUNC()
CVMX_PEXP_SLI_PKT_IPTR_FUNC(void)1968 static inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void)
1969 {
1970 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1971 cvmx_warn("CVMX_PEXP_SLI_PKT_IPTR not supported on this chip\n");
1972 return CVMX_ADD_IO_SEG(0x00011F0000011070ull);
1973 }
1974 #else
1975 #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
1976 #endif
1977 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1978 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC()
CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)1979 static inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)
1980 {
1981 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1982 cvmx_warn("CVMX_PEXP_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
1983 return CVMX_ADD_IO_SEG(0x00011F0000011180ull);
1984 }
1985 #else
1986 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
1987 #endif
1988 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1989 #define CVMX_PEXP_SLI_PKT_OUT_BMODE CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC()
CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void)1990 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void)
1991 {
1992 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1993 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BMODE not supported on this chip\n");
1994 return CVMX_ADD_IO_SEG(0x00011F00000110D0ull);
1995 }
1996 #else
1997 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
1998 #endif
1999 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2000 #define CVMX_PEXP_SLI_PKT_OUT_BP_EN CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC()
CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC(void)2001 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC(void)
2002 {
2003 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
2004 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BP_EN not supported on this chip\n");
2005 return CVMX_ADD_IO_SEG(0x00011F0000011240ull);
2006 }
2007 #else
2008 #define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
2009 #endif
2010 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2011 #define CVMX_PEXP_SLI_PKT_OUT_ENB CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC()
CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void)2012 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void)
2013 {
2014 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2015 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_ENB not supported on this chip\n");
2016 return CVMX_ADD_IO_SEG(0x00011F0000011010ull);
2017 }
2018 #else
2019 #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
2020 #endif
2021 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2022 #define CVMX_PEXP_SLI_PKT_PCIE_PORT CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC()
CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void)2023 static inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void)
2024 {
2025 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2026 cvmx_warn("CVMX_PEXP_SLI_PKT_PCIE_PORT not supported on this chip\n");
2027 return CVMX_ADD_IO_SEG(0x00011F00000110E0ull);
2028 }
2029 #else
2030 #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
2031 #endif
2032 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2033 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC()
CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void)2034 static inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void)
2035 {
2036 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2037 cvmx_warn("CVMX_PEXP_SLI_PKT_PORT_IN_RST not supported on this chip\n");
2038 return CVMX_ADD_IO_SEG(0x00011F00000111F0ull);
2039 }
2040 #else
2041 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
2042 #endif
2043 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2044 #define CVMX_PEXP_SLI_PKT_SLIST_ES CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC()
CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void)2045 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void)
2046 {
2047 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2048 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ES not supported on this chip\n");
2049 return CVMX_ADD_IO_SEG(0x00011F0000011050ull);
2050 }
2051 #else
2052 #define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
2053 #endif
2054 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2055 #define CVMX_PEXP_SLI_PKT_SLIST_NS CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC()
CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void)2056 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void)
2057 {
2058 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2059 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_NS not supported on this chip\n");
2060 return CVMX_ADD_IO_SEG(0x00011F0000011040ull);
2061 }
2062 #else
2063 #define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
2064 #endif
2065 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2066 #define CVMX_PEXP_SLI_PKT_SLIST_ROR CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC()
CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void)2067 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void)
2068 {
2069 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2070 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ROR not supported on this chip\n");
2071 return CVMX_ADD_IO_SEG(0x00011F0000011030ull);
2072 }
2073 #else
2074 #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
2075 #endif
2076 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2077 #define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC()
CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)2078 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)
2079 {
2080 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2081 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT not supported on this chip\n");
2082 return CVMX_ADD_IO_SEG(0x00011F0000011140ull);
2083 }
2084 #else
2085 #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
2086 #endif
2087 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2088 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC()
CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void)2089 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void)
2090 {
2091 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2092 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
2093 return CVMX_ADD_IO_SEG(0x00011F0000011160ull);
2094 }
2095 #else
2096 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
2097 #endif
2098 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_PORTX_PKIND(unsigned long offset)2099 static inline uint64_t CVMX_PEXP_SLI_PORTX_PKIND(unsigned long offset)
2100 {
2101 if (!(
2102 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
2103 cvmx_warn("CVMX_PEXP_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
2104 return CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16;
2105 }
2106 #else
2107 #define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
2108 #endif
2109 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)2110 static inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
2111 {
2112 if (!(
2113 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
2114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
2115 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
2116 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
2117 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
2118 cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
2119 return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16;
2120 }
2121 #else
2122 #define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
2123 #endif
2124 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2125 #define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC()
CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)2126 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)
2127 {
2128 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2129 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_1 not supported on this chip\n");
2130 return CVMX_ADD_IO_SEG(0x00011F00000103C0ull);
2131 }
2132 #else
2133 #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
2134 #endif
2135 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2136 #define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC()
CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)2137 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)
2138 {
2139 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2140 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_2 not supported on this chip\n");
2141 return CVMX_ADD_IO_SEG(0x00011F00000103D0ull);
2142 }
2143 #else
2144 #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
2145 #endif
2146 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2147 #define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC()
CVMX_PEXP_SLI_STATE1_FUNC(void)2148 static inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void)
2149 {
2150 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2151 cvmx_warn("CVMX_PEXP_SLI_STATE1 not supported on this chip\n");
2152 return CVMX_ADD_IO_SEG(0x00011F0000010620ull);
2153 }
2154 #else
2155 #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
2156 #endif
2157 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2158 #define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC()
CVMX_PEXP_SLI_STATE2_FUNC(void)2159 static inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void)
2160 {
2161 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2162 cvmx_warn("CVMX_PEXP_SLI_STATE2 not supported on this chip\n");
2163 return CVMX_ADD_IO_SEG(0x00011F0000010630ull);
2164 }
2165 #else
2166 #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
2167 #endif
2168 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2169 #define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC()
CVMX_PEXP_SLI_STATE3_FUNC(void)2170 static inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void)
2171 {
2172 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2173 cvmx_warn("CVMX_PEXP_SLI_STATE3 not supported on this chip\n");
2174 return CVMX_ADD_IO_SEG(0x00011F0000010640ull);
2175 }
2176 #else
2177 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
2178 #endif
2179 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2180 #define CVMX_PEXP_SLI_TX_PIPE CVMX_PEXP_SLI_TX_PIPE_FUNC()
CVMX_PEXP_SLI_TX_PIPE_FUNC(void)2181 static inline uint64_t CVMX_PEXP_SLI_TX_PIPE_FUNC(void)
2182 {
2183 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
2184 cvmx_warn("CVMX_PEXP_SLI_TX_PIPE not supported on this chip\n");
2185 return CVMX_ADD_IO_SEG(0x00011F0000011230ull);
2186 }
2187 #else
2188 #define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
2189 #endif
2190 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2191 #define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC()
CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void)2192 static inline uint64_t CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void)
2193 {
2194 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2195 cvmx_warn("CVMX_PEXP_SLI_WINDOW_CTL not supported on this chip\n");
2196 return CVMX_ADD_IO_SEG(0x00011F00000102E0ull);
2197 }
2198 #else
2199 #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
2200 #endif
2201
2202 #endif
2203