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39
40
41 /**
42 * cvmx-npi-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon npi.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_NPI_DEFS_H__
53 #define __CVMX_NPI_DEFS_H__
54
55 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
56 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
57 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
58 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
59 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)60 static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)
61 {
62 if (!(
63 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
64 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
65 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
66 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
67 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
68 cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset);
69 return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16;
70 }
71 #else
72 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
73 #endif
74 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
75 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
76 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
77 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
78 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)79 static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)
80 {
81 if (!(
82 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
83 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
85 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
87 cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset);
88 return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8;
89 }
90 #else
91 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
92 #endif
93 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
94 #define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC()
CVMX_NPI_BIST_STATUS_FUNC(void)95 static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void)
96 {
97 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
98 cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n");
99 return CVMX_ADD_IO_SEG(0x00011F00000003F8ull);
100 }
101 #else
102 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
103 #endif
104 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
105 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
106 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
107 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)109 static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)
110 {
111 if (!(
112 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
113 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
114 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
115 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
116 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
117 cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset);
118 return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8;
119 }
120 #else
121 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
122 #endif
123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
124 #define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC()
CVMX_NPI_COMP_CTL_FUNC(void)125 static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void)
126 {
127 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
128 cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n");
129 return CVMX_ADD_IO_SEG(0x00011F0000000218ull);
130 }
131 #else
132 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
133 #endif
134 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
135 #define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC()
CVMX_NPI_CTL_STATUS_FUNC(void)136 static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void)
137 {
138 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
139 cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n");
140 return CVMX_ADD_IO_SEG(0x00011F0000000010ull);
141 }
142 #else
143 #define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
144 #endif
145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
146 #define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC()
CVMX_NPI_DBG_SELECT_FUNC(void)147 static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void)
148 {
149 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
150 cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n");
151 return CVMX_ADD_IO_SEG(0x00011F0000000008ull);
152 }
153 #else
154 #define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
155 #endif
156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
157 #define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC()
CVMX_NPI_DMA_CONTROL_FUNC(void)158 static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void)
159 {
160 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
161 cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n");
162 return CVMX_ADD_IO_SEG(0x00011F0000000128ull);
163 }
164 #else
165 #define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
166 #endif
167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
168 #define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC()
CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)169 static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)
170 {
171 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
172 cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n");
173 return CVMX_ADD_IO_SEG(0x00011F0000000148ull);
174 }
175 #else
176 #define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
177 #endif
178 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
179 #define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC()
CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)180 static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)
181 {
182 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
183 cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n");
184 return CVMX_ADD_IO_SEG(0x00011F0000000158ull);
185 }
186 #else
187 #define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
188 #endif
189 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
190 #define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC()
CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)191 static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)
192 {
193 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
194 cvmx_warn("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n");
195 return CVMX_ADD_IO_SEG(0x00011F0000000140ull);
196 }
197 #else
198 #define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
199 #endif
200 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
201 #define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC()
CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)202 static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)
203 {
204 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
205 cvmx_warn("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n");
206 return CVMX_ADD_IO_SEG(0x00011F0000000150ull);
207 }
208 #else
209 #define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
210 #endif
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 #define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC()
CVMX_NPI_HIGHP_DBELL_FUNC(void)213 static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void)
214 {
215 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
216 cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n");
217 return CVMX_ADD_IO_SEG(0x00011F0000000120ull);
218 }
219 #else
220 #define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
221 #endif
222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
223 #define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC()
CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)224 static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)
225 {
226 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
227 cvmx_warn("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n");
228 return CVMX_ADD_IO_SEG(0x00011F0000000110ull);
229 }
230 #else
231 #define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
232 #endif
233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
234 #define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC()
CVMX_NPI_INPUT_CONTROL_FUNC(void)235 static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void)
236 {
237 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
238 cvmx_warn("CVMX_NPI_INPUT_CONTROL not supported on this chip\n");
239 return CVMX_ADD_IO_SEG(0x00011F0000000138ull);
240 }
241 #else
242 #define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
243 #endif
244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
245 #define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC()
CVMX_NPI_INT_ENB_FUNC(void)246 static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void)
247 {
248 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
249 cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n");
250 return CVMX_ADD_IO_SEG(0x00011F0000000020ull);
251 }
252 #else
253 #define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
254 #endif
255 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
256 #define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC()
CVMX_NPI_INT_SUM_FUNC(void)257 static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void)
258 {
259 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
260 cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n");
261 return CVMX_ADD_IO_SEG(0x00011F0000000018ull);
262 }
263 #else
264 #define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
265 #endif
266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
267 #define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC()
CVMX_NPI_LOWP_DBELL_FUNC(void)268 static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void)
269 {
270 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
271 cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n");
272 return CVMX_ADD_IO_SEG(0x00011F0000000118ull);
273 }
274 #else
275 #define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
276 #endif
277 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
278 #define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC()
CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)279 static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)
280 {
281 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
282 cvmx_warn("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n");
283 return CVMX_ADD_IO_SEG(0x00011F0000000108ull);
284 }
285 #else
286 #define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
287 #endif
288 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
289 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
290 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
291 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)293 static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)
294 {
295 if (!(
296 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 3) && (offset <= 6)))) ||
297 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 3) && (offset <= 6)))) ||
298 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 3) && (offset <= 6)))) ||
299 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 3) && (offset <= 6)))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 3) && (offset <= 6))))))
301 cvmx_warn("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
302 return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3;
303 }
304 #else
305 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
306 #endif
307 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
308 #define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC()
CVMX_NPI_MSI_RCV_FUNC(void)309 static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void)
310 {
311 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
312 cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n");
313 return 0x0000000000000190ull;
314 }
315 #else
316 #define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
317 #endif
318 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
319 #define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC()
CVMX_NPI_NPI_MSI_RCV_FUNC(void)320 static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void)
321 {
322 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
323 cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n");
324 return CVMX_ADD_IO_SEG(0x00011F0000001190ull);
325 }
326 #else
327 #define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
328 #endif
329 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
330 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
331 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
332 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
333 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)334 static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)
335 {
336 if (!(
337 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
338 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
339 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
340 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
341 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
342 cvmx_warn("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n", offset);
343 return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8;
344 }
345 #else
346 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
347 #endif
348 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
349 #define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC()
CVMX_NPI_OUTPUT_CONTROL_FUNC(void)350 static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void)
351 {
352 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
353 cvmx_warn("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n");
354 return CVMX_ADD_IO_SEG(0x00011F0000000100ull);
355 }
356 #else
357 #define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
358 #endif
359 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
360 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
361 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
362 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
363 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
364 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
365 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
366 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
367 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
368 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
369 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
370 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
371 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
372 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
373 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
374 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
375 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)376 static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)
377 {
378 if (!(
379 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
380 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
381 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
382 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
383 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
384 cvmx_warn("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
385 return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4;
386 }
387 #else
388 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
389 #endif
390 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
391 #define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC()
CVMX_NPI_PCI_BIST_REG_FUNC(void)392 static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void)
393 {
394 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
395 cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n");
396 return CVMX_ADD_IO_SEG(0x00011F00000011C0ull);
397 }
398 #else
399 #define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
400 #endif
401 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
402 #define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC()
CVMX_NPI_PCI_BURST_SIZE_FUNC(void)403 static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void)
404 {
405 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
406 cvmx_warn("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n");
407 return CVMX_ADD_IO_SEG(0x00011F00000000D8ull);
408 }
409 #else
410 #define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
411 #endif
412 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
413 #define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC()
CVMX_NPI_PCI_CFG00_FUNC(void)414 static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void)
415 {
416 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
417 cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n");
418 return CVMX_ADD_IO_SEG(0x00011F0000001800ull);
419 }
420 #else
421 #define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
422 #endif
423 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
424 #define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC()
CVMX_NPI_PCI_CFG01_FUNC(void)425 static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void)
426 {
427 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
428 cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n");
429 return CVMX_ADD_IO_SEG(0x00011F0000001804ull);
430 }
431 #else
432 #define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
433 #endif
434 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
435 #define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC()
CVMX_NPI_PCI_CFG02_FUNC(void)436 static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void)
437 {
438 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
439 cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n");
440 return CVMX_ADD_IO_SEG(0x00011F0000001808ull);
441 }
442 #else
443 #define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
444 #endif
445 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
446 #define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC()
CVMX_NPI_PCI_CFG03_FUNC(void)447 static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void)
448 {
449 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
450 cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n");
451 return CVMX_ADD_IO_SEG(0x00011F000000180Cull);
452 }
453 #else
454 #define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
455 #endif
456 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
457 #define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC()
CVMX_NPI_PCI_CFG04_FUNC(void)458 static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void)
459 {
460 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
461 cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n");
462 return CVMX_ADD_IO_SEG(0x00011F0000001810ull);
463 }
464 #else
465 #define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
466 #endif
467 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
468 #define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC()
CVMX_NPI_PCI_CFG05_FUNC(void)469 static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void)
470 {
471 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
472 cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n");
473 return CVMX_ADD_IO_SEG(0x00011F0000001814ull);
474 }
475 #else
476 #define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
477 #endif
478 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
479 #define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC()
CVMX_NPI_PCI_CFG06_FUNC(void)480 static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void)
481 {
482 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
483 cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n");
484 return CVMX_ADD_IO_SEG(0x00011F0000001818ull);
485 }
486 #else
487 #define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
488 #endif
489 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
490 #define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC()
CVMX_NPI_PCI_CFG07_FUNC(void)491 static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void)
492 {
493 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
494 cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n");
495 return CVMX_ADD_IO_SEG(0x00011F000000181Cull);
496 }
497 #else
498 #define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
499 #endif
500 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
501 #define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC()
CVMX_NPI_PCI_CFG08_FUNC(void)502 static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void)
503 {
504 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
505 cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n");
506 return CVMX_ADD_IO_SEG(0x00011F0000001820ull);
507 }
508 #else
509 #define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
510 #endif
511 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
512 #define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC()
CVMX_NPI_PCI_CFG09_FUNC(void)513 static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void)
514 {
515 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
516 cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n");
517 return CVMX_ADD_IO_SEG(0x00011F0000001824ull);
518 }
519 #else
520 #define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
521 #endif
522 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
523 #define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC()
CVMX_NPI_PCI_CFG10_FUNC(void)524 static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void)
525 {
526 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
527 cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n");
528 return CVMX_ADD_IO_SEG(0x00011F0000001828ull);
529 }
530 #else
531 #define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
532 #endif
533 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
534 #define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC()
CVMX_NPI_PCI_CFG11_FUNC(void)535 static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void)
536 {
537 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
538 cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n");
539 return CVMX_ADD_IO_SEG(0x00011F000000182Cull);
540 }
541 #else
542 #define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
543 #endif
544 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
545 #define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC()
CVMX_NPI_PCI_CFG12_FUNC(void)546 static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void)
547 {
548 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
549 cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n");
550 return CVMX_ADD_IO_SEG(0x00011F0000001830ull);
551 }
552 #else
553 #define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
554 #endif
555 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
556 #define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC()
CVMX_NPI_PCI_CFG13_FUNC(void)557 static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void)
558 {
559 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
560 cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n");
561 return CVMX_ADD_IO_SEG(0x00011F0000001834ull);
562 }
563 #else
564 #define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
565 #endif
566 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
567 #define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC()
CVMX_NPI_PCI_CFG15_FUNC(void)568 static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void)
569 {
570 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
571 cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n");
572 return CVMX_ADD_IO_SEG(0x00011F000000183Cull);
573 }
574 #else
575 #define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
576 #endif
577 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
578 #define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC()
CVMX_NPI_PCI_CFG16_FUNC(void)579 static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void)
580 {
581 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
582 cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n");
583 return CVMX_ADD_IO_SEG(0x00011F0000001840ull);
584 }
585 #else
586 #define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
587 #endif
588 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
589 #define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC()
CVMX_NPI_PCI_CFG17_FUNC(void)590 static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void)
591 {
592 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
593 cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n");
594 return CVMX_ADD_IO_SEG(0x00011F0000001844ull);
595 }
596 #else
597 #define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
598 #endif
599 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
600 #define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC()
CVMX_NPI_PCI_CFG18_FUNC(void)601 static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void)
602 {
603 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
604 cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n");
605 return CVMX_ADD_IO_SEG(0x00011F0000001848ull);
606 }
607 #else
608 #define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
609 #endif
610 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
611 #define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC()
CVMX_NPI_PCI_CFG19_FUNC(void)612 static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void)
613 {
614 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
615 cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n");
616 return CVMX_ADD_IO_SEG(0x00011F000000184Cull);
617 }
618 #else
619 #define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
620 #endif
621 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
622 #define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC()
CVMX_NPI_PCI_CFG20_FUNC(void)623 static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void)
624 {
625 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
626 cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n");
627 return CVMX_ADD_IO_SEG(0x00011F0000001850ull);
628 }
629 #else
630 #define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
631 #endif
632 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
633 #define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC()
CVMX_NPI_PCI_CFG21_FUNC(void)634 static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void)
635 {
636 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
637 cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n");
638 return CVMX_ADD_IO_SEG(0x00011F0000001854ull);
639 }
640 #else
641 #define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
642 #endif
643 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
644 #define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC()
CVMX_NPI_PCI_CFG22_FUNC(void)645 static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void)
646 {
647 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
648 cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n");
649 return CVMX_ADD_IO_SEG(0x00011F0000001858ull);
650 }
651 #else
652 #define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
653 #endif
654 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
655 #define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC()
CVMX_NPI_PCI_CFG56_FUNC(void)656 static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void)
657 {
658 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
659 cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n");
660 return CVMX_ADD_IO_SEG(0x00011F00000018E0ull);
661 }
662 #else
663 #define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
664 #endif
665 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
666 #define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC()
CVMX_NPI_PCI_CFG57_FUNC(void)667 static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void)
668 {
669 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
670 cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n");
671 return CVMX_ADD_IO_SEG(0x00011F00000018E4ull);
672 }
673 #else
674 #define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
675 #endif
676 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
677 #define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC()
CVMX_NPI_PCI_CFG58_FUNC(void)678 static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void)
679 {
680 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
681 cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n");
682 return CVMX_ADD_IO_SEG(0x00011F00000018E8ull);
683 }
684 #else
685 #define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
686 #endif
687 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
688 #define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC()
CVMX_NPI_PCI_CFG59_FUNC(void)689 static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void)
690 {
691 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
692 cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n");
693 return CVMX_ADD_IO_SEG(0x00011F00000018ECull);
694 }
695 #else
696 #define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
697 #endif
698 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
699 #define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC()
CVMX_NPI_PCI_CFG60_FUNC(void)700 static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void)
701 {
702 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
703 cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n");
704 return CVMX_ADD_IO_SEG(0x00011F00000018F0ull);
705 }
706 #else
707 #define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
708 #endif
709 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
710 #define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC()
CVMX_NPI_PCI_CFG61_FUNC(void)711 static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void)
712 {
713 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
714 cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n");
715 return CVMX_ADD_IO_SEG(0x00011F00000018F4ull);
716 }
717 #else
718 #define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
719 #endif
720 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
721 #define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC()
CVMX_NPI_PCI_CFG62_FUNC(void)722 static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void)
723 {
724 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
725 cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n");
726 return CVMX_ADD_IO_SEG(0x00011F00000018F8ull);
727 }
728 #else
729 #define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
730 #endif
731 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
732 #define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC()
CVMX_NPI_PCI_CFG63_FUNC(void)733 static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void)
734 {
735 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
736 cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n");
737 return CVMX_ADD_IO_SEG(0x00011F00000018FCull);
738 }
739 #else
740 #define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
741 #endif
742 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
743 #define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC()
CVMX_NPI_PCI_CNT_REG_FUNC(void)744 static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void)
745 {
746 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
747 cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n");
748 return CVMX_ADD_IO_SEG(0x00011F00000011B8ull);
749 }
750 #else
751 #define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
752 #endif
753 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
754 #define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC()
CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)755 static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)
756 {
757 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
758 cvmx_warn("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n");
759 return CVMX_ADD_IO_SEG(0x00011F000000118Cull);
760 }
761 #else
762 #define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
763 #endif
764 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
765 #define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC()
CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)766 static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)
767 {
768 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
769 cvmx_warn("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n");
770 return CVMX_ADD_IO_SEG(0x00011F0000000130ull);
771 }
772 #else
773 #define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
774 #endif
775 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
776 #define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC()
CVMX_NPI_PCI_INT_ENB2_FUNC(void)777 static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void)
778 {
779 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
780 cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n");
781 return CVMX_ADD_IO_SEG(0x00011F00000011A0ull);
782 }
783 #else
784 #define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
785 #endif
786 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
787 #define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC()
CVMX_NPI_PCI_INT_SUM2_FUNC(void)788 static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void)
789 {
790 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
791 cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n");
792 return CVMX_ADD_IO_SEG(0x00011F0000001198ull);
793 }
794 #else
795 #define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
796 #endif
797 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
798 #define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC()
CVMX_NPI_PCI_READ_CMD_FUNC(void)799 static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void)
800 {
801 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
802 cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n");
803 return CVMX_ADD_IO_SEG(0x00011F0000000048ull);
804 }
805 #else
806 #define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
807 #endif
808 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
809 #define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC()
CVMX_NPI_PCI_READ_CMD_6_FUNC(void)810 static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void)
811 {
812 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
813 cvmx_warn("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n");
814 return CVMX_ADD_IO_SEG(0x00011F0000001180ull);
815 }
816 #else
817 #define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
818 #endif
819 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
820 #define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC()
CVMX_NPI_PCI_READ_CMD_C_FUNC(void)821 static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void)
822 {
823 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
824 cvmx_warn("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n");
825 return CVMX_ADD_IO_SEG(0x00011F0000001184ull);
826 }
827 #else
828 #define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
829 #endif
830 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
831 #define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC()
CVMX_NPI_PCI_READ_CMD_E_FUNC(void)832 static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void)
833 {
834 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
835 cvmx_warn("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n");
836 return CVMX_ADD_IO_SEG(0x00011F0000001188ull);
837 }
838 #else
839 #define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
840 #endif
841 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
842 #define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC()
CVMX_NPI_PCI_SCM_REG_FUNC(void)843 static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void)
844 {
845 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
846 cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n");
847 return CVMX_ADD_IO_SEG(0x00011F00000011A8ull);
848 }
849 #else
850 #define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
851 #endif
852 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
853 #define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC()
CVMX_NPI_PCI_TSR_REG_FUNC(void)854 static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void)
855 {
856 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
857 cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n");
858 return CVMX_ADD_IO_SEG(0x00011F00000011B0ull);
859 }
860 #else
861 #define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
862 #endif
863 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
864 #define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC()
CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)865 static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)
866 {
867 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
868 cvmx_warn("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n");
869 return CVMX_ADD_IO_SEG(0x00011F00000001F8ull);
870 }
871 #else
872 #define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
873 #endif
874 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
875 #define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC()
CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)876 static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)
877 {
878 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
879 cvmx_warn("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n");
880 return CVMX_ADD_IO_SEG(0x00011F0000000200ull);
881 }
882 #else
883 #define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
884 #endif
885 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
886 #define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC()
CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)887 static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)
888 {
889 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
890 cvmx_warn("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n");
891 return CVMX_ADD_IO_SEG(0x00011F0000000208ull);
892 }
893 #else
894 #define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
895 #endif
896 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
897 #define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC()
CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)898 static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)
899 {
900 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
901 cvmx_warn("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n");
902 return CVMX_ADD_IO_SEG(0x00011F0000000210ull);
903 }
904 #else
905 #define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
906 #endif
907 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
908 #define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC()
CVMX_NPI_PORT_BP_CONTROL_FUNC(void)909 static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void)
910 {
911 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
912 cvmx_warn("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n");
913 return CVMX_ADD_IO_SEG(0x00011F00000001F0ull);
914 }
915 #else
916 #define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
917 #endif
918 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)919 static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)
920 {
921 if (!(
922 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
923 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
924 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
925 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
926 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
927 cvmx_warn("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n", offset);
928 return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8;
929 }
930 #else
931 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
932 #endif
933 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)934 static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)
935 {
936 if (!(
937 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
938 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
939 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
940 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
941 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
942 cvmx_warn("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n", offset);
943 return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8;
944 }
945 #else
946 #define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
947 #endif
948 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)949 static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)
950 {
951 if (!(
952 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
953 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
954 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
955 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
956 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
957 cvmx_warn("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n", offset);
958 return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8;
959 }
960 #else
961 #define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
962 #endif
963 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)964 static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)
965 {
966 if (!(
967 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
968 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
969 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
970 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
971 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
972 cvmx_warn("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n", offset);
973 return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8;
974 }
975 #else
976 #define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
977 #endif
978 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
979 #define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC()
CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)980 static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)
981 {
982 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
983 cvmx_warn("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n");
984 return CVMX_ADD_IO_SEG(0x00011F0000000000ull);
985 }
986 #else
987 #define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
988 #endif
989 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
990 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
991 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
992 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
993 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPI_SIZE_INPUTX(unsigned long offset)994 static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset)
995 {
996 if (!(
997 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
998 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
999 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
1000 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1001 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
1002 cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n", offset);
1003 return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16;
1004 }
1005 #else
1006 #define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
1007 #endif
1008 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1009 #define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC()
CVMX_NPI_WIN_READ_TO_FUNC(void)1010 static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
1011 {
1012 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
1013 cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n");
1014 return CVMX_ADD_IO_SEG(0x00011F00000001E0ull);
1015 }
1016 #else
1017 #define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
1018 #endif
1019
1020 /**
1021 * cvmx_npi_base_addr_input#
1022 *
1023 * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register
1024 *
1025 * The address to start reading Instructions from for Input-0.
1026 */
1027 union cvmx_npi_base_addr_inputx {
1028 uint64_t u64;
1029 struct cvmx_npi_base_addr_inputx_s {
1030 #ifdef __BIG_ENDIAN_BITFIELD
1031 uint64_t baddr : 61; /**< The address to read Instruction from for output 0.
1032 This address is 8-byte aligned, for this reason
1033 address bits [2:0] will always be zero. */
1034 uint64_t reserved_0_2 : 3;
1035 #else
1036 uint64_t reserved_0_2 : 3;
1037 uint64_t baddr : 61;
1038 #endif
1039 } s;
1040 struct cvmx_npi_base_addr_inputx_s cn30xx;
1041 struct cvmx_npi_base_addr_inputx_s cn31xx;
1042 struct cvmx_npi_base_addr_inputx_s cn38xx;
1043 struct cvmx_npi_base_addr_inputx_s cn38xxp2;
1044 struct cvmx_npi_base_addr_inputx_s cn50xx;
1045 struct cvmx_npi_base_addr_inputx_s cn58xx;
1046 struct cvmx_npi_base_addr_inputx_s cn58xxp1;
1047 };
1048 typedef union cvmx_npi_base_addr_inputx cvmx_npi_base_addr_inputx_t;
1049
1050 /**
1051 * cvmx_npi_base_addr_output#
1052 *
1053 * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register
1054 *
1055 * The address to start reading Instructions from for Output-0.
1056 */
1057 union cvmx_npi_base_addr_outputx {
1058 uint64_t u64;
1059 struct cvmx_npi_base_addr_outputx_s {
1060 #ifdef __BIG_ENDIAN_BITFIELD
1061 uint64_t baddr : 61; /**< The address to read Instruction from for output 0.
1062 This address is 8-byte aligned, for this reason
1063 address bits [2:0] will always be zero. */
1064 uint64_t reserved_0_2 : 3;
1065 #else
1066 uint64_t reserved_0_2 : 3;
1067 uint64_t baddr : 61;
1068 #endif
1069 } s;
1070 struct cvmx_npi_base_addr_outputx_s cn30xx;
1071 struct cvmx_npi_base_addr_outputx_s cn31xx;
1072 struct cvmx_npi_base_addr_outputx_s cn38xx;
1073 struct cvmx_npi_base_addr_outputx_s cn38xxp2;
1074 struct cvmx_npi_base_addr_outputx_s cn50xx;
1075 struct cvmx_npi_base_addr_outputx_s cn58xx;
1076 struct cvmx_npi_base_addr_outputx_s cn58xxp1;
1077 };
1078 typedef union cvmx_npi_base_addr_outputx cvmx_npi_base_addr_outputx_t;
1079
1080 /**
1081 * cvmx_npi_bist_status
1082 *
1083 * NPI_BIST_STATUS = NPI's BIST Status Register
1084 *
1085 * Results from BIST runs of NPI's memories.
1086 */
1087 union cvmx_npi_bist_status {
1088 uint64_t u64;
1089 struct cvmx_npi_bist_status_s {
1090 #ifdef __BIG_ENDIAN_BITFIELD
1091 uint64_t reserved_20_63 : 44;
1092 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */
1093 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */
1094 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */
1095 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */
1096 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */
1097 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */
1098 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */
1099 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */
1100 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */
1101 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */
1102 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */
1103 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */
1104 uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */
1105 uint64_t pof2_bs : 1; /**< BIST Status for the pof2_fifo */
1106 uint64_t pof3_bs : 1; /**< BIST Status for the pof3_fifo */
1107 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */
1108 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */
1109 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */
1110 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */
1111 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */
1112 #else
1113 uint64_t dpi_bs : 1;
1114 uint64_t pdf_bs : 1;
1115 uint64_t dob_bs : 1;
1116 uint64_t nus_bs : 1;
1117 uint64_t pos_bs : 1;
1118 uint64_t pof3_bs : 1;
1119 uint64_t pof2_bs : 1;
1120 uint64_t pof1_bs : 1;
1121 uint64_t pof0_bs : 1;
1122 uint64_t pig_bs : 1;
1123 uint64_t pgf_bs : 1;
1124 uint64_t rdnl_bs : 1;
1125 uint64_t pcad_bs : 1;
1126 uint64_t pcac_bs : 1;
1127 uint64_t rdn_bs : 1;
1128 uint64_t pcn_bs : 1;
1129 uint64_t pcnc_bs : 1;
1130 uint64_t rdp_bs : 1;
1131 uint64_t dif_bs : 1;
1132 uint64_t csr_bs : 1;
1133 uint64_t reserved_20_63 : 44;
1134 #endif
1135 } s;
1136 struct cvmx_npi_bist_status_cn30xx {
1137 #ifdef __BIG_ENDIAN_BITFIELD
1138 uint64_t reserved_20_63 : 44;
1139 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */
1140 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */
1141 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */
1142 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */
1143 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */
1144 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */
1145 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */
1146 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */
1147 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */
1148 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */
1149 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */
1150 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */
1151 uint64_t reserved_5_7 : 3;
1152 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */
1153 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */
1154 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */
1155 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */
1156 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */
1157 #else
1158 uint64_t dpi_bs : 1;
1159 uint64_t pdf_bs : 1;
1160 uint64_t dob_bs : 1;
1161 uint64_t nus_bs : 1;
1162 uint64_t pos_bs : 1;
1163 uint64_t reserved_5_7 : 3;
1164 uint64_t pof0_bs : 1;
1165 uint64_t pig_bs : 1;
1166 uint64_t pgf_bs : 1;
1167 uint64_t rdnl_bs : 1;
1168 uint64_t pcad_bs : 1;
1169 uint64_t pcac_bs : 1;
1170 uint64_t rdn_bs : 1;
1171 uint64_t pcn_bs : 1;
1172 uint64_t pcnc_bs : 1;
1173 uint64_t rdp_bs : 1;
1174 uint64_t dif_bs : 1;
1175 uint64_t csr_bs : 1;
1176 uint64_t reserved_20_63 : 44;
1177 #endif
1178 } cn30xx;
1179 struct cvmx_npi_bist_status_s cn31xx;
1180 struct cvmx_npi_bist_status_s cn38xx;
1181 struct cvmx_npi_bist_status_s cn38xxp2;
1182 struct cvmx_npi_bist_status_cn50xx {
1183 #ifdef __BIG_ENDIAN_BITFIELD
1184 uint64_t reserved_20_63 : 44;
1185 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */
1186 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */
1187 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */
1188 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */
1189 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */
1190 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */
1191 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */
1192 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */
1193 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */
1194 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */
1195 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */
1196 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */
1197 uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */
1198 uint64_t reserved_5_6 : 2;
1199 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */
1200 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */
1201 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */
1202 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */
1203 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */
1204 #else
1205 uint64_t dpi_bs : 1;
1206 uint64_t pdf_bs : 1;
1207 uint64_t dob_bs : 1;
1208 uint64_t nus_bs : 1;
1209 uint64_t pos_bs : 1;
1210 uint64_t reserved_5_6 : 2;
1211 uint64_t pof1_bs : 1;
1212 uint64_t pof0_bs : 1;
1213 uint64_t pig_bs : 1;
1214 uint64_t pgf_bs : 1;
1215 uint64_t rdnl_bs : 1;
1216 uint64_t pcad_bs : 1;
1217 uint64_t pcac_bs : 1;
1218 uint64_t rdn_bs : 1;
1219 uint64_t pcn_bs : 1;
1220 uint64_t pcnc_bs : 1;
1221 uint64_t rdp_bs : 1;
1222 uint64_t dif_bs : 1;
1223 uint64_t csr_bs : 1;
1224 uint64_t reserved_20_63 : 44;
1225 #endif
1226 } cn50xx;
1227 struct cvmx_npi_bist_status_s cn58xx;
1228 struct cvmx_npi_bist_status_s cn58xxp1;
1229 };
1230 typedef union cvmx_npi_bist_status cvmx_npi_bist_status_t;
1231
1232 /**
1233 * cvmx_npi_buff_size_output#
1234 *
1235 * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0
1236 *
1237 * The size in bytes of the Data Bufffer and Information Buffer for output 0.
1238 */
1239 union cvmx_npi_buff_size_outputx {
1240 uint64_t u64;
1241 struct cvmx_npi_buff_size_outputx_s {
1242 #ifdef __BIG_ENDIAN_BITFIELD
1243 uint64_t reserved_23_63 : 41;
1244 uint64_t isize : 7; /**< The number of bytes to move to the Info-Pointer
1245 from the front of the packet.
1246 Legal values are 0-120. */
1247 uint64_t bsize : 16; /**< The size in bytes of the area pointed to by
1248 buffer pointer for output packet data. */
1249 #else
1250 uint64_t bsize : 16;
1251 uint64_t isize : 7;
1252 uint64_t reserved_23_63 : 41;
1253 #endif
1254 } s;
1255 struct cvmx_npi_buff_size_outputx_s cn30xx;
1256 struct cvmx_npi_buff_size_outputx_s cn31xx;
1257 struct cvmx_npi_buff_size_outputx_s cn38xx;
1258 struct cvmx_npi_buff_size_outputx_s cn38xxp2;
1259 struct cvmx_npi_buff_size_outputx_s cn50xx;
1260 struct cvmx_npi_buff_size_outputx_s cn58xx;
1261 struct cvmx_npi_buff_size_outputx_s cn58xxp1;
1262 };
1263 typedef union cvmx_npi_buff_size_outputx cvmx_npi_buff_size_outputx_t;
1264
1265 /**
1266 * cvmx_npi_comp_ctl
1267 *
1268 * NPI_COMP_CTL = PCI Compensation Control
1269 *
1270 * PCI Compensation Control
1271 */
1272 union cvmx_npi_comp_ctl {
1273 uint64_t u64;
1274 struct cvmx_npi_comp_ctl_s {
1275 #ifdef __BIG_ENDIAN_BITFIELD
1276 uint64_t reserved_10_63 : 54;
1277 uint64_t pctl : 5; /**< Bypass value for PCTL */
1278 uint64_t nctl : 5; /**< Bypass value for NCTL */
1279 #else
1280 uint64_t nctl : 5;
1281 uint64_t pctl : 5;
1282 uint64_t reserved_10_63 : 54;
1283 #endif
1284 } s;
1285 struct cvmx_npi_comp_ctl_s cn50xx;
1286 struct cvmx_npi_comp_ctl_s cn58xx;
1287 struct cvmx_npi_comp_ctl_s cn58xxp1;
1288 };
1289 typedef union cvmx_npi_comp_ctl cvmx_npi_comp_ctl_t;
1290
1291 /**
1292 * cvmx_npi_ctl_status
1293 *
1294 * NPI_CTL_STATUS = NPI's Control Status Register
1295 *
1296 * Contains control ans status for NPI.
1297 * Writes to this register are not ordered with writes/reads to the PCI Memory space.
1298 * To ensure that a write has completed the user must read the register before
1299 * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
1300 */
1301 union cvmx_npi_ctl_status {
1302 uint64_t u64;
1303 struct cvmx_npi_ctl_status_s {
1304 #ifdef __BIG_ENDIAN_BITFIELD
1305 uint64_t reserved_63_63 : 1;
1306 uint64_t chip_rev : 8; /**< The revision of the N3. */
1307 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window
1308 Registers are disabled. */
1309 uint64_t out3_enb : 1; /**< When asserted '1' the output3 engine is enabled.
1310 After enabling the values of the associated
1311 Address and Size Register should not be changed. */
1312 uint64_t out2_enb : 1; /**< When asserted '1' the output2 engine is enabled.
1313 After enabling the values of the associated
1314 Address and Size Register should not be changed. */
1315 uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled.
1316 After enabling the values of the associated
1317 Address and Size Register should not be changed. */
1318 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled.
1319 After enabling the values of the associated
1320 Address and Size Register should not be changed. */
1321 uint64_t ins3_enb : 1; /**< When asserted '1' the gather3 engine is enabled.
1322 After enabling the values of the associated
1323 Address and Size Register should not be changed. */
1324 uint64_t ins2_enb : 1; /**< When asserted '1' the gather2 engine is enabled.
1325 After enabling the values of the associated
1326 Address and Size Register should not be changed. */
1327 uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled.
1328 After enabling the values of the associated
1329 Address and Size Register should not be changed. */
1330 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled.
1331 After enabling the values of the associated
1332 Address and Size Register should not be changed. */
1333 uint64_t ins3_64b : 1; /**< When asserted '1' the instructions read by the
1334 gather3 engine are 64-Byte instructions, when
1335 de-asserted '0' instructions are 32-byte. */
1336 uint64_t ins2_64b : 1; /**< When asserted '1' the instructions read by the
1337 gather2 engine are 64-Byte instructions, when
1338 de-asserted '0' instructions are 32-byte. */
1339 uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the
1340 gather1 engine are 64-Byte instructions, when
1341 de-asserted '0' instructions are 32-byte. */
1342 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the
1343 gather0 engine are 64-Byte instructions, when
1344 de-asserted '0' instructions are 32-byte. */
1345 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in
1346 PNI address range 0x1000 - 0x17FF from the PCI. */
1347 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1348 from the L2C before sending additional access to
1349 the L2C from the PCI. */
1350 uint64_t reserved_37_39 : 3;
1351 uint64_t max_word : 5; /**< The maximum number of words to merge into a single
1352 write operation from the PPs to the PCI. Legal
1353 values are 1 to 32, where a '0' is treated as 32. */
1354 uint64_t reserved_10_31 : 22;
1355 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait
1356 no longer than the value of TIMER in eclks to
1357 merge additional writes from the PPs into 1
1358 large write. The values for this field is 1 to
1359 1024 where a value of '0' is treated as 1024. */
1360 #else
1361 uint64_t timer : 10;
1362 uint64_t reserved_10_31 : 22;
1363 uint64_t max_word : 5;
1364 uint64_t reserved_37_39 : 3;
1365 uint64_t wait_com : 1;
1366 uint64_t pci_wdis : 1;
1367 uint64_t ins0_64b : 1;
1368 uint64_t ins1_64b : 1;
1369 uint64_t ins2_64b : 1;
1370 uint64_t ins3_64b : 1;
1371 uint64_t ins0_enb : 1;
1372 uint64_t ins1_enb : 1;
1373 uint64_t ins2_enb : 1;
1374 uint64_t ins3_enb : 1;
1375 uint64_t out0_enb : 1;
1376 uint64_t out1_enb : 1;
1377 uint64_t out2_enb : 1;
1378 uint64_t out3_enb : 1;
1379 uint64_t dis_pniw : 1;
1380 uint64_t chip_rev : 8;
1381 uint64_t reserved_63_63 : 1;
1382 #endif
1383 } s;
1384 struct cvmx_npi_ctl_status_cn30xx {
1385 #ifdef __BIG_ENDIAN_BITFIELD
1386 uint64_t reserved_63_63 : 1;
1387 uint64_t chip_rev : 8; /**< The revision of the N3. */
1388 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window
1389 Registers are disabled. */
1390 uint64_t reserved_51_53 : 3;
1391 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled.
1392 After enabling the values of the associated
1393 Address and Size Register should not be changed. */
1394 uint64_t reserved_47_49 : 3;
1395 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled.
1396 After enabling the values of the associated
1397 Address and Size Register should not be changed. */
1398 uint64_t reserved_43_45 : 3;
1399 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the
1400 gather0 engine are 64-Byte instructions, when
1401 de-asserted '0' instructions are 32-byte. */
1402 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in
1403 PNI address range 0x1000 - 0x17FF from the PCI. */
1404 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1405 from the L2C before sending additional access to
1406 the L2C from the PCI. */
1407 uint64_t reserved_37_39 : 3;
1408 uint64_t max_word : 5; /**< The maximum number of words to merge into a single
1409 write operation from the PPs to the PCI. Legal
1410 values are 1 to 32, where a '0' is treated as 32. */
1411 uint64_t reserved_10_31 : 22;
1412 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait
1413 no longer than the value of TIMER in eclks to
1414 merge additional writes from the PPs into 1
1415 large write. The values for this field is 1 to
1416 1024 where a value of '0' is treated as 1024. */
1417 #else
1418 uint64_t timer : 10;
1419 uint64_t reserved_10_31 : 22;
1420 uint64_t max_word : 5;
1421 uint64_t reserved_37_39 : 3;
1422 uint64_t wait_com : 1;
1423 uint64_t pci_wdis : 1;
1424 uint64_t ins0_64b : 1;
1425 uint64_t reserved_43_45 : 3;
1426 uint64_t ins0_enb : 1;
1427 uint64_t reserved_47_49 : 3;
1428 uint64_t out0_enb : 1;
1429 uint64_t reserved_51_53 : 3;
1430 uint64_t dis_pniw : 1;
1431 uint64_t chip_rev : 8;
1432 uint64_t reserved_63_63 : 1;
1433 #endif
1434 } cn30xx;
1435 struct cvmx_npi_ctl_status_cn31xx {
1436 #ifdef __BIG_ENDIAN_BITFIELD
1437 uint64_t reserved_63_63 : 1;
1438 uint64_t chip_rev : 8; /**< The revision of the N3.
1439 0 => pass1.x, 1 => 2.0 */
1440 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window
1441 Registers are disabled. */
1442 uint64_t reserved_52_53 : 2;
1443 uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled.
1444 After enabling the values of the associated
1445 Address and Size Register should not be changed. */
1446 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled.
1447 After enabling the values of the associated
1448 Address and Size Register should not be changed. */
1449 uint64_t reserved_48_49 : 2;
1450 uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled.
1451 After enabling the values of the associated
1452 Address and Size Register should not be changed. */
1453 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled.
1454 After enabling the values of the associated
1455 Address and Size Register should not be changed. */
1456 uint64_t reserved_44_45 : 2;
1457 uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the
1458 gather1 engine are 64-Byte instructions, when
1459 de-asserted '0' instructions are 32-byte. */
1460 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the
1461 gather0 engine are 64-Byte instructions, when
1462 de-asserted '0' instructions are 32-byte. */
1463 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in
1464 PNI address range 0x1000 - 0x17FF from the PCI. */
1465 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1466 from the L2C before sending additional access to
1467 the L2C from the PCI. */
1468 uint64_t reserved_37_39 : 3;
1469 uint64_t max_word : 5; /**< The maximum number of words to merge into a single
1470 write operation from the PPs to the PCI. Legal
1471 values are 1 to 32, where a '0' is treated as 32. */
1472 uint64_t reserved_10_31 : 22;
1473 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait
1474 no longer than the value of TIMER in eclks to
1475 merge additional writes from the PPs into 1
1476 large write. The values for this field is 1 to
1477 1024 where a value of '0' is treated as 1024. */
1478 #else
1479 uint64_t timer : 10;
1480 uint64_t reserved_10_31 : 22;
1481 uint64_t max_word : 5;
1482 uint64_t reserved_37_39 : 3;
1483 uint64_t wait_com : 1;
1484 uint64_t pci_wdis : 1;
1485 uint64_t ins0_64b : 1;
1486 uint64_t ins1_64b : 1;
1487 uint64_t reserved_44_45 : 2;
1488 uint64_t ins0_enb : 1;
1489 uint64_t ins1_enb : 1;
1490 uint64_t reserved_48_49 : 2;
1491 uint64_t out0_enb : 1;
1492 uint64_t out1_enb : 1;
1493 uint64_t reserved_52_53 : 2;
1494 uint64_t dis_pniw : 1;
1495 uint64_t chip_rev : 8;
1496 uint64_t reserved_63_63 : 1;
1497 #endif
1498 } cn31xx;
1499 struct cvmx_npi_ctl_status_s cn38xx;
1500 struct cvmx_npi_ctl_status_s cn38xxp2;
1501 struct cvmx_npi_ctl_status_cn31xx cn50xx;
1502 struct cvmx_npi_ctl_status_s cn58xx;
1503 struct cvmx_npi_ctl_status_s cn58xxp1;
1504 };
1505 typedef union cvmx_npi_ctl_status cvmx_npi_ctl_status_t;
1506
1507 /**
1508 * cvmx_npi_dbg_select
1509 *
1510 * NPI_DBG_SELECT = Debug Select Register
1511 *
1512 * Contains the debug select value in last written to the RSLs.
1513 */
1514 union cvmx_npi_dbg_select {
1515 uint64_t u64;
1516 struct cvmx_npi_dbg_select_s {
1517 #ifdef __BIG_ENDIAN_BITFIELD
1518 uint64_t reserved_16_63 : 48;
1519 uint64_t dbg_sel : 16; /**< When this register is written its value is sent to
1520 all RSLs. */
1521 #else
1522 uint64_t dbg_sel : 16;
1523 uint64_t reserved_16_63 : 48;
1524 #endif
1525 } s;
1526 struct cvmx_npi_dbg_select_s cn30xx;
1527 struct cvmx_npi_dbg_select_s cn31xx;
1528 struct cvmx_npi_dbg_select_s cn38xx;
1529 struct cvmx_npi_dbg_select_s cn38xxp2;
1530 struct cvmx_npi_dbg_select_s cn50xx;
1531 struct cvmx_npi_dbg_select_s cn58xx;
1532 struct cvmx_npi_dbg_select_s cn58xxp1;
1533 };
1534 typedef union cvmx_npi_dbg_select cvmx_npi_dbg_select_t;
1535
1536 /**
1537 * cvmx_npi_dma_control
1538 *
1539 * NPI_DMA_CONTROL = DMA Control Register
1540 *
1541 * Controls operation of the DMA IN/OUT of the NPI.
1542 */
1543 union cvmx_npi_dma_control {
1544 uint64_t u64;
1545 struct cvmx_npi_dma_control_s {
1546 #ifdef __BIG_ENDIAN_BITFIELD
1547 uint64_t reserved_36_63 : 28;
1548 uint64_t b0_lend : 1; /**< When set '1' and the NPI is in the mode to write
1549 0 to L2C memory when a DMA is done, the address
1550 to be written to will be treated as a Little
1551 Endian address. This field is new to PASS-2. */
1552 uint64_t dwb_denb : 1; /**< When set '1' the NPI will send a value in the DWB
1553 field for a free page operation for the memory
1554 that contained the data in N3. */
1555 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
1556 this value is used for the DWB field of the
1557 operation. */
1558 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
1559 be returned to when used. */
1560 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
1561 if '0' then the number of bytes in the dma transfer
1562 will be added to the count register. */
1563 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
1564 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
1565 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
1566 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
1567 '1' use pointer values for address and register
1568 values for RO, ES, and NS, '0' use register
1569 values for address and pointer values for
1570 RO, ES, and NS. */
1571 uint64_t hp_enb : 1; /**< Enables the High Priority DMA.
1572 While this bit is disabled '0' then the value
1573 in the NPI_HIGHP_IBUFF_SADDR is re-loaded to the
1574 starting address of the High Priority DMA engine.
1575 CSIZE field will be reloaded, for the High Priority
1576 DMA Engine. */
1577 uint64_t lp_enb : 1; /**< Enables the Low Priority DMA.
1578 While this bit is disabled '0' then the value
1579 in the NPI_LOWP_IBUFF_SADDR is re-loaded to the
1580 starting address of the Low Priority DMA engine.
1581 PASS-2: When this bit is '0' the value in the
1582 CSIZE field will be reloaded, for the Low Priority
1583 DMA Engine. */
1584 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
1585 This value should only be written once. After
1586 writing this value a new value will not be
1587 recognized until the end of the DMA I-Chunk is
1588 reached. */
1589 #else
1590 uint64_t csize : 14;
1591 uint64_t lp_enb : 1;
1592 uint64_t hp_enb : 1;
1593 uint64_t o_mode : 1;
1594 uint64_t o_es : 2;
1595 uint64_t o_ns : 1;
1596 uint64_t o_ro : 1;
1597 uint64_t o_add1 : 1;
1598 uint64_t fpa_que : 3;
1599 uint64_t dwb_ichk : 9;
1600 uint64_t dwb_denb : 1;
1601 uint64_t b0_lend : 1;
1602 uint64_t reserved_36_63 : 28;
1603 #endif
1604 } s;
1605 struct cvmx_npi_dma_control_s cn30xx;
1606 struct cvmx_npi_dma_control_s cn31xx;
1607 struct cvmx_npi_dma_control_s cn38xx;
1608 struct cvmx_npi_dma_control_s cn38xxp2;
1609 struct cvmx_npi_dma_control_s cn50xx;
1610 struct cvmx_npi_dma_control_s cn58xx;
1611 struct cvmx_npi_dma_control_s cn58xxp1;
1612 };
1613 typedef union cvmx_npi_dma_control cvmx_npi_dma_control_t;
1614
1615 /**
1616 * cvmx_npi_dma_highp_counts
1617 *
1618 * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts
1619 *
1620 * Values for determing the number of instructions for High Priority DMA in the NPI.
1621 */
1622 union cvmx_npi_dma_highp_counts {
1623 uint64_t u64;
1624 struct cvmx_npi_dma_highp_counts_s {
1625 #ifdef __BIG_ENDIAN_BITFIELD
1626 uint64_t reserved_39_63 : 25;
1627 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */
1628 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */
1629 #else
1630 uint64_t dbell : 32;
1631 uint64_t fcnt : 7;
1632 uint64_t reserved_39_63 : 25;
1633 #endif
1634 } s;
1635 struct cvmx_npi_dma_highp_counts_s cn30xx;
1636 struct cvmx_npi_dma_highp_counts_s cn31xx;
1637 struct cvmx_npi_dma_highp_counts_s cn38xx;
1638 struct cvmx_npi_dma_highp_counts_s cn38xxp2;
1639 struct cvmx_npi_dma_highp_counts_s cn50xx;
1640 struct cvmx_npi_dma_highp_counts_s cn58xx;
1641 struct cvmx_npi_dma_highp_counts_s cn58xxp1;
1642 };
1643 typedef union cvmx_npi_dma_highp_counts cvmx_npi_dma_highp_counts_t;
1644
1645 /**
1646 * cvmx_npi_dma_highp_naddr
1647 *
1648 * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address
1649 *
1650 * Place NPI will read the next Ichunk data from. This is valid when state is 0
1651 */
1652 union cvmx_npi_dma_highp_naddr {
1653 uint64_t u64;
1654 struct cvmx_npi_dma_highp_naddr_s {
1655 #ifdef __BIG_ENDIAN_BITFIELD
1656 uint64_t reserved_40_63 : 24;
1657 uint64_t state : 4; /**< The DMA instruction engine state vector.
1658 Typical value is 0 (IDLE). */
1659 uint64_t addr : 36; /**< The next L2C address to read DMA instructions
1660 from for the High Priority DMA engine. */
1661 #else
1662 uint64_t addr : 36;
1663 uint64_t state : 4;
1664 uint64_t reserved_40_63 : 24;
1665 #endif
1666 } s;
1667 struct cvmx_npi_dma_highp_naddr_s cn30xx;
1668 struct cvmx_npi_dma_highp_naddr_s cn31xx;
1669 struct cvmx_npi_dma_highp_naddr_s cn38xx;
1670 struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
1671 struct cvmx_npi_dma_highp_naddr_s cn50xx;
1672 struct cvmx_npi_dma_highp_naddr_s cn58xx;
1673 struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
1674 };
1675 typedef union cvmx_npi_dma_highp_naddr cvmx_npi_dma_highp_naddr_t;
1676
1677 /**
1678 * cvmx_npi_dma_lowp_counts
1679 *
1680 * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts
1681 *
1682 * Values for determing the number of instructions for Low Priority DMA in the NPI.
1683 */
1684 union cvmx_npi_dma_lowp_counts {
1685 uint64_t u64;
1686 struct cvmx_npi_dma_lowp_counts_s {
1687 #ifdef __BIG_ENDIAN_BITFIELD
1688 uint64_t reserved_39_63 : 25;
1689 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */
1690 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */
1691 #else
1692 uint64_t dbell : 32;
1693 uint64_t fcnt : 7;
1694 uint64_t reserved_39_63 : 25;
1695 #endif
1696 } s;
1697 struct cvmx_npi_dma_lowp_counts_s cn30xx;
1698 struct cvmx_npi_dma_lowp_counts_s cn31xx;
1699 struct cvmx_npi_dma_lowp_counts_s cn38xx;
1700 struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
1701 struct cvmx_npi_dma_lowp_counts_s cn50xx;
1702 struct cvmx_npi_dma_lowp_counts_s cn58xx;
1703 struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
1704 };
1705 typedef union cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_counts_t;
1706
1707 /**
1708 * cvmx_npi_dma_lowp_naddr
1709 *
1710 * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address
1711 *
1712 * Place NPI will read the next Ichunk data from. This is valid when state is 0
1713 */
1714 union cvmx_npi_dma_lowp_naddr {
1715 uint64_t u64;
1716 struct cvmx_npi_dma_lowp_naddr_s {
1717 #ifdef __BIG_ENDIAN_BITFIELD
1718 uint64_t reserved_40_63 : 24;
1719 uint64_t state : 4; /**< The DMA instruction engine state vector.
1720 Typical value is 0 (IDLE). */
1721 uint64_t addr : 36; /**< The next L2C address to read DMA instructions
1722 from for the Low Priority DMA engine. */
1723 #else
1724 uint64_t addr : 36;
1725 uint64_t state : 4;
1726 uint64_t reserved_40_63 : 24;
1727 #endif
1728 } s;
1729 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
1730 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
1731 struct cvmx_npi_dma_lowp_naddr_s cn38xx;
1732 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
1733 struct cvmx_npi_dma_lowp_naddr_s cn50xx;
1734 struct cvmx_npi_dma_lowp_naddr_s cn58xx;
1735 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
1736 };
1737 typedef union cvmx_npi_dma_lowp_naddr cvmx_npi_dma_lowp_naddr_t;
1738
1739 /**
1740 * cvmx_npi_highp_dbell
1741 *
1742 * NPI_HIGHP_DBELL = High Priority Door Bell
1743 *
1744 * The door bell register for the high priority DMA queue.
1745 */
1746 union cvmx_npi_highp_dbell {
1747 uint64_t u64;
1748 struct cvmx_npi_highp_dbell_s {
1749 #ifdef __BIG_ENDIAN_BITFIELD
1750 uint64_t reserved_16_63 : 48;
1751 uint64_t dbell : 16; /**< The value written to this register is added to the
1752 number of 8byte words to be read and processes for
1753 the high priority dma queue. */
1754 #else
1755 uint64_t dbell : 16;
1756 uint64_t reserved_16_63 : 48;
1757 #endif
1758 } s;
1759 struct cvmx_npi_highp_dbell_s cn30xx;
1760 struct cvmx_npi_highp_dbell_s cn31xx;
1761 struct cvmx_npi_highp_dbell_s cn38xx;
1762 struct cvmx_npi_highp_dbell_s cn38xxp2;
1763 struct cvmx_npi_highp_dbell_s cn50xx;
1764 struct cvmx_npi_highp_dbell_s cn58xx;
1765 struct cvmx_npi_highp_dbell_s cn58xxp1;
1766 };
1767 typedef union cvmx_npi_highp_dbell cvmx_npi_highp_dbell_t;
1768
1769 /**
1770 * cvmx_npi_highp_ibuff_saddr
1771 *
1772 * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address
1773 *
1774 * The address to start reading Instructions from for HIGHP.
1775 */
1776 union cvmx_npi_highp_ibuff_saddr {
1777 uint64_t u64;
1778 struct cvmx_npi_highp_ibuff_saddr_s {
1779 #ifdef __BIG_ENDIAN_BITFIELD
1780 uint64_t reserved_36_63 : 28;
1781 uint64_t saddr : 36; /**< The starting address to read the first instruction. */
1782 #else
1783 uint64_t saddr : 36;
1784 uint64_t reserved_36_63 : 28;
1785 #endif
1786 } s;
1787 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
1788 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
1789 struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
1790 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
1791 struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
1792 struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
1793 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
1794 };
1795 typedef union cvmx_npi_highp_ibuff_saddr cvmx_npi_highp_ibuff_saddr_t;
1796
1797 /**
1798 * cvmx_npi_input_control
1799 *
1800 * NPI_INPUT_CONTROL = NPI's Input Control Register
1801 *
1802 * Control for reads for gather list and instructions.
1803 */
1804 union cvmx_npi_input_control {
1805 uint64_t u64;
1806 struct cvmx_npi_input_control_s {
1807 #ifdef __BIG_ENDIAN_BITFIELD
1808 uint64_t reserved_23_63 : 41;
1809 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be
1810 made with a Round Robin arbitration. When '0'
1811 the input packet port is fixed in priority,
1812 where the lower port number has higher priority.
1813 PASS3 Field */
1814 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in
1815 calculating a DPTR. */
1816 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of
1817 gather data. */
1818 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of
1819 gather data. */
1820 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1821 gather data. */
1822 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
1823 ROR, ESR, and NSR. When clear '0' the value in
1824 DPTR will be used. In turn the bits not used for
1825 ROR, ESR, and NSR, will be used for bits [63:60]
1826 of the address used to fetch packet data. */
1827 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of
1828 gather list and gather instruction. */
1829 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of
1830 gather list and gather instruction. */
1831 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1832 gather list and gather instruction. */
1833 #else
1834 uint64_t ror : 1;
1835 uint64_t esr : 2;
1836 uint64_t nsr : 1;
1837 uint64_t use_csr : 1;
1838 uint64_t d_ror : 1;
1839 uint64_t d_esr : 2;
1840 uint64_t d_nsr : 1;
1841 uint64_t pbp_dhi : 13;
1842 uint64_t pkt_rr : 1;
1843 uint64_t reserved_23_63 : 41;
1844 #endif
1845 } s;
1846 struct cvmx_npi_input_control_cn30xx {
1847 #ifdef __BIG_ENDIAN_BITFIELD
1848 uint64_t reserved_22_63 : 42;
1849 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in
1850 calculating a DPTR. */
1851 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of
1852 gather data. */
1853 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of
1854 gather data. */
1855 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1856 gather data. */
1857 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
1858 ROR, ESR, and NSR. When clear '0' the value in
1859 DPTR will be used. In turn the bits not used for
1860 ROR, ESR, and NSR, will be used for bits [63:60]
1861 of the address used to fetch packet data. */
1862 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of
1863 gather list and gather instruction. */
1864 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of
1865 gather list and gather instruction. */
1866 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of
1867 gather list and gather instruction. */
1868 #else
1869 uint64_t ror : 1;
1870 uint64_t esr : 2;
1871 uint64_t nsr : 1;
1872 uint64_t use_csr : 1;
1873 uint64_t d_ror : 1;
1874 uint64_t d_esr : 2;
1875 uint64_t d_nsr : 1;
1876 uint64_t pbp_dhi : 13;
1877 uint64_t reserved_22_63 : 42;
1878 #endif
1879 } cn30xx;
1880 struct cvmx_npi_input_control_cn30xx cn31xx;
1881 struct cvmx_npi_input_control_s cn38xx;
1882 struct cvmx_npi_input_control_cn30xx cn38xxp2;
1883 struct cvmx_npi_input_control_s cn50xx;
1884 struct cvmx_npi_input_control_s cn58xx;
1885 struct cvmx_npi_input_control_s cn58xxp1;
1886 };
1887 typedef union cvmx_npi_input_control cvmx_npi_input_control_t;
1888
1889 /**
1890 * cvmx_npi_int_enb
1891 *
1892 * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register
1893 *
1894 * Used to enable the various interrupting conditions of NPI
1895 */
1896 union cvmx_npi_int_enb {
1897 uint64_t u64;
1898 struct cvmx_npi_int_enb_s {
1899 #ifdef __BIG_ENDIAN_BITFIELD
1900 uint64_t reserved_62_63 : 2;
1901 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
1902 interrupt. */
1903 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
1904 interrupt. */
1905 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
1906 interrupt. */
1907 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
1908 interrupt. */
1909 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
1910 interrupt. */
1911 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
1912 interrupt. */
1913 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
1914 interrupt. */
1915 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
1916 interrupt. */
1917 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
1918 interrupt. */
1919 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
1920 interrupt. */
1921 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an
1922 interrupt. */
1923 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an
1924 interrupt. */
1925 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
1926 interrupt. */
1927 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
1928 interrupt. */
1929 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
1930 interrupt. */
1931 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
1932 interrupt. */
1933 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
1934 interrupt. */
1935 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
1936 interrupt. */
1937 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
1938 interrupt. */
1939 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
1940 interrupt. */
1941 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
1942 interrupt. */
1943 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
1944 interrupt. */
1945 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
1946 interrupt. */
1947 uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
1948 interrupt. */
1949 uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
1950 interrupt. */
1951 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
1952 interrupt. */
1953 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
1954 interrupt. */
1955 uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
1956 interrupt. */
1957 uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
1958 interrupt. */
1959 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
1960 interrupt. */
1961 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
1962 interrupt. */
1963 uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
1964 interrupt. */
1965 uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
1966 interrupt. */
1967 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
1968 interrupt. */
1969 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
1970 interrupt. */
1971 uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
1972 interrupt. */
1973 uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
1974 interrupt. */
1975 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
1976 interrupt. */
1977 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
1978 interrupt. */
1979 uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an
1980 interrupt. */
1981 uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an
1982 interrupt. */
1983 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an
1984 interrupt. */
1985 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
1986 interrupt. */
1987 uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
1988 interrupt. */
1989 uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
1990 interrupt. */
1991 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
1992 interrupt. */
1993 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
1994 interrupt. */
1995 uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
1996 interrupt. */
1997 uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
1998 interrupt. */
1999 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
2000 interrupt. */
2001 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2002 interrupt. */
2003 uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
2004 interrupt. */
2005 uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
2006 interrupt. */
2007 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
2008 interrupt. */
2009 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2010 interrupt. */
2011 uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
2012 interrupt. */
2013 uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
2014 interrupt. */
2015 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
2016 interrupt. */
2017 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2018 interrupt. */
2019 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2020 interrupt. */
2021 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2022 interrupt. */
2023 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2024 interrupt. */
2025 #else
2026 uint64_t rml_rto : 1;
2027 uint64_t rml_wto : 1;
2028 uint64_t pci_rsl : 1;
2029 uint64_t po0_2sml : 1;
2030 uint64_t po1_2sml : 1;
2031 uint64_t po2_2sml : 1;
2032 uint64_t po3_2sml : 1;
2033 uint64_t i0_rtout : 1;
2034 uint64_t i1_rtout : 1;
2035 uint64_t i2_rtout : 1;
2036 uint64_t i3_rtout : 1;
2037 uint64_t i0_overf : 1;
2038 uint64_t i1_overf : 1;
2039 uint64_t i2_overf : 1;
2040 uint64_t i3_overf : 1;
2041 uint64_t p0_rtout : 1;
2042 uint64_t p1_rtout : 1;
2043 uint64_t p2_rtout : 1;
2044 uint64_t p3_rtout : 1;
2045 uint64_t p0_perr : 1;
2046 uint64_t p1_perr : 1;
2047 uint64_t p2_perr : 1;
2048 uint64_t p3_perr : 1;
2049 uint64_t g0_rtout : 1;
2050 uint64_t g1_rtout : 1;
2051 uint64_t g2_rtout : 1;
2052 uint64_t g3_rtout : 1;
2053 uint64_t p0_pperr : 1;
2054 uint64_t p1_pperr : 1;
2055 uint64_t p2_pperr : 1;
2056 uint64_t p3_pperr : 1;
2057 uint64_t p0_ptout : 1;
2058 uint64_t p1_ptout : 1;
2059 uint64_t p2_ptout : 1;
2060 uint64_t p3_ptout : 1;
2061 uint64_t i0_pperr : 1;
2062 uint64_t i1_pperr : 1;
2063 uint64_t i2_pperr : 1;
2064 uint64_t i3_pperr : 1;
2065 uint64_t win_rto : 1;
2066 uint64_t p_dperr : 1;
2067 uint64_t iobdma : 1;
2068 uint64_t fcr_s_e : 1;
2069 uint64_t fcr_a_f : 1;
2070 uint64_t pcr_s_e : 1;
2071 uint64_t pcr_a_f : 1;
2072 uint64_t q2_s_e : 1;
2073 uint64_t q2_a_f : 1;
2074 uint64_t q3_s_e : 1;
2075 uint64_t q3_a_f : 1;
2076 uint64_t com_s_e : 1;
2077 uint64_t com_a_f : 1;
2078 uint64_t pnc_s_e : 1;
2079 uint64_t pnc_a_f : 1;
2080 uint64_t rwx_s_e : 1;
2081 uint64_t rdx_s_e : 1;
2082 uint64_t pcf_p_e : 1;
2083 uint64_t pcf_p_f : 1;
2084 uint64_t pdf_p_e : 1;
2085 uint64_t pdf_p_f : 1;
2086 uint64_t q1_s_e : 1;
2087 uint64_t q1_a_f : 1;
2088 uint64_t reserved_62_63 : 2;
2089 #endif
2090 } s;
2091 struct cvmx_npi_int_enb_cn30xx {
2092 #ifdef __BIG_ENDIAN_BITFIELD
2093 uint64_t reserved_62_63 : 2;
2094 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
2095 interrupt. */
2096 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
2097 interrupt. */
2098 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
2099 interrupt. */
2100 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
2101 interrupt. */
2102 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
2103 interrupt. */
2104 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
2105 interrupt. */
2106 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
2107 interrupt. */
2108 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
2109 interrupt. */
2110 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
2111 interrupt. */
2112 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
2113 interrupt. */
2114 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an
2115 interrupt. */
2116 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an
2117 interrupt. */
2118 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
2119 interrupt. */
2120 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
2121 interrupt. */
2122 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
2123 interrupt. */
2124 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
2125 interrupt. */
2126 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
2127 interrupt. */
2128 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
2129 interrupt. */
2130 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
2131 interrupt. */
2132 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
2133 interrupt. */
2134 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
2135 interrupt. */
2136 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
2137 interrupt. */
2138 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
2139 interrupt. */
2140 uint64_t reserved_36_38 : 3;
2141 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
2142 interrupt. */
2143 uint64_t reserved_32_34 : 3;
2144 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
2145 interrupt. */
2146 uint64_t reserved_28_30 : 3;
2147 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
2148 interrupt. */
2149 uint64_t reserved_24_26 : 3;
2150 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
2151 interrupt. */
2152 uint64_t reserved_20_22 : 3;
2153 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
2154 interrupt. */
2155 uint64_t reserved_16_18 : 3;
2156 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
2157 interrupt. */
2158 uint64_t reserved_12_14 : 3;
2159 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2160 interrupt. */
2161 uint64_t reserved_8_10 : 3;
2162 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2163 interrupt. */
2164 uint64_t reserved_4_6 : 3;
2165 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2166 interrupt. */
2167 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2168 interrupt. */
2169 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2170 interrupt. */
2171 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2172 interrupt. */
2173 #else
2174 uint64_t rml_rto : 1;
2175 uint64_t rml_wto : 1;
2176 uint64_t pci_rsl : 1;
2177 uint64_t po0_2sml : 1;
2178 uint64_t reserved_4_6 : 3;
2179 uint64_t i0_rtout : 1;
2180 uint64_t reserved_8_10 : 3;
2181 uint64_t i0_overf : 1;
2182 uint64_t reserved_12_14 : 3;
2183 uint64_t p0_rtout : 1;
2184 uint64_t reserved_16_18 : 3;
2185 uint64_t p0_perr : 1;
2186 uint64_t reserved_20_22 : 3;
2187 uint64_t g0_rtout : 1;
2188 uint64_t reserved_24_26 : 3;
2189 uint64_t p0_pperr : 1;
2190 uint64_t reserved_28_30 : 3;
2191 uint64_t p0_ptout : 1;
2192 uint64_t reserved_32_34 : 3;
2193 uint64_t i0_pperr : 1;
2194 uint64_t reserved_36_38 : 3;
2195 uint64_t win_rto : 1;
2196 uint64_t p_dperr : 1;
2197 uint64_t iobdma : 1;
2198 uint64_t fcr_s_e : 1;
2199 uint64_t fcr_a_f : 1;
2200 uint64_t pcr_s_e : 1;
2201 uint64_t pcr_a_f : 1;
2202 uint64_t q2_s_e : 1;
2203 uint64_t q2_a_f : 1;
2204 uint64_t q3_s_e : 1;
2205 uint64_t q3_a_f : 1;
2206 uint64_t com_s_e : 1;
2207 uint64_t com_a_f : 1;
2208 uint64_t pnc_s_e : 1;
2209 uint64_t pnc_a_f : 1;
2210 uint64_t rwx_s_e : 1;
2211 uint64_t rdx_s_e : 1;
2212 uint64_t pcf_p_e : 1;
2213 uint64_t pcf_p_f : 1;
2214 uint64_t pdf_p_e : 1;
2215 uint64_t pdf_p_f : 1;
2216 uint64_t q1_s_e : 1;
2217 uint64_t q1_a_f : 1;
2218 uint64_t reserved_62_63 : 2;
2219 #endif
2220 } cn30xx;
2221 struct cvmx_npi_int_enb_cn31xx {
2222 #ifdef __BIG_ENDIAN_BITFIELD
2223 uint64_t reserved_62_63 : 2;
2224 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
2225 interrupt. */
2226 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
2227 interrupt. */
2228 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
2229 interrupt. */
2230 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
2231 interrupt. */
2232 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
2233 interrupt. */
2234 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
2235 interrupt. */
2236 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
2237 interrupt. */
2238 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
2239 interrupt. */
2240 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
2241 interrupt. */
2242 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
2243 interrupt. */
2244 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an
2245 interrupt. */
2246 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an
2247 interrupt. */
2248 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
2249 interrupt. */
2250 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
2251 interrupt. */
2252 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
2253 interrupt. */
2254 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
2255 interrupt. */
2256 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
2257 interrupt. */
2258 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
2259 interrupt. */
2260 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
2261 interrupt. */
2262 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
2263 interrupt. */
2264 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
2265 interrupt. */
2266 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
2267 interrupt. */
2268 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
2269 interrupt. */
2270 uint64_t reserved_37_38 : 2;
2271 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
2272 interrupt. */
2273 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
2274 interrupt. */
2275 uint64_t reserved_33_34 : 2;
2276 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
2277 interrupt. */
2278 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
2279 interrupt. */
2280 uint64_t reserved_29_30 : 2;
2281 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
2282 interrupt. */
2283 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
2284 interrupt. */
2285 uint64_t reserved_25_26 : 2;
2286 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
2287 interrupt. */
2288 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
2289 interrupt. */
2290 uint64_t reserved_21_22 : 2;
2291 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an
2292 interrupt. */
2293 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
2294 interrupt. */
2295 uint64_t reserved_17_18 : 2;
2296 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
2297 interrupt. */
2298 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
2299 interrupt. */
2300 uint64_t reserved_13_14 : 2;
2301 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
2302 interrupt. */
2303 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2304 interrupt. */
2305 uint64_t reserved_9_10 : 2;
2306 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
2307 interrupt. */
2308 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2309 interrupt. */
2310 uint64_t reserved_5_6 : 2;
2311 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
2312 interrupt. */
2313 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2314 interrupt. */
2315 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2316 interrupt. */
2317 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2318 interrupt. */
2319 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2320 interrupt. */
2321 #else
2322 uint64_t rml_rto : 1;
2323 uint64_t rml_wto : 1;
2324 uint64_t pci_rsl : 1;
2325 uint64_t po0_2sml : 1;
2326 uint64_t po1_2sml : 1;
2327 uint64_t reserved_5_6 : 2;
2328 uint64_t i0_rtout : 1;
2329 uint64_t i1_rtout : 1;
2330 uint64_t reserved_9_10 : 2;
2331 uint64_t i0_overf : 1;
2332 uint64_t i1_overf : 1;
2333 uint64_t reserved_13_14 : 2;
2334 uint64_t p0_rtout : 1;
2335 uint64_t p1_rtout : 1;
2336 uint64_t reserved_17_18 : 2;
2337 uint64_t p0_perr : 1;
2338 uint64_t p1_perr : 1;
2339 uint64_t reserved_21_22 : 2;
2340 uint64_t g0_rtout : 1;
2341 uint64_t g1_rtout : 1;
2342 uint64_t reserved_25_26 : 2;
2343 uint64_t p0_pperr : 1;
2344 uint64_t p1_pperr : 1;
2345 uint64_t reserved_29_30 : 2;
2346 uint64_t p0_ptout : 1;
2347 uint64_t p1_ptout : 1;
2348 uint64_t reserved_33_34 : 2;
2349 uint64_t i0_pperr : 1;
2350 uint64_t i1_pperr : 1;
2351 uint64_t reserved_37_38 : 2;
2352 uint64_t win_rto : 1;
2353 uint64_t p_dperr : 1;
2354 uint64_t iobdma : 1;
2355 uint64_t fcr_s_e : 1;
2356 uint64_t fcr_a_f : 1;
2357 uint64_t pcr_s_e : 1;
2358 uint64_t pcr_a_f : 1;
2359 uint64_t q2_s_e : 1;
2360 uint64_t q2_a_f : 1;
2361 uint64_t q3_s_e : 1;
2362 uint64_t q3_a_f : 1;
2363 uint64_t com_s_e : 1;
2364 uint64_t com_a_f : 1;
2365 uint64_t pnc_s_e : 1;
2366 uint64_t pnc_a_f : 1;
2367 uint64_t rwx_s_e : 1;
2368 uint64_t rdx_s_e : 1;
2369 uint64_t pcf_p_e : 1;
2370 uint64_t pcf_p_f : 1;
2371 uint64_t pdf_p_e : 1;
2372 uint64_t pdf_p_f : 1;
2373 uint64_t q1_s_e : 1;
2374 uint64_t q1_a_f : 1;
2375 uint64_t reserved_62_63 : 2;
2376 #endif
2377 } cn31xx;
2378 struct cvmx_npi_int_enb_s cn38xx;
2379 struct cvmx_npi_int_enb_cn38xxp2 {
2380 #ifdef __BIG_ENDIAN_BITFIELD
2381 uint64_t reserved_42_63 : 22;
2382 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an
2383 interrupt. */
2384 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an
2385 interrupt. */
2386 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
2387 interrupt. */
2388 uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
2389 interrupt. */
2390 uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
2391 interrupt. */
2392 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
2393 interrupt. */
2394 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
2395 interrupt. */
2396 uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
2397 interrupt. */
2398 uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
2399 interrupt. */
2400 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
2401 interrupt. */
2402 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
2403 interrupt. */
2404 uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
2405 interrupt. */
2406 uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
2407 interrupt. */
2408 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
2409 interrupt. */
2410 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
2411 interrupt. */
2412 uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
2413 interrupt. */
2414 uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
2415 interrupt. */
2416 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
2417 interrupt. */
2418 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
2419 interrupt. */
2420 uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an
2421 interrupt. */
2422 uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an
2423 interrupt. */
2424 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an
2425 interrupt. */
2426 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an
2427 interrupt. */
2428 uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
2429 interrupt. */
2430 uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
2431 interrupt. */
2432 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
2433 interrupt. */
2434 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
2435 interrupt. */
2436 uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
2437 interrupt. */
2438 uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
2439 interrupt. */
2440 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
2441 interrupt. */
2442 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
2443 interrupt. */
2444 uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
2445 interrupt. */
2446 uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
2447 interrupt. */
2448 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
2449 interrupt. */
2450 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
2451 interrupt. */
2452 uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
2453 interrupt. */
2454 uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
2455 interrupt. */
2456 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
2457 interrupt. */
2458 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
2459 interrupt. */
2460 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
2461 interrupt. */
2462 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an
2463 interrupt. */
2464 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an
2465 interrupt. */
2466 #else
2467 uint64_t rml_rto : 1;
2468 uint64_t rml_wto : 1;
2469 uint64_t pci_rsl : 1;
2470 uint64_t po0_2sml : 1;
2471 uint64_t po1_2sml : 1;
2472 uint64_t po2_2sml : 1;
2473 uint64_t po3_2sml : 1;
2474 uint64_t i0_rtout : 1;
2475 uint64_t i1_rtout : 1;
2476 uint64_t i2_rtout : 1;
2477 uint64_t i3_rtout : 1;
2478 uint64_t i0_overf : 1;
2479 uint64_t i1_overf : 1;
2480 uint64_t i2_overf : 1;
2481 uint64_t i3_overf : 1;
2482 uint64_t p0_rtout : 1;
2483 uint64_t p1_rtout : 1;
2484 uint64_t p2_rtout : 1;
2485 uint64_t p3_rtout : 1;
2486 uint64_t p0_perr : 1;
2487 uint64_t p1_perr : 1;
2488 uint64_t p2_perr : 1;
2489 uint64_t p3_perr : 1;
2490 uint64_t g0_rtout : 1;
2491 uint64_t g1_rtout : 1;
2492 uint64_t g2_rtout : 1;
2493 uint64_t g3_rtout : 1;
2494 uint64_t p0_pperr : 1;
2495 uint64_t p1_pperr : 1;
2496 uint64_t p2_pperr : 1;
2497 uint64_t p3_pperr : 1;
2498 uint64_t p0_ptout : 1;
2499 uint64_t p1_ptout : 1;
2500 uint64_t p2_ptout : 1;
2501 uint64_t p3_ptout : 1;
2502 uint64_t i0_pperr : 1;
2503 uint64_t i1_pperr : 1;
2504 uint64_t i2_pperr : 1;
2505 uint64_t i3_pperr : 1;
2506 uint64_t win_rto : 1;
2507 uint64_t p_dperr : 1;
2508 uint64_t iobdma : 1;
2509 uint64_t reserved_42_63 : 22;
2510 #endif
2511 } cn38xxp2;
2512 struct cvmx_npi_int_enb_cn31xx cn50xx;
2513 struct cvmx_npi_int_enb_s cn58xx;
2514 struct cvmx_npi_int_enb_s cn58xxp1;
2515 };
2516 typedef union cvmx_npi_int_enb cvmx_npi_int_enb_t;
2517
2518 /**
2519 * cvmx_npi_int_sum
2520 *
2521 * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register
2522 *
2523 * Set when an interrupt condition occurs, write '1' to clear.
2524 */
2525 union cvmx_npi_int_sum {
2526 uint64_t u64;
2527 struct cvmx_npi_int_sum_s {
2528 #ifdef __BIG_ENDIAN_BITFIELD
2529 uint64_t reserved_62_63 : 2;
2530 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full.
2531 PASS3 Field. */
2532 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty.
2533 PASS3 Field. */
2534 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO.
2535 PASS3 Field. */
2536 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO.
2537 PASS3 Field. */
2538 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO.
2539 PASS3 Field. */
2540 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO.
2541 PASS3 Field. */
2542 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0.
2543 PASS3 Field. */
2544 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0.
2545 PASS3 Field. */
2546 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max.
2547 PASS3 Field. */
2548 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0.
2549 PASS3 Field. */
2550 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max.
2551 PASS3 Field. */
2552 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0.
2553 PASS3 Field. */
2554 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full.
2555 PASS3 Field. */
2556 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty.
2557 PASS3 Field. */
2558 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full.
2559 PASS3 Field. */
2560 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty.
2561 PASS3 Field. */
2562 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full.
2563 PASS3 Field. */
2564 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty.
2565 PASS3 Field. */
2566 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full.
2567 PASS3 Field. */
2568 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty.
2569 PASS3 Field. */
2570 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2571 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2572 from the PCI this bit may be set. */
2573 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2574 uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction
2575 this bit may be set. */
2576 uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction
2577 this bit may be set. */
2578 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction
2579 this bit may be set. */
2580 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2581 this bit may be set. */
2582 uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO
2583 pair. */
2584 uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO
2585 pair. */
2586 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO
2587 pair. */
2588 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2589 pair. */
2590 uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2591 pointer-pair, this bit may be set. */
2592 uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2593 pointer-pair, this bit may be set. */
2594 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2595 pointer-pair, this bit may be set. */
2596 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2597 pointer-pair, this bit may be set. */
2598 uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to
2599 read a gather list. */
2600 uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to
2601 read a gather list. */
2602 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2603 read a gather list. */
2604 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2605 read a gather list. */
2606 uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet
2607 data this bit may be set. */
2608 uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet
2609 data this bit may be set. */
2610 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet
2611 data this bit may be set. */
2612 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
2613 data this bit may be set. */
2614 uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to
2615 read packet data. */
2616 uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to
2617 read packet data. */
2618 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2619 read packet data. */
2620 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2621 read packet data. */
2622 uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the
2623 doorbell count was set. */
2624 uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the
2625 doorbell count was set. */
2626 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the
2627 doorbell count was set. */
2628 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
2629 doorbell count was set. */
2630 uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to
2631 read instructions. */
2632 uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to
2633 read instructions. */
2634 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2635 read instructions. */
2636 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2637 read instructions. */
2638 uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller
2639 than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
2640 uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller
2641 than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
2642 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller
2643 than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
2644 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
2645 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
2646 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
2647 corresponding bit in the PCI_INT_ENB2 is SET. */
2648 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
2649 back from a RSL after sending a write command to
2650 a RSL. */
2651 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
2652 back from a RSL after sending a read command to
2653 a RSL. */
2654 #else
2655 uint64_t rml_rto : 1;
2656 uint64_t rml_wto : 1;
2657 uint64_t pci_rsl : 1;
2658 uint64_t po0_2sml : 1;
2659 uint64_t po1_2sml : 1;
2660 uint64_t po2_2sml : 1;
2661 uint64_t po3_2sml : 1;
2662 uint64_t i0_rtout : 1;
2663 uint64_t i1_rtout : 1;
2664 uint64_t i2_rtout : 1;
2665 uint64_t i3_rtout : 1;
2666 uint64_t i0_overf : 1;
2667 uint64_t i1_overf : 1;
2668 uint64_t i2_overf : 1;
2669 uint64_t i3_overf : 1;
2670 uint64_t p0_rtout : 1;
2671 uint64_t p1_rtout : 1;
2672 uint64_t p2_rtout : 1;
2673 uint64_t p3_rtout : 1;
2674 uint64_t p0_perr : 1;
2675 uint64_t p1_perr : 1;
2676 uint64_t p2_perr : 1;
2677 uint64_t p3_perr : 1;
2678 uint64_t g0_rtout : 1;
2679 uint64_t g1_rtout : 1;
2680 uint64_t g2_rtout : 1;
2681 uint64_t g3_rtout : 1;
2682 uint64_t p0_pperr : 1;
2683 uint64_t p1_pperr : 1;
2684 uint64_t p2_pperr : 1;
2685 uint64_t p3_pperr : 1;
2686 uint64_t p0_ptout : 1;
2687 uint64_t p1_ptout : 1;
2688 uint64_t p2_ptout : 1;
2689 uint64_t p3_ptout : 1;
2690 uint64_t i0_pperr : 1;
2691 uint64_t i1_pperr : 1;
2692 uint64_t i2_pperr : 1;
2693 uint64_t i3_pperr : 1;
2694 uint64_t win_rto : 1;
2695 uint64_t p_dperr : 1;
2696 uint64_t iobdma : 1;
2697 uint64_t fcr_s_e : 1;
2698 uint64_t fcr_a_f : 1;
2699 uint64_t pcr_s_e : 1;
2700 uint64_t pcr_a_f : 1;
2701 uint64_t q2_s_e : 1;
2702 uint64_t q2_a_f : 1;
2703 uint64_t q3_s_e : 1;
2704 uint64_t q3_a_f : 1;
2705 uint64_t com_s_e : 1;
2706 uint64_t com_a_f : 1;
2707 uint64_t pnc_s_e : 1;
2708 uint64_t pnc_a_f : 1;
2709 uint64_t rwx_s_e : 1;
2710 uint64_t rdx_s_e : 1;
2711 uint64_t pcf_p_e : 1;
2712 uint64_t pcf_p_f : 1;
2713 uint64_t pdf_p_e : 1;
2714 uint64_t pdf_p_f : 1;
2715 uint64_t q1_s_e : 1;
2716 uint64_t q1_a_f : 1;
2717 uint64_t reserved_62_63 : 2;
2718 #endif
2719 } s;
2720 struct cvmx_npi_int_sum_cn30xx {
2721 #ifdef __BIG_ENDIAN_BITFIELD
2722 uint64_t reserved_62_63 : 2;
2723 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */
2724 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */
2725 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */
2726 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */
2727 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */
2728 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */
2729 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
2730 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
2731 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */
2732 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */
2733 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */
2734 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */
2735 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */
2736 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */
2737 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */
2738 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */
2739 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */
2740 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */
2741 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */
2742 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */
2743 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2744 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2745 from the PCI this bit may be set. */
2746 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2747 uint64_t reserved_36_38 : 3;
2748 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2749 this bit may be set. */
2750 uint64_t reserved_32_34 : 3;
2751 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2752 pair. */
2753 uint64_t reserved_28_30 : 3;
2754 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2755 pointer-pair, this bit may be set. */
2756 uint64_t reserved_24_26 : 3;
2757 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2758 read a gather list. */
2759 uint64_t reserved_20_22 : 3;
2760 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
2761 data this bit may be set. */
2762 uint64_t reserved_16_18 : 3;
2763 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2764 read packet data. */
2765 uint64_t reserved_12_14 : 3;
2766 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
2767 doorbell count was set. */
2768 uint64_t reserved_8_10 : 3;
2769 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2770 read instructions. */
2771 uint64_t reserved_4_6 : 3;
2772 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
2773 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
2774 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
2775 corresponding bit in the PCI_INT_ENB2 is SET. */
2776 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
2777 back from a RSL after sending a write command to
2778 a RSL. */
2779 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
2780 back from a RSL after sending a read command to
2781 a RSL. */
2782 #else
2783 uint64_t rml_rto : 1;
2784 uint64_t rml_wto : 1;
2785 uint64_t pci_rsl : 1;
2786 uint64_t po0_2sml : 1;
2787 uint64_t reserved_4_6 : 3;
2788 uint64_t i0_rtout : 1;
2789 uint64_t reserved_8_10 : 3;
2790 uint64_t i0_overf : 1;
2791 uint64_t reserved_12_14 : 3;
2792 uint64_t p0_rtout : 1;
2793 uint64_t reserved_16_18 : 3;
2794 uint64_t p0_perr : 1;
2795 uint64_t reserved_20_22 : 3;
2796 uint64_t g0_rtout : 1;
2797 uint64_t reserved_24_26 : 3;
2798 uint64_t p0_pperr : 1;
2799 uint64_t reserved_28_30 : 3;
2800 uint64_t p0_ptout : 1;
2801 uint64_t reserved_32_34 : 3;
2802 uint64_t i0_pperr : 1;
2803 uint64_t reserved_36_38 : 3;
2804 uint64_t win_rto : 1;
2805 uint64_t p_dperr : 1;
2806 uint64_t iobdma : 1;
2807 uint64_t fcr_s_e : 1;
2808 uint64_t fcr_a_f : 1;
2809 uint64_t pcr_s_e : 1;
2810 uint64_t pcr_a_f : 1;
2811 uint64_t q2_s_e : 1;
2812 uint64_t q2_a_f : 1;
2813 uint64_t q3_s_e : 1;
2814 uint64_t q3_a_f : 1;
2815 uint64_t com_s_e : 1;
2816 uint64_t com_a_f : 1;
2817 uint64_t pnc_s_e : 1;
2818 uint64_t pnc_a_f : 1;
2819 uint64_t rwx_s_e : 1;
2820 uint64_t rdx_s_e : 1;
2821 uint64_t pcf_p_e : 1;
2822 uint64_t pcf_p_f : 1;
2823 uint64_t pdf_p_e : 1;
2824 uint64_t pdf_p_f : 1;
2825 uint64_t q1_s_e : 1;
2826 uint64_t q1_a_f : 1;
2827 uint64_t reserved_62_63 : 2;
2828 #endif
2829 } cn30xx;
2830 struct cvmx_npi_int_sum_cn31xx {
2831 #ifdef __BIG_ENDIAN_BITFIELD
2832 uint64_t reserved_62_63 : 2;
2833 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */
2834 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */
2835 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */
2836 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */
2837 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */
2838 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */
2839 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
2840 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
2841 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */
2842 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */
2843 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */
2844 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */
2845 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */
2846 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */
2847 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */
2848 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */
2849 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */
2850 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */
2851 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */
2852 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */
2853 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2854 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2855 from the PCI this bit may be set. */
2856 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2857 uint64_t reserved_37_38 : 2;
2858 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction
2859 this bit may be set. */
2860 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2861 this bit may be set. */
2862 uint64_t reserved_33_34 : 2;
2863 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO
2864 pair. */
2865 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2866 pair. */
2867 uint64_t reserved_29_30 : 2;
2868 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2869 pointer-pair, this bit may be set. */
2870 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2871 pointer-pair, this bit may be set. */
2872 uint64_t reserved_25_26 : 2;
2873 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2874 read a gather list. */
2875 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2876 read a gather list. */
2877 uint64_t reserved_21_22 : 2;
2878 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet
2879 data this bit may be set. */
2880 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
2881 data this bit may be set. */
2882 uint64_t reserved_17_18 : 2;
2883 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2884 read packet data. */
2885 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2886 read packet data. */
2887 uint64_t reserved_13_14 : 2;
2888 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the
2889 doorbell count was set. */
2890 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
2891 doorbell count was set. */
2892 uint64_t reserved_9_10 : 2;
2893 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to
2894 read instructions. */
2895 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
2896 read instructions. */
2897 uint64_t reserved_5_6 : 2;
2898 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller
2899 than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
2900 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
2901 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
2902 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
2903 corresponding bit in the PCI_INT_ENB2 is SET. */
2904 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
2905 back from a RSL after sending a write command to
2906 a RSL. */
2907 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
2908 back from a RSL after sending a read command to
2909 a RSL. */
2910 #else
2911 uint64_t rml_rto : 1;
2912 uint64_t rml_wto : 1;
2913 uint64_t pci_rsl : 1;
2914 uint64_t po0_2sml : 1;
2915 uint64_t po1_2sml : 1;
2916 uint64_t reserved_5_6 : 2;
2917 uint64_t i0_rtout : 1;
2918 uint64_t i1_rtout : 1;
2919 uint64_t reserved_9_10 : 2;
2920 uint64_t i0_overf : 1;
2921 uint64_t i1_overf : 1;
2922 uint64_t reserved_13_14 : 2;
2923 uint64_t p0_rtout : 1;
2924 uint64_t p1_rtout : 1;
2925 uint64_t reserved_17_18 : 2;
2926 uint64_t p0_perr : 1;
2927 uint64_t p1_perr : 1;
2928 uint64_t reserved_21_22 : 2;
2929 uint64_t g0_rtout : 1;
2930 uint64_t g1_rtout : 1;
2931 uint64_t reserved_25_26 : 2;
2932 uint64_t p0_pperr : 1;
2933 uint64_t p1_pperr : 1;
2934 uint64_t reserved_29_30 : 2;
2935 uint64_t p0_ptout : 1;
2936 uint64_t p1_ptout : 1;
2937 uint64_t reserved_33_34 : 2;
2938 uint64_t i0_pperr : 1;
2939 uint64_t i1_pperr : 1;
2940 uint64_t reserved_37_38 : 2;
2941 uint64_t win_rto : 1;
2942 uint64_t p_dperr : 1;
2943 uint64_t iobdma : 1;
2944 uint64_t fcr_s_e : 1;
2945 uint64_t fcr_a_f : 1;
2946 uint64_t pcr_s_e : 1;
2947 uint64_t pcr_a_f : 1;
2948 uint64_t q2_s_e : 1;
2949 uint64_t q2_a_f : 1;
2950 uint64_t q3_s_e : 1;
2951 uint64_t q3_a_f : 1;
2952 uint64_t com_s_e : 1;
2953 uint64_t com_a_f : 1;
2954 uint64_t pnc_s_e : 1;
2955 uint64_t pnc_a_f : 1;
2956 uint64_t rwx_s_e : 1;
2957 uint64_t rdx_s_e : 1;
2958 uint64_t pcf_p_e : 1;
2959 uint64_t pcf_p_f : 1;
2960 uint64_t pdf_p_e : 1;
2961 uint64_t pdf_p_f : 1;
2962 uint64_t q1_s_e : 1;
2963 uint64_t q1_a_f : 1;
2964 uint64_t reserved_62_63 : 2;
2965 #endif
2966 } cn31xx;
2967 struct cvmx_npi_int_sum_s cn38xx;
2968 struct cvmx_npi_int_sum_cn38xxp2 {
2969 #ifdef __BIG_ENDIAN_BITFIELD
2970 uint64_t reserved_42_63 : 22;
2971 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */
2972 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C
2973 from the PCI this bit may be set. */
2974 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */
2975 uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction
2976 this bit may be set. */
2977 uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction
2978 this bit may be set. */
2979 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction
2980 this bit may be set. */
2981 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction
2982 this bit may be set. */
2983 uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO
2984 pair. */
2985 uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO
2986 pair. */
2987 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO
2988 pair. */
2989 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO
2990 pair. */
2991 uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2992 pointer-pair, this bit may be set. */
2993 uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2994 pointer-pair, this bit may be set. */
2995 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2996 pointer-pair, this bit may be set. */
2997 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO
2998 pointer-pair, this bit may be set. */
2999 uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to
3000 read a gather list. */
3001 uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to
3002 read a gather list. */
3003 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to
3004 read a gather list. */
3005 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to
3006 read a gather list. */
3007 uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet
3008 data this bit may be set. */
3009 uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet
3010 data this bit may be set. */
3011 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet
3012 data this bit may be set. */
3013 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet
3014 data this bit may be set. */
3015 uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to
3016 read packet data. */
3017 uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to
3018 read packet data. */
3019 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to
3020 read packet data. */
3021 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to
3022 read packet data. */
3023 uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the
3024 doorbell count was set. */
3025 uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the
3026 doorbell count was set. */
3027 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the
3028 doorbell count was set. */
3029 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the
3030 doorbell count was set. */
3031 uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to
3032 read instructions. */
3033 uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to
3034 read instructions. */
3035 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to
3036 read instructions. */
3037 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to
3038 read instructions. */
3039 uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller
3040 than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
3041 uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller
3042 than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
3043 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller
3044 than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
3045 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller
3046 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
3047 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
3048 corresponding bit in the PCI_INT_ENB2 is SET. */
3049 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit
3050 back from a RSL after sending a write command to
3051 a RSL. */
3052 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data
3053 back from a RSL after sending a read command to
3054 a RSL. */
3055 #else
3056 uint64_t rml_rto : 1;
3057 uint64_t rml_wto : 1;
3058 uint64_t pci_rsl : 1;
3059 uint64_t po0_2sml : 1;
3060 uint64_t po1_2sml : 1;
3061 uint64_t po2_2sml : 1;
3062 uint64_t po3_2sml : 1;
3063 uint64_t i0_rtout : 1;
3064 uint64_t i1_rtout : 1;
3065 uint64_t i2_rtout : 1;
3066 uint64_t i3_rtout : 1;
3067 uint64_t i0_overf : 1;
3068 uint64_t i1_overf : 1;
3069 uint64_t i2_overf : 1;
3070 uint64_t i3_overf : 1;
3071 uint64_t p0_rtout : 1;
3072 uint64_t p1_rtout : 1;
3073 uint64_t p2_rtout : 1;
3074 uint64_t p3_rtout : 1;
3075 uint64_t p0_perr : 1;
3076 uint64_t p1_perr : 1;
3077 uint64_t p2_perr : 1;
3078 uint64_t p3_perr : 1;
3079 uint64_t g0_rtout : 1;
3080 uint64_t g1_rtout : 1;
3081 uint64_t g2_rtout : 1;
3082 uint64_t g3_rtout : 1;
3083 uint64_t p0_pperr : 1;
3084 uint64_t p1_pperr : 1;
3085 uint64_t p2_pperr : 1;
3086 uint64_t p3_pperr : 1;
3087 uint64_t p0_ptout : 1;
3088 uint64_t p1_ptout : 1;
3089 uint64_t p2_ptout : 1;
3090 uint64_t p3_ptout : 1;
3091 uint64_t i0_pperr : 1;
3092 uint64_t i1_pperr : 1;
3093 uint64_t i2_pperr : 1;
3094 uint64_t i3_pperr : 1;
3095 uint64_t win_rto : 1;
3096 uint64_t p_dperr : 1;
3097 uint64_t iobdma : 1;
3098 uint64_t reserved_42_63 : 22;
3099 #endif
3100 } cn38xxp2;
3101 struct cvmx_npi_int_sum_cn31xx cn50xx;
3102 struct cvmx_npi_int_sum_s cn58xx;
3103 struct cvmx_npi_int_sum_s cn58xxp1;
3104 };
3105 typedef union cvmx_npi_int_sum cvmx_npi_int_sum_t;
3106
3107 /**
3108 * cvmx_npi_lowp_dbell
3109 *
3110 * NPI_LOWP_DBELL = Low Priority Door Bell
3111 *
3112 * The door bell register for the low priority DMA queue.
3113 */
3114 union cvmx_npi_lowp_dbell {
3115 uint64_t u64;
3116 struct cvmx_npi_lowp_dbell_s {
3117 #ifdef __BIG_ENDIAN_BITFIELD
3118 uint64_t reserved_16_63 : 48;
3119 uint64_t dbell : 16; /**< The value written to this register is added to the
3120 number of 8byte words to be read and processes for
3121 the low priority dma queue. */
3122 #else
3123 uint64_t dbell : 16;
3124 uint64_t reserved_16_63 : 48;
3125 #endif
3126 } s;
3127 struct cvmx_npi_lowp_dbell_s cn30xx;
3128 struct cvmx_npi_lowp_dbell_s cn31xx;
3129 struct cvmx_npi_lowp_dbell_s cn38xx;
3130 struct cvmx_npi_lowp_dbell_s cn38xxp2;
3131 struct cvmx_npi_lowp_dbell_s cn50xx;
3132 struct cvmx_npi_lowp_dbell_s cn58xx;
3133 struct cvmx_npi_lowp_dbell_s cn58xxp1;
3134 };
3135 typedef union cvmx_npi_lowp_dbell cvmx_npi_lowp_dbell_t;
3136
3137 /**
3138 * cvmx_npi_lowp_ibuff_saddr
3139 *
3140 * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address
3141 *
3142 * The address to start reading Instructions from for LOWP.
3143 */
3144 union cvmx_npi_lowp_ibuff_saddr {
3145 uint64_t u64;
3146 struct cvmx_npi_lowp_ibuff_saddr_s {
3147 #ifdef __BIG_ENDIAN_BITFIELD
3148 uint64_t reserved_36_63 : 28;
3149 uint64_t saddr : 36; /**< The starting address to read the first instruction. */
3150 #else
3151 uint64_t saddr : 36;
3152 uint64_t reserved_36_63 : 28;
3153 #endif
3154 } s;
3155 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
3156 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
3157 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
3158 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
3159 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
3160 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
3161 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
3162 };
3163 typedef union cvmx_npi_lowp_ibuff_saddr cvmx_npi_lowp_ibuff_saddr_t;
3164
3165 /**
3166 * cvmx_npi_mem_access_subid#
3167 *
3168 * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register
3169 *
3170 * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3.
3171 * Writes to this register are not ordered with writes/reads to the PCI Memory space.
3172 * To ensure that a write has completed the user must read the register before
3173 * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
3174 */
3175 union cvmx_npi_mem_access_subidx {
3176 uint64_t u64;
3177 struct cvmx_npi_mem_access_subidx_s {
3178 #ifdef __BIG_ENDIAN_BITFIELD
3179 uint64_t reserved_38_63 : 26;
3180 uint64_t shortl : 1; /**< Generate CMD-6 on PCI(x) when '1'.
3181 Loads from the cores to the corresponding subid
3182 that are 32-bits or smaller:
3183 - Will generate the PCI-X "Memory Read DWORD"
3184 command in PCI-X mode. (Note that "Memory
3185 Read DWORD" appears much like an IO read on
3186 the PCI-X bus.)
3187 - Will generate the PCI "Memory Read" command
3188 in PCI-X mode, irrespective of the
3189 NPI_PCI_READ_CMD[CMD_SIZE] value.
3190 NOT IN PASS 1 NOR PASS 2 */
3191 uint64_t nmerge : 1; /**< No Merge. (NOT IN PASS 1 NOR PASS 2) */
3192 uint64_t esr : 2; /**< Endian-Swap on read. */
3193 uint64_t esw : 2; /**< Endian-Swap on write. */
3194 uint64_t nsr : 1; /**< No-Snoop on read. */
3195 uint64_t nsw : 1; /**< No-Snoop on write. */
3196 uint64_t ror : 1; /**< Relax Read on read. */
3197 uint64_t row : 1; /**< Relax Order on write. */
3198 uint64_t ba : 28; /**< PCI Address bits [63:36]. */
3199 #else
3200 uint64_t ba : 28;
3201 uint64_t row : 1;
3202 uint64_t ror : 1;
3203 uint64_t nsw : 1;
3204 uint64_t nsr : 1;
3205 uint64_t esw : 2;
3206 uint64_t esr : 2;
3207 uint64_t nmerge : 1;
3208 uint64_t shortl : 1;
3209 uint64_t reserved_38_63 : 26;
3210 #endif
3211 } s;
3212 struct cvmx_npi_mem_access_subidx_s cn30xx;
3213 struct cvmx_npi_mem_access_subidx_cn31xx {
3214 #ifdef __BIG_ENDIAN_BITFIELD
3215 uint64_t reserved_36_63 : 28;
3216 uint64_t esr : 2; /**< Endian-Swap on read. */
3217 uint64_t esw : 2; /**< Endian-Swap on write. */
3218 uint64_t nsr : 1; /**< No-Snoop on read. */
3219 uint64_t nsw : 1; /**< No-Snoop on write. */
3220 uint64_t ror : 1; /**< Relax Read on read. */
3221 uint64_t row : 1; /**< Relax Order on write. */
3222 uint64_t ba : 28; /**< PCI Address bits [63:36]. */
3223 #else
3224 uint64_t ba : 28;
3225 uint64_t row : 1;
3226 uint64_t ror : 1;
3227 uint64_t nsw : 1;
3228 uint64_t nsr : 1;
3229 uint64_t esw : 2;
3230 uint64_t esr : 2;
3231 uint64_t reserved_36_63 : 28;
3232 #endif
3233 } cn31xx;
3234 struct cvmx_npi_mem_access_subidx_s cn38xx;
3235 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
3236 struct cvmx_npi_mem_access_subidx_s cn50xx;
3237 struct cvmx_npi_mem_access_subidx_s cn58xx;
3238 struct cvmx_npi_mem_access_subidx_s cn58xxp1;
3239 };
3240 typedef union cvmx_npi_mem_access_subidx cvmx_npi_mem_access_subidx_t;
3241
3242 /**
3243 * cvmx_npi_msi_rcv
3244 *
3245 * NPI_MSI_RCV = NPI MSI Receive Vector Register
3246 *
3247 * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register.
3248 */
3249 union cvmx_npi_msi_rcv {
3250 uint64_t u64;
3251 struct cvmx_npi_msi_rcv_s {
3252 #ifdef __BIG_ENDIAN_BITFIELD
3253 uint64_t int_vec : 64; /**< Refer to PCI_MSI_RCV */
3254 #else
3255 uint64_t int_vec : 64;
3256 #endif
3257 } s;
3258 struct cvmx_npi_msi_rcv_s cn30xx;
3259 struct cvmx_npi_msi_rcv_s cn31xx;
3260 struct cvmx_npi_msi_rcv_s cn38xx;
3261 struct cvmx_npi_msi_rcv_s cn38xxp2;
3262 struct cvmx_npi_msi_rcv_s cn50xx;
3263 struct cvmx_npi_msi_rcv_s cn58xx;
3264 struct cvmx_npi_msi_rcv_s cn58xxp1;
3265 };
3266 typedef union cvmx_npi_msi_rcv cvmx_npi_msi_rcv_t;
3267
3268 /**
3269 * cvmx_npi_num_desc_output#
3270 *
3271 * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0
3272 *
3273 * The size of the Buffer/Info Pointer Pair ring for Output-0.
3274 */
3275 union cvmx_npi_num_desc_outputx {
3276 uint64_t u64;
3277 struct cvmx_npi_num_desc_outputx_s {
3278 #ifdef __BIG_ENDIAN_BITFIELD
3279 uint64_t reserved_32_63 : 32;
3280 uint64_t size : 32; /**< The size of the Buffer/Info Pointer Pair ring. */
3281 #else
3282 uint64_t size : 32;
3283 uint64_t reserved_32_63 : 32;
3284 #endif
3285 } s;
3286 struct cvmx_npi_num_desc_outputx_s cn30xx;
3287 struct cvmx_npi_num_desc_outputx_s cn31xx;
3288 struct cvmx_npi_num_desc_outputx_s cn38xx;
3289 struct cvmx_npi_num_desc_outputx_s cn38xxp2;
3290 struct cvmx_npi_num_desc_outputx_s cn50xx;
3291 struct cvmx_npi_num_desc_outputx_s cn58xx;
3292 struct cvmx_npi_num_desc_outputx_s cn58xxp1;
3293 };
3294 typedef union cvmx_npi_num_desc_outputx cvmx_npi_num_desc_outputx_t;
3295
3296 /**
3297 * cvmx_npi_output_control
3298 *
3299 * NPI_OUTPUT_CONTROL = NPI's Output Control Register
3300 *
3301 * The address to start reading Instructions from for Output-3.
3302 */
3303 union cvmx_npi_output_control {
3304 uint64_t u64;
3305 struct cvmx_npi_output_control_s {
3306 #ifdef __BIG_ENDIAN_BITFIELD
3307 uint64_t reserved_49_63 : 15;
3308 uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be
3309 made with a Round Robin arbitration. When '0'
3310 the output packet port is fixed in priority,
3311 where the lower port number has higher priority.
3312 PASS3 Field */
3313 uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be
3314 updated with the number of bytes in the packet
3315 sent, when '0' the register will have a value
3316 of '1' added. */
3317 uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be
3318 updated with the number of bytes in the packet
3319 sent, when '0' the register will have a value
3320 of '1' added. */
3321 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3322 updated with the number of bytes in the packet
3323 sent, when '0' the register will have a value
3324 of '1' added. */
3325 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3326 updated with the number of bytes in the packet
3327 sent, when '0' the register will have a value
3328 of '1' added. */
3329 uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */
3330 uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */
3331 uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */
3332 uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */
3333 uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */
3334 uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */
3335 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3336 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3337 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3338 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3339 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3340 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3341 uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3342 comes from the DPTR[63:60] in the scatter-list pair,
3343 and the RO, NS, ES values come from the O3_ES,
3344 O3_NS, O3_RO. When '0' the RO == DPTR[60],
3345 NS == DPTR[61], ES == DPTR[63:62], the address the
3346 packet will be written to is ADDR[63:60] ==
3347 O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
3348 uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3349 comes from the DPTR[63:60] in the scatter-list pair,
3350 and the RO, NS, ES values come from the O2_ES,
3351 O2_NS, O2_RO. When '0' the RO == DPTR[60],
3352 NS == DPTR[61], ES == DPTR[63:62], the address the
3353 packet will be written to is ADDR[63:60] ==
3354 O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
3355 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3356 comes from the DPTR[63:60] in the scatter-list pair,
3357 and the RO, NS, ES values come from the O1_ES,
3358 O1_NS, O1_RO. When '0' the RO == DPTR[60],
3359 NS == DPTR[61], ES == DPTR[63:62], the address the
3360 packet will be written to is ADDR[63:60] ==
3361 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
3362 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3363 comes from the DPTR[63:60] in the scatter-list pair,
3364 and the RO, NS, ES values come from the O0_ES,
3365 O0_NS, O0_RO. When '0' the RO == DPTR[60],
3366 NS == DPTR[61], ES == DPTR[63:62], the address the
3367 packet will be written to is ADDR[63:60] ==
3368 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
3369 uint64_t reserved_20_23 : 4;
3370 uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data
3371 for output-3. */
3372 uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data
3373 for output-2. */
3374 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3375 for output-1. */
3376 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3377 for output-0. */
3378 uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */
3379 uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */
3380 uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */
3381 uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */
3382 uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */
3383 uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */
3384 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3385 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3386 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3387 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3388 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3389 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3390 #else
3391 uint64_t ror_sl0 : 1;
3392 uint64_t nsr_sl0 : 1;
3393 uint64_t esr_sl0 : 2;
3394 uint64_t ror_sl1 : 1;
3395 uint64_t nsr_sl1 : 1;
3396 uint64_t esr_sl1 : 2;
3397 uint64_t ror_sl2 : 1;
3398 uint64_t nsr_sl2 : 1;
3399 uint64_t esr_sl2 : 2;
3400 uint64_t ror_sl3 : 1;
3401 uint64_t nsr_sl3 : 1;
3402 uint64_t esr_sl3 : 2;
3403 uint64_t iptr_o0 : 1;
3404 uint64_t iptr_o1 : 1;
3405 uint64_t iptr_o2 : 1;
3406 uint64_t iptr_o3 : 1;
3407 uint64_t reserved_20_23 : 4;
3408 uint64_t o0_csrm : 1;
3409 uint64_t o1_csrm : 1;
3410 uint64_t o2_csrm : 1;
3411 uint64_t o3_csrm : 1;
3412 uint64_t o0_ro : 1;
3413 uint64_t o0_ns : 1;
3414 uint64_t o0_es : 2;
3415 uint64_t o1_ro : 1;
3416 uint64_t o1_ns : 1;
3417 uint64_t o1_es : 2;
3418 uint64_t o2_ro : 1;
3419 uint64_t o2_ns : 1;
3420 uint64_t o2_es : 2;
3421 uint64_t o3_ro : 1;
3422 uint64_t o3_ns : 1;
3423 uint64_t o3_es : 2;
3424 uint64_t p0_bmode : 1;
3425 uint64_t p1_bmode : 1;
3426 uint64_t p2_bmode : 1;
3427 uint64_t p3_bmode : 1;
3428 uint64_t pkt_rr : 1;
3429 uint64_t reserved_49_63 : 15;
3430 #endif
3431 } s;
3432 struct cvmx_npi_output_control_cn30xx {
3433 #ifdef __BIG_ENDIAN_BITFIELD
3434 uint64_t reserved_45_63 : 19;
3435 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3436 updated with the number of bytes in the packet
3437 sent, when '0' the register will have a value
3438 of '1' added. */
3439 uint64_t reserved_32_43 : 12;
3440 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3441 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3442 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3443 uint64_t reserved_25_27 : 3;
3444 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3445 comes from the DPTR[63:60] in the scatter-list pair,
3446 and the RO, NS, ES values come from the O0_ES,
3447 O0_NS, O0_RO. When '0' the RO == DPTR[60],
3448 NS == DPTR[61], ES == DPTR[63:62], the address the
3449 packet will be written to is ADDR[63:60] ==
3450 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
3451 uint64_t reserved_17_23 : 7;
3452 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3453 for output-0. */
3454 uint64_t reserved_4_15 : 12;
3455 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3456 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3457 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3458 #else
3459 uint64_t ror_sl0 : 1;
3460 uint64_t nsr_sl0 : 1;
3461 uint64_t esr_sl0 : 2;
3462 uint64_t reserved_4_15 : 12;
3463 uint64_t iptr_o0 : 1;
3464 uint64_t reserved_17_23 : 7;
3465 uint64_t o0_csrm : 1;
3466 uint64_t reserved_25_27 : 3;
3467 uint64_t o0_ro : 1;
3468 uint64_t o0_ns : 1;
3469 uint64_t o0_es : 2;
3470 uint64_t reserved_32_43 : 12;
3471 uint64_t p0_bmode : 1;
3472 uint64_t reserved_45_63 : 19;
3473 #endif
3474 } cn30xx;
3475 struct cvmx_npi_output_control_cn31xx {
3476 #ifdef __BIG_ENDIAN_BITFIELD
3477 uint64_t reserved_46_63 : 18;
3478 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3479 updated with the number of bytes in the packet
3480 sent, when '0' the register will have a value
3481 of '1' added. */
3482 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3483 updated with the number of bytes in the packet
3484 sent, when '0' the register will have a value
3485 of '1' added. */
3486 uint64_t reserved_36_43 : 8;
3487 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3488 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3489 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3490 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3491 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3492 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3493 uint64_t reserved_26_27 : 2;
3494 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3495 comes from the DPTR[63:60] in the scatter-list pair,
3496 and the RO, NS, ES values come from the O1_ES,
3497 O1_NS, O1_RO. When '0' the RO == DPTR[60],
3498 NS == DPTR[61], ES == DPTR[63:62], the address the
3499 packet will be written to is ADDR[63:60] ==
3500 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
3501 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3502 comes from the DPTR[63:60] in the scatter-list pair,
3503 and the RO, NS, ES values come from the O0_ES,
3504 O0_NS, O0_RO. When '0' the RO == DPTR[60],
3505 NS == DPTR[61], ES == DPTR[63:62], the address the
3506 packet will be written to is ADDR[63:60] ==
3507 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
3508 uint64_t reserved_18_23 : 6;
3509 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3510 for output-1. */
3511 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3512 for output-0. */
3513 uint64_t reserved_8_15 : 8;
3514 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3515 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3516 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3517 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3518 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3519 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3520 #else
3521 uint64_t ror_sl0 : 1;
3522 uint64_t nsr_sl0 : 1;
3523 uint64_t esr_sl0 : 2;
3524 uint64_t ror_sl1 : 1;
3525 uint64_t nsr_sl1 : 1;
3526 uint64_t esr_sl1 : 2;
3527 uint64_t reserved_8_15 : 8;
3528 uint64_t iptr_o0 : 1;
3529 uint64_t iptr_o1 : 1;
3530 uint64_t reserved_18_23 : 6;
3531 uint64_t o0_csrm : 1;
3532 uint64_t o1_csrm : 1;
3533 uint64_t reserved_26_27 : 2;
3534 uint64_t o0_ro : 1;
3535 uint64_t o0_ns : 1;
3536 uint64_t o0_es : 2;
3537 uint64_t o1_ro : 1;
3538 uint64_t o1_ns : 1;
3539 uint64_t o1_es : 2;
3540 uint64_t reserved_36_43 : 8;
3541 uint64_t p0_bmode : 1;
3542 uint64_t p1_bmode : 1;
3543 uint64_t reserved_46_63 : 18;
3544 #endif
3545 } cn31xx;
3546 struct cvmx_npi_output_control_s cn38xx;
3547 struct cvmx_npi_output_control_cn38xxp2 {
3548 #ifdef __BIG_ENDIAN_BITFIELD
3549 uint64_t reserved_48_63 : 16;
3550 uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be
3551 updated with the number of bytes in the packet
3552 sent, when '0' the register will have a value
3553 of '1' added. */
3554 uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be
3555 updated with the number of bytes in the packet
3556 sent, when '0' the register will have a value
3557 of '1' added. */
3558 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3559 updated with the number of bytes in the packet
3560 sent, when '0' the register will have a value
3561 of '1' added. */
3562 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3563 updated with the number of bytes in the packet
3564 sent, when '0' the register will have a value
3565 of '1' added. */
3566 uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */
3567 uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */
3568 uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */
3569 uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */
3570 uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */
3571 uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */
3572 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3573 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3574 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3575 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3576 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3577 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3578 uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3579 comes from the DPTR[63:60] in the scatter-list pair,
3580 and the RO, NS, ES values come from the O3_ES,
3581 O3_NS, O3_RO. When '0' the RO == DPTR[60],
3582 NS == DPTR[61], ES == DPTR[63:62], the address the
3583 packet will be written to is ADDR[63:60] ==
3584 O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
3585 uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3586 comes from the DPTR[63:60] in the scatter-list pair,
3587 and the RO, NS, ES values come from the O2_ES,
3588 O2_NS, O2_RO. When '0' the RO == DPTR[60],
3589 NS == DPTR[61], ES == DPTR[63:62], the address the
3590 packet will be written to is ADDR[63:60] ==
3591 O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
3592 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3593 comes from the DPTR[63:60] in the scatter-list pair,
3594 and the RO, NS, ES values come from the O1_ES,
3595 O1_NS, O1_RO. When '0' the RO == DPTR[60],
3596 NS == DPTR[61], ES == DPTR[63:62], the address the
3597 packet will be written to is ADDR[63:60] ==
3598 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
3599 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3600 comes from the DPTR[63:60] in the scatter-list pair,
3601 and the RO, NS, ES values come from the O0_ES,
3602 O0_NS, O0_RO. When '0' the RO == DPTR[60],
3603 NS == DPTR[61], ES == DPTR[63:62], the address the
3604 packet will be written to is ADDR[63:60] ==
3605 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
3606 uint64_t reserved_20_23 : 4;
3607 uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data
3608 for output-3. */
3609 uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data
3610 for output-2. */
3611 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3612 for output-1. */
3613 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3614 for output-0. */
3615 uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */
3616 uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */
3617 uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */
3618 uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */
3619 uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */
3620 uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */
3621 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3622 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3623 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3624 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3625 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3626 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3627 #else
3628 uint64_t ror_sl0 : 1;
3629 uint64_t nsr_sl0 : 1;
3630 uint64_t esr_sl0 : 2;
3631 uint64_t ror_sl1 : 1;
3632 uint64_t nsr_sl1 : 1;
3633 uint64_t esr_sl1 : 2;
3634 uint64_t ror_sl2 : 1;
3635 uint64_t nsr_sl2 : 1;
3636 uint64_t esr_sl2 : 2;
3637 uint64_t ror_sl3 : 1;
3638 uint64_t nsr_sl3 : 1;
3639 uint64_t esr_sl3 : 2;
3640 uint64_t iptr_o0 : 1;
3641 uint64_t iptr_o1 : 1;
3642 uint64_t iptr_o2 : 1;
3643 uint64_t iptr_o3 : 1;
3644 uint64_t reserved_20_23 : 4;
3645 uint64_t o0_csrm : 1;
3646 uint64_t o1_csrm : 1;
3647 uint64_t o2_csrm : 1;
3648 uint64_t o3_csrm : 1;
3649 uint64_t o0_ro : 1;
3650 uint64_t o0_ns : 1;
3651 uint64_t o0_es : 2;
3652 uint64_t o1_ro : 1;
3653 uint64_t o1_ns : 1;
3654 uint64_t o1_es : 2;
3655 uint64_t o2_ro : 1;
3656 uint64_t o2_ns : 1;
3657 uint64_t o2_es : 2;
3658 uint64_t o3_ro : 1;
3659 uint64_t o3_ns : 1;
3660 uint64_t o3_es : 2;
3661 uint64_t p0_bmode : 1;
3662 uint64_t p1_bmode : 1;
3663 uint64_t p2_bmode : 1;
3664 uint64_t p3_bmode : 1;
3665 uint64_t reserved_48_63 : 16;
3666 #endif
3667 } cn38xxp2;
3668 struct cvmx_npi_output_control_cn50xx {
3669 #ifdef __BIG_ENDIAN_BITFIELD
3670 uint64_t reserved_49_63 : 15;
3671 uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be
3672 made with a Round Robin arbitration. When '0'
3673 the output packet port is fixed in priority,
3674 where the lower port number has higher priority.
3675 PASS2 Field */
3676 uint64_t reserved_46_47 : 2;
3677 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be
3678 updated with the number of bytes in the packet
3679 sent, when '0' the register will have a value
3680 of '1' added. */
3681 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be
3682 updated with the number of bytes in the packet
3683 sent, when '0' the register will have a value
3684 of '1' added. */
3685 uint64_t reserved_36_43 : 8;
3686 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */
3687 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */
3688 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */
3689 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */
3690 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */
3691 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */
3692 uint64_t reserved_26_27 : 2;
3693 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3694 comes from the DPTR[63:60] in the scatter-list pair,
3695 and the RO, NS, ES values come from the O1_ES,
3696 O1_NS, O1_RO. When '0' the RO == DPTR[60],
3697 NS == DPTR[61], ES == DPTR[63:62], the address the
3698 packet will be written to is ADDR[63:60] ==
3699 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
3700 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data,
3701 comes from the DPTR[63:60] in the scatter-list pair,
3702 and the RO, NS, ES values come from the O0_ES,
3703 O0_NS, O0_RO. When '0' the RO == DPTR[60],
3704 NS == DPTR[61], ES == DPTR[63:62], the address the
3705 packet will be written to is ADDR[63:60] ==
3706 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
3707 uint64_t reserved_18_23 : 6;
3708 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data
3709 for output-1. */
3710 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data
3711 for output-0. */
3712 uint64_t reserved_8_15 : 8;
3713 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */
3714 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */
3715 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */
3716 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */
3717 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */
3718 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */
3719 #else
3720 uint64_t ror_sl0 : 1;
3721 uint64_t nsr_sl0 : 1;
3722 uint64_t esr_sl0 : 2;
3723 uint64_t ror_sl1 : 1;
3724 uint64_t nsr_sl1 : 1;
3725 uint64_t esr_sl1 : 2;
3726 uint64_t reserved_8_15 : 8;
3727 uint64_t iptr_o0 : 1;
3728 uint64_t iptr_o1 : 1;
3729 uint64_t reserved_18_23 : 6;
3730 uint64_t o0_csrm : 1;
3731 uint64_t o1_csrm : 1;
3732 uint64_t reserved_26_27 : 2;
3733 uint64_t o0_ro : 1;
3734 uint64_t o0_ns : 1;
3735 uint64_t o0_es : 2;
3736 uint64_t o1_ro : 1;
3737 uint64_t o1_ns : 1;
3738 uint64_t o1_es : 2;
3739 uint64_t reserved_36_43 : 8;
3740 uint64_t p0_bmode : 1;
3741 uint64_t p1_bmode : 1;
3742 uint64_t reserved_46_47 : 2;
3743 uint64_t pkt_rr : 1;
3744 uint64_t reserved_49_63 : 15;
3745 #endif
3746 } cn50xx;
3747 struct cvmx_npi_output_control_s cn58xx;
3748 struct cvmx_npi_output_control_s cn58xxp1;
3749 };
3750 typedef union cvmx_npi_output_control cvmx_npi_output_control_t;
3751
3752 /**
3753 * cvmx_npi_p#_dbpair_addr
3754 *
3755 * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address.
3756 *
3757 * Contains the next address to read for Port's-0 Data/Buffer Pair.
3758 */
3759 union cvmx_npi_px_dbpair_addr {
3760 uint64_t u64;
3761 struct cvmx_npi_px_dbpair_addr_s {
3762 #ifdef __BIG_ENDIAN_BITFIELD
3763 uint64_t reserved_63_63 : 1;
3764 uint64_t state : 2; /**< POS state machine vector. Used to tell when NADDR
3765 is valid (when STATE == 0). */
3766 uint64_t naddr : 61; /**< Bits [63:3] of the next Data-Info Pair to read.
3767 Value is only valid when STATE == 0. */
3768 #else
3769 uint64_t naddr : 61;
3770 uint64_t state : 2;
3771 uint64_t reserved_63_63 : 1;
3772 #endif
3773 } s;
3774 struct cvmx_npi_px_dbpair_addr_s cn30xx;
3775 struct cvmx_npi_px_dbpair_addr_s cn31xx;
3776 struct cvmx_npi_px_dbpair_addr_s cn38xx;
3777 struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
3778 struct cvmx_npi_px_dbpair_addr_s cn50xx;
3779 struct cvmx_npi_px_dbpair_addr_s cn58xx;
3780 struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
3781 };
3782 typedef union cvmx_npi_px_dbpair_addr cvmx_npi_px_dbpair_addr_t;
3783
3784 /**
3785 * cvmx_npi_p#_instr_addr
3786 *
3787 * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address.
3788 *
3789 * Contains the next address to read for Port's-0 Instructions.
3790 */
3791 union cvmx_npi_px_instr_addr {
3792 uint64_t u64;
3793 struct cvmx_npi_px_instr_addr_s {
3794 #ifdef __BIG_ENDIAN_BITFIELD
3795 uint64_t state : 3; /**< Gather engine state vector. Used to tell when
3796 NADDR is valid (when STATE == 0). */
3797 uint64_t naddr : 61; /**< Bits [63:3] of the next Instruction to read.
3798 Value is only valid when STATE == 0. */
3799 #else
3800 uint64_t naddr : 61;
3801 uint64_t state : 3;
3802 #endif
3803 } s;
3804 struct cvmx_npi_px_instr_addr_s cn30xx;
3805 struct cvmx_npi_px_instr_addr_s cn31xx;
3806 struct cvmx_npi_px_instr_addr_s cn38xx;
3807 struct cvmx_npi_px_instr_addr_s cn38xxp2;
3808 struct cvmx_npi_px_instr_addr_s cn50xx;
3809 struct cvmx_npi_px_instr_addr_s cn58xx;
3810 struct cvmx_npi_px_instr_addr_s cn58xxp1;
3811 };
3812 typedef union cvmx_npi_px_instr_addr cvmx_npi_px_instr_addr_t;
3813
3814 /**
3815 * cvmx_npi_p#_instr_cnts
3816 *
3817 * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In.
3818 *
3819 * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets.
3820 */
3821 union cvmx_npi_px_instr_cnts {
3822 uint64_t u64;
3823 struct cvmx_npi_px_instr_cnts_s {
3824 #ifdef __BIG_ENDIAN_BITFIELD
3825 uint64_t reserved_38_63 : 26;
3826 uint64_t fcnt : 6; /**< Number entries in the Instruction FIFO. */
3827 uint64_t avail : 32; /**< Doorbell count to be read. */
3828 #else
3829 uint64_t avail : 32;
3830 uint64_t fcnt : 6;
3831 uint64_t reserved_38_63 : 26;
3832 #endif
3833 } s;
3834 struct cvmx_npi_px_instr_cnts_s cn30xx;
3835 struct cvmx_npi_px_instr_cnts_s cn31xx;
3836 struct cvmx_npi_px_instr_cnts_s cn38xx;
3837 struct cvmx_npi_px_instr_cnts_s cn38xxp2;
3838 struct cvmx_npi_px_instr_cnts_s cn50xx;
3839 struct cvmx_npi_px_instr_cnts_s cn58xx;
3840 struct cvmx_npi_px_instr_cnts_s cn58xxp1;
3841 };
3842 typedef union cvmx_npi_px_instr_cnts cvmx_npi_px_instr_cnts_t;
3843
3844 /**
3845 * cvmx_npi_p#_pair_cnts
3846 *
3847 * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out.
3848 *
3849 * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets.
3850 */
3851 union cvmx_npi_px_pair_cnts {
3852 uint64_t u64;
3853 struct cvmx_npi_px_pair_cnts_s {
3854 #ifdef __BIG_ENDIAN_BITFIELD
3855 uint64_t reserved_37_63 : 27;
3856 uint64_t fcnt : 5; /**< 16 - number entries in the D/I Pair FIFO. */
3857 uint64_t avail : 32; /**< Doorbell count to be read. */
3858 #else
3859 uint64_t avail : 32;
3860 uint64_t fcnt : 5;
3861 uint64_t reserved_37_63 : 27;
3862 #endif
3863 } s;
3864 struct cvmx_npi_px_pair_cnts_s cn30xx;
3865 struct cvmx_npi_px_pair_cnts_s cn31xx;
3866 struct cvmx_npi_px_pair_cnts_s cn38xx;
3867 struct cvmx_npi_px_pair_cnts_s cn38xxp2;
3868 struct cvmx_npi_px_pair_cnts_s cn50xx;
3869 struct cvmx_npi_px_pair_cnts_s cn58xx;
3870 struct cvmx_npi_px_pair_cnts_s cn58xxp1;
3871 };
3872 typedef union cvmx_npi_px_pair_cnts cvmx_npi_px_pair_cnts_t;
3873
3874 /**
3875 * cvmx_npi_pci_burst_size
3876 *
3877 * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register
3878 *
3879 * Control the number of words the NPI will attempt to read / write to/from the PCI.
3880 */
3881 union cvmx_npi_pci_burst_size {
3882 uint64_t u64;
3883 struct cvmx_npi_pci_burst_size_s {
3884 #ifdef __BIG_ENDIAN_BITFIELD
3885 uint64_t reserved_14_63 : 50;
3886 uint64_t wr_brst : 7; /**< The number of 8B words to write to PCI in any one
3887 write operation. A zero is equal to 128. This
3888 value is used the packet reads and is clamped at
3889 a max of 112 for dma writes. */
3890 uint64_t rd_brst : 7; /**< Number of 8B words to read from PCI in any one
3891 read operation. Legal values are 1 to 127, where
3892 a 0 will be treated as a 1.
3893 "For reading of packet data value is limited to 64
3894 in PASS-2."
3895 This value does not control the size of a read
3896 caused by an IOBDMA from a PP. */
3897 #else
3898 uint64_t rd_brst : 7;
3899 uint64_t wr_brst : 7;
3900 uint64_t reserved_14_63 : 50;
3901 #endif
3902 } s;
3903 struct cvmx_npi_pci_burst_size_s cn30xx;
3904 struct cvmx_npi_pci_burst_size_s cn31xx;
3905 struct cvmx_npi_pci_burst_size_s cn38xx;
3906 struct cvmx_npi_pci_burst_size_s cn38xxp2;
3907 struct cvmx_npi_pci_burst_size_s cn50xx;
3908 struct cvmx_npi_pci_burst_size_s cn58xx;
3909 struct cvmx_npi_pci_burst_size_s cn58xxp1;
3910 };
3911 typedef union cvmx_npi_pci_burst_size cvmx_npi_pci_burst_size_t;
3912
3913 /**
3914 * cvmx_npi_pci_int_arb_cfg
3915 *
3916 * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter
3917 *
3918 * Controls operation of the Internal PCI Arbiter. This register should
3919 * only be written when PRST# is asserted. NPI_PCI_INT_ARB_CFG[EN] should
3920 * only be set when Octane is a host.
3921 */
3922 union cvmx_npi_pci_int_arb_cfg {
3923 uint64_t u64;
3924 struct cvmx_npi_pci_int_arb_cfg_s {
3925 #ifdef __BIG_ENDIAN_BITFIELD
3926 uint64_t reserved_13_63 : 51;
3927 uint64_t hostmode : 1; /**< PCI Host Mode Pin (sampled for use by software).
3928 This bit reflects the sampled PCI_HOSTMODE pin.
3929 In HOST Mode, OCTEON drives the PCI_CLK_OUT and
3930 PCI initialization pattern during PCI_RST_N deassertion). */
3931 uint64_t pci_ovr : 4; /**< PCI Host Mode Bus Speed/Type Override
3932 When in Host Mode(PCI_HOSTMODE pin =1), OCTEON acting
3933 as the PCI Central Agent, samples the PCI_PCI100,
3934 PCI_M66EN and PCI_PCIXCAP pins to determine the
3935 'sampled' PCI Bus speed and Bus Type (PCI or PCIX).
3936 (see: PCI_CNT_REG[HM_SPEED,HM_PCIX])
3937 However, in some cases, SW may want to override the
3938 the 'sampled' PCI Bus Type/Speed, and use some
3939 SLOWER Bus frequency.
3940 The PCI_OVR field encoding represents the 'override'
3941 PCI Bus Type/Speed which will be used to generate the
3942 PCI_CLK_OUT and determines the PCI initialization pattern
3943 driven during PCI_RST_N deassertion.
3944 PCI_OVR[3]: OVERRIDE (0:DISABLE/1:ENABLE)
3945 PCI_OVR[2]: BUS TYPE(0:PCI/1:PCIX)
3946 PCI_OVR[1:0]: BUS SPEED(0:33/1:66/2:100/3:133)
3947 OVERRIDE TYPE SPEED | Override Configuration
3948 [3] [2] [1:0] | TYPE SPEED
3949 ------------------+-------------------------------
3950 0 x xx | No override(uses 'sampled'
3951 | Bus Speed(HM_SPEED) and Bus Type(HM_PCIX)
3952 1 0 00 | PCI Mode 33MHz
3953 1 0 01 | PCI Mode 66MHz
3954 1 0 10 | RESERVED (DO NOT USE)
3955 1 0 11 | RESERVED (DO NOT USE)
3956 1 1 00 | RESERVED (DO NOT USE)
3957 1 1 01 | PCIX Mode 66MHz
3958 1 1 10 | PCIX Mode 100MHz
3959 1 1 11 | PCIX Mode 133MHz
3960 NOTES:
3961 - NPI_PCI_INT_ARB_CFG[PCI_OVR] has NO EFFECT on
3962 PCI_CNT_REG[HM_SPEED,HM_PCIX] (ie: the sampled PCI Bus
3963 Type/Speed), but WILL EFFECT PCI_CTL_STATUS_2[AP_PCIX]
3964 which reflects the actual PCI Bus Type(0:PCI/1:PCIX).
3965 - Software should never 'up' configure the recommended values.
3966 In other words, if the 'sampled' Bus Type=PCI(HM_PCIX=0),
3967 then SW should NOT attempt to set TYPE[2]=1 for PCIX Mode.
3968 Likewise, if the sampled Bus Speed=66MHz(HM_SPEED=01),
3969 then SW should NOT attempt to 'speed up' the bus [ie:
3970 SPEED[1:0]=10(100MHz)].
3971 - If PCI_OVR<3> is set prior to PCI reset de-assertion
3972 in host mode, NPI_PCI_INT_ARB_CFG[PCI_OVR]
3973 indicates the Bus Type/Speed that OCTEON drove on the
3974 DEVSEL/STOP/TRDY pins during reset de-assertion. (user
3975 should then ignore the 'sampled' Bus Type/Speed
3976 contained in the PCI_CNT_REG[HM_PCIX, HM_SPEED]) fields.
3977 - If PCI_OVR<3> is clear prior to PCI reset de-assertion
3978 in host mode, PCI_CNT_REG[HM_PCIX,HM_SPEED])
3979 indicates the Bus Type/Speed that OCTEON drove on the
3980 DEVSEL/STOP/TRDY pins during reset de-assertion. */
3981 uint64_t reserved_5_7 : 3;
3982 uint64_t en : 1; /**< Internal arbiter enable. */
3983 uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */
3984 uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */
3985 #else
3986 uint64_t park_dev : 3;
3987 uint64_t park_mod : 1;
3988 uint64_t en : 1;
3989 uint64_t reserved_5_7 : 3;
3990 uint64_t pci_ovr : 4;
3991 uint64_t hostmode : 1;
3992 uint64_t reserved_13_63 : 51;
3993 #endif
3994 } s;
3995 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
3996 #ifdef __BIG_ENDIAN_BITFIELD
3997 uint64_t reserved_5_63 : 59;
3998 uint64_t en : 1; /**< Internal arbiter enable. */
3999 uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */
4000 uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */
4001 #else
4002 uint64_t park_dev : 3;
4003 uint64_t park_mod : 1;
4004 uint64_t en : 1;
4005 uint64_t reserved_5_63 : 59;
4006 #endif
4007 } cn30xx;
4008 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
4009 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
4010 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
4011 struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
4012 struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
4013 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
4014 };
4015 typedef union cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_int_arb_cfg_t;
4016
4017 /**
4018 * cvmx_npi_pci_read_cmd
4019 *
4020 * NPI_PCI_READ_CMD = NPI PCI Read Command Register
4021 *
4022 * Controls the type of read command sent.
4023 * Writes to this register are not ordered with writes/reads to the PCI Memory space.
4024 * To ensure that a write has completed the user must read the register before
4025 * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
4026 * Also any previously issued reads/writes to PCI memory space, still stored in the outbound
4027 * FIFO will use the value of this register after it has been updated.
4028 */
4029 union cvmx_npi_pci_read_cmd {
4030 uint64_t u64;
4031 struct cvmx_npi_pci_read_cmd_s {
4032 #ifdef __BIG_ENDIAN_BITFIELD
4033 uint64_t reserved_11_63 : 53;
4034 uint64_t cmd_size : 11; /**< Number bytes to be read is equal to or exceeds this
4035 size will cause the PCI in PCI mode to use a
4036 Memory-Read-Multiple. This register has a value
4037 from 8 to 2048. A value of 0-7 will be treated as
4038 a value of 2048. */
4039 #else
4040 uint64_t cmd_size : 11;
4041 uint64_t reserved_11_63 : 53;
4042 #endif
4043 } s;
4044 struct cvmx_npi_pci_read_cmd_s cn30xx;
4045 struct cvmx_npi_pci_read_cmd_s cn31xx;
4046 struct cvmx_npi_pci_read_cmd_s cn38xx;
4047 struct cvmx_npi_pci_read_cmd_s cn38xxp2;
4048 struct cvmx_npi_pci_read_cmd_s cn50xx;
4049 struct cvmx_npi_pci_read_cmd_s cn58xx;
4050 struct cvmx_npi_pci_read_cmd_s cn58xxp1;
4051 };
4052 typedef union cvmx_npi_pci_read_cmd cvmx_npi_pci_read_cmd_t;
4053
4054 /**
4055 * cvmx_npi_port32_instr_hdr
4056 *
4057 * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header
4058 *
4059 * Contains bits [62:42] of the Instruction Header for port 32.
4060 */
4061 union cvmx_npi_port32_instr_hdr {
4062 uint64_t u64;
4063 struct cvmx_npi_port32_instr_hdr_s {
4064 #ifdef __BIG_ENDIAN_BITFIELD
4065 uint64_t reserved_44_63 : 20;
4066 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4067 uint64_t rsv_f : 5; /**< Reserved */
4068 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4069 uint64_t rsv_e : 1; /**< Reserved */
4070 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4071 uint64_t rsv_d : 6; /**< Reserved */
4072 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4073 as part of the packet data, regardless of the
4074 value of bit [63] of the instruction header.
4075 USE_IHDR must be set whenever PBP is set. */
4076 uint64_t rsv_c : 5; /**< Reserved */
4077 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4078 is not raw and PBP is not set. */
4079 uint64_t rsv_b : 1; /**< Reserved
4080 instruction header sent to IPD. */
4081 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4082 is not raw and PBP is not set. */
4083 uint64_t rsv_a : 6; /**< Reserved */
4084 #else
4085 uint64_t rsv_a : 6;
4086 uint64_t skp_len : 7;
4087 uint64_t rsv_b : 1;
4088 uint64_t par_mode : 2;
4089 uint64_t rsv_c : 5;
4090 uint64_t use_ihdr : 1;
4091 uint64_t rsv_d : 6;
4092 uint64_t rskp_len : 7;
4093 uint64_t rsv_e : 1;
4094 uint64_t rparmode : 2;
4095 uint64_t rsv_f : 5;
4096 uint64_t pbp : 1;
4097 uint64_t reserved_44_63 : 20;
4098 #endif
4099 } s;
4100 struct cvmx_npi_port32_instr_hdr_s cn30xx;
4101 struct cvmx_npi_port32_instr_hdr_s cn31xx;
4102 struct cvmx_npi_port32_instr_hdr_s cn38xx;
4103 struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
4104 struct cvmx_npi_port32_instr_hdr_s cn50xx;
4105 struct cvmx_npi_port32_instr_hdr_s cn58xx;
4106 struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
4107 };
4108 typedef union cvmx_npi_port32_instr_hdr cvmx_npi_port32_instr_hdr_t;
4109
4110 /**
4111 * cvmx_npi_port33_instr_hdr
4112 *
4113 * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header
4114 *
4115 * Contains bits [62:42] of the Instruction Header for port 33.
4116 */
4117 union cvmx_npi_port33_instr_hdr {
4118 uint64_t u64;
4119 struct cvmx_npi_port33_instr_hdr_s {
4120 #ifdef __BIG_ENDIAN_BITFIELD
4121 uint64_t reserved_44_63 : 20;
4122 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4123 uint64_t rsv_f : 5; /**< Reserved */
4124 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4125 uint64_t rsv_e : 1; /**< Reserved */
4126 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4127 uint64_t rsv_d : 6; /**< Reserved */
4128 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4129 as part of the packet data, regardless of the
4130 value of bit [63] of the instruction header.
4131 USE_IHDR must be set whenever PBP is set. */
4132 uint64_t rsv_c : 5; /**< Reserved */
4133 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4134 is not raw and PBP is not set. */
4135 uint64_t rsv_b : 1; /**< Reserved
4136 instruction header sent to IPD. */
4137 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4138 is not raw and PBP is not set. */
4139 uint64_t rsv_a : 6; /**< Reserved */
4140 #else
4141 uint64_t rsv_a : 6;
4142 uint64_t skp_len : 7;
4143 uint64_t rsv_b : 1;
4144 uint64_t par_mode : 2;
4145 uint64_t rsv_c : 5;
4146 uint64_t use_ihdr : 1;
4147 uint64_t rsv_d : 6;
4148 uint64_t rskp_len : 7;
4149 uint64_t rsv_e : 1;
4150 uint64_t rparmode : 2;
4151 uint64_t rsv_f : 5;
4152 uint64_t pbp : 1;
4153 uint64_t reserved_44_63 : 20;
4154 #endif
4155 } s;
4156 struct cvmx_npi_port33_instr_hdr_s cn31xx;
4157 struct cvmx_npi_port33_instr_hdr_s cn38xx;
4158 struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
4159 struct cvmx_npi_port33_instr_hdr_s cn50xx;
4160 struct cvmx_npi_port33_instr_hdr_s cn58xx;
4161 struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
4162 };
4163 typedef union cvmx_npi_port33_instr_hdr cvmx_npi_port33_instr_hdr_t;
4164
4165 /**
4166 * cvmx_npi_port34_instr_hdr
4167 *
4168 * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header
4169 *
4170 * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2.
4171 */
4172 union cvmx_npi_port34_instr_hdr {
4173 uint64_t u64;
4174 struct cvmx_npi_port34_instr_hdr_s {
4175 #ifdef __BIG_ENDIAN_BITFIELD
4176 uint64_t reserved_44_63 : 20;
4177 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4178 uint64_t rsv_f : 5; /**< Reserved */
4179 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4180 uint64_t rsv_e : 1; /**< Reserved */
4181 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4182 uint64_t rsv_d : 6; /**< Reserved */
4183 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4184 as part of the packet data, regardless of the
4185 value of bit [63] of the instruction header.
4186 USE_IHDR must be set whenever PBP is set. */
4187 uint64_t rsv_c : 5; /**< Reserved */
4188 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4189 is not raw and PBP is not set. */
4190 uint64_t rsv_b : 1; /**< Reserved
4191 instruction header sent to IPD. */
4192 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4193 is not raw and PBP is not set. */
4194 uint64_t rsv_a : 6; /**< Reserved */
4195 #else
4196 uint64_t rsv_a : 6;
4197 uint64_t skp_len : 7;
4198 uint64_t rsv_b : 1;
4199 uint64_t par_mode : 2;
4200 uint64_t rsv_c : 5;
4201 uint64_t use_ihdr : 1;
4202 uint64_t rsv_d : 6;
4203 uint64_t rskp_len : 7;
4204 uint64_t rsv_e : 1;
4205 uint64_t rparmode : 2;
4206 uint64_t rsv_f : 5;
4207 uint64_t pbp : 1;
4208 uint64_t reserved_44_63 : 20;
4209 #endif
4210 } s;
4211 struct cvmx_npi_port34_instr_hdr_s cn38xx;
4212 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
4213 struct cvmx_npi_port34_instr_hdr_s cn58xx;
4214 struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
4215 };
4216 typedef union cvmx_npi_port34_instr_hdr cvmx_npi_port34_instr_hdr_t;
4217
4218 /**
4219 * cvmx_npi_port35_instr_hdr
4220 *
4221 * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header
4222 *
4223 * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2.
4224 */
4225 union cvmx_npi_port35_instr_hdr {
4226 uint64_t u64;
4227 struct cvmx_npi_port35_instr_hdr_s {
4228 #ifdef __BIG_ENDIAN_BITFIELD
4229 uint64_t reserved_44_63 : 20;
4230 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
4231 uint64_t rsv_f : 5; /**< Reserved */
4232 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
4233 uint64_t rsv_e : 1; /**< Reserved */
4234 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
4235 uint64_t rsv_d : 6; /**< Reserved */
4236 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
4237 as part of the packet data, regardless of the
4238 value of bit [63] of the instruction header.
4239 USE_IHDR must be set whenever PBP is set. */
4240 uint64_t rsv_c : 5; /**< Reserved */
4241 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
4242 is not raw and PBP is not set. */
4243 uint64_t rsv_b : 1; /**< Reserved
4244 instruction header sent to IPD. */
4245 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
4246 is not raw and PBP is not set. */
4247 uint64_t rsv_a : 6; /**< Reserved */
4248 #else
4249 uint64_t rsv_a : 6;
4250 uint64_t skp_len : 7;
4251 uint64_t rsv_b : 1;
4252 uint64_t par_mode : 2;
4253 uint64_t rsv_c : 5;
4254 uint64_t use_ihdr : 1;
4255 uint64_t rsv_d : 6;
4256 uint64_t rskp_len : 7;
4257 uint64_t rsv_e : 1;
4258 uint64_t rparmode : 2;
4259 uint64_t rsv_f : 5;
4260 uint64_t pbp : 1;
4261 uint64_t reserved_44_63 : 20;
4262 #endif
4263 } s;
4264 struct cvmx_npi_port35_instr_hdr_s cn38xx;
4265 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
4266 struct cvmx_npi_port35_instr_hdr_s cn58xx;
4267 struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
4268 };
4269 typedef union cvmx_npi_port35_instr_hdr cvmx_npi_port35_instr_hdr_t;
4270
4271 /**
4272 * cvmx_npi_port_bp_control
4273 *
4274 * NPI_PORT_BP_CONTROL = Port Backpressure Control
4275 *
4276 * Enables Port Level Backpressure
4277 */
4278 union cvmx_npi_port_bp_control {
4279 uint64_t u64;
4280 struct cvmx_npi_port_bp_control_s {
4281 #ifdef __BIG_ENDIAN_BITFIELD
4282 uint64_t reserved_8_63 : 56;
4283 uint64_t bp_on : 4; /**< Port 35-32 port level backpressure applied. */
4284 uint64_t enb : 4; /**< Enables port level backpressure from the IPD. */
4285 #else
4286 uint64_t enb : 4;
4287 uint64_t bp_on : 4;
4288 uint64_t reserved_8_63 : 56;
4289 #endif
4290 } s;
4291 struct cvmx_npi_port_bp_control_s cn30xx;
4292 struct cvmx_npi_port_bp_control_s cn31xx;
4293 struct cvmx_npi_port_bp_control_s cn38xx;
4294 struct cvmx_npi_port_bp_control_s cn38xxp2;
4295 struct cvmx_npi_port_bp_control_s cn50xx;
4296 struct cvmx_npi_port_bp_control_s cn58xx;
4297 struct cvmx_npi_port_bp_control_s cn58xxp1;
4298 };
4299 typedef union cvmx_npi_port_bp_control cvmx_npi_port_bp_control_t;
4300
4301 /**
4302 * cvmx_npi_rsl_int_blocks
4303 *
4304 * RSL_INT_BLOCKS = RSL Interrupt Blocks Register
4305 *
4306 * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
4307 * that presently has an interrupt pending. The Field Description below supplies the name of the
4308 * register that software should read to find out why that intterupt bit is set.
4309 */
4310 union cvmx_npi_rsl_int_blocks {
4311 uint64_t u64;
4312 struct cvmx_npi_rsl_int_blocks_s {
4313 #ifdef __BIG_ENDIAN_BITFIELD
4314 uint64_t reserved_32_63 : 32;
4315 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4316 uint64_t iob : 1; /**< IOB_INT_SUM */
4317 uint64_t reserved_28_29 : 2;
4318 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4319 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4320 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4321 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4322 uint64_t asx1 : 1; /**< ASX1_INT_REG */
4323 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4324 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4325 uint64_t pip : 1; /**< PIP_INT_REG. */
4326 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */
4327 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */
4328 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4329 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4330 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4331 uint64_t reserved_13_14 : 2;
4332 uint64_t pow : 1; /**< POW_ECC_ERR */
4333 uint64_t tim : 1; /**< TIM_REG_ERROR */
4334 uint64_t pko : 1; /**< PKO_REG_ERROR */
4335 uint64_t ipd : 1; /**< IPD_INT_SUM */
4336 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4337 uint64_t zip : 1; /**< ZIP_ERROR */
4338 uint64_t dfa : 1; /**< DFA_ERR */
4339 uint64_t fpa : 1; /**< FPA_INT_SUM */
4340 uint64_t key : 1; /**< KEY_INT_SUM */
4341 uint64_t npi : 1; /**< NPI_INT_SUM */
4342 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
4343 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4344 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4345 #else
4346 uint64_t mio : 1;
4347 uint64_t gmx0 : 1;
4348 uint64_t gmx1 : 1;
4349 uint64_t npi : 1;
4350 uint64_t key : 1;
4351 uint64_t fpa : 1;
4352 uint64_t dfa : 1;
4353 uint64_t zip : 1;
4354 uint64_t rint_8 : 1;
4355 uint64_t ipd : 1;
4356 uint64_t pko : 1;
4357 uint64_t tim : 1;
4358 uint64_t pow : 1;
4359 uint64_t reserved_13_14 : 2;
4360 uint64_t rint_15 : 1;
4361 uint64_t l2c : 1;
4362 uint64_t lmc : 1;
4363 uint64_t spx0 : 1;
4364 uint64_t spx1 : 1;
4365 uint64_t pip : 1;
4366 uint64_t rint_21 : 1;
4367 uint64_t asx0 : 1;
4368 uint64_t asx1 : 1;
4369 uint64_t rint_24 : 1;
4370 uint64_t rint_25 : 1;
4371 uint64_t rint_26 : 1;
4372 uint64_t rint_27 : 1;
4373 uint64_t reserved_28_29 : 2;
4374 uint64_t iob : 1;
4375 uint64_t rint_31 : 1;
4376 uint64_t reserved_32_63 : 32;
4377 #endif
4378 } s;
4379 struct cvmx_npi_rsl_int_blocks_cn30xx {
4380 #ifdef __BIG_ENDIAN_BITFIELD
4381 uint64_t reserved_32_63 : 32;
4382 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4383 uint64_t iob : 1; /**< IOB_INT_SUM */
4384 uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4385 uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4386 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4387 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4388 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4389 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4390 uint64_t asx1 : 1; /**< ASX1_INT_REG */
4391 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4392 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4393 uint64_t pip : 1; /**< PIP_INT_REG. */
4394 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */
4395 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */
4396 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4397 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4398 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4399 uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4400 uint64_t usb : 1; /**< USBN_INT_SUM */
4401 uint64_t pow : 1; /**< POW_ECC_ERR */
4402 uint64_t tim : 1; /**< TIM_REG_ERROR */
4403 uint64_t pko : 1; /**< PKO_REG_ERROR */
4404 uint64_t ipd : 1; /**< IPD_INT_SUM */
4405 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4406 uint64_t zip : 1; /**< ZIP_ERROR */
4407 uint64_t dfa : 1; /**< DFA_ERR */
4408 uint64_t fpa : 1; /**< FPA_INT_SUM */
4409 uint64_t key : 1; /**< Set '1' when RSL bLock has an interrupt. */
4410 uint64_t npi : 1; /**< NPI_INT_SUM */
4411 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
4412 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4413 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4414 #else
4415 uint64_t mio : 1;
4416 uint64_t gmx0 : 1;
4417 uint64_t gmx1 : 1;
4418 uint64_t npi : 1;
4419 uint64_t key : 1;
4420 uint64_t fpa : 1;
4421 uint64_t dfa : 1;
4422 uint64_t zip : 1;
4423 uint64_t rint_8 : 1;
4424 uint64_t ipd : 1;
4425 uint64_t pko : 1;
4426 uint64_t tim : 1;
4427 uint64_t pow : 1;
4428 uint64_t usb : 1;
4429 uint64_t rint_14 : 1;
4430 uint64_t rint_15 : 1;
4431 uint64_t l2c : 1;
4432 uint64_t lmc : 1;
4433 uint64_t spx0 : 1;
4434 uint64_t spx1 : 1;
4435 uint64_t pip : 1;
4436 uint64_t rint_21 : 1;
4437 uint64_t asx0 : 1;
4438 uint64_t asx1 : 1;
4439 uint64_t rint_24 : 1;
4440 uint64_t rint_25 : 1;
4441 uint64_t rint_26 : 1;
4442 uint64_t rint_27 : 1;
4443 uint64_t rint_28 : 1;
4444 uint64_t rint_29 : 1;
4445 uint64_t iob : 1;
4446 uint64_t rint_31 : 1;
4447 uint64_t reserved_32_63 : 32;
4448 #endif
4449 } cn30xx;
4450 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
4451 struct cvmx_npi_rsl_int_blocks_cn38xx {
4452 #ifdef __BIG_ENDIAN_BITFIELD
4453 uint64_t reserved_32_63 : 32;
4454 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4455 uint64_t iob : 1; /**< IOB_INT_SUM */
4456 uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4457 uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4458 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4459 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4460 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4461 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4462 uint64_t asx1 : 1; /**< ASX1_INT_REG */
4463 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4464 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4465 uint64_t pip : 1; /**< PIP_INT_REG. */
4466 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */
4467 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */
4468 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4469 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4470 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4471 uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4472 uint64_t rint_13 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4473 uint64_t pow : 1; /**< POW_ECC_ERR */
4474 uint64_t tim : 1; /**< TIM_REG_ERROR */
4475 uint64_t pko : 1; /**< PKO_REG_ERROR */
4476 uint64_t ipd : 1; /**< IPD_INT_SUM */
4477 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */
4478 uint64_t zip : 1; /**< ZIP_ERROR */
4479 uint64_t dfa : 1; /**< DFA_ERR */
4480 uint64_t fpa : 1; /**< FPA_INT_SUM */
4481 uint64_t key : 1; /**< KEY_INT_SUM */
4482 uint64_t npi : 1; /**< NPI_INT_SUM */
4483 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
4484 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4485 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4486 #else
4487 uint64_t mio : 1;
4488 uint64_t gmx0 : 1;
4489 uint64_t gmx1 : 1;
4490 uint64_t npi : 1;
4491 uint64_t key : 1;
4492 uint64_t fpa : 1;
4493 uint64_t dfa : 1;
4494 uint64_t zip : 1;
4495 uint64_t rint_8 : 1;
4496 uint64_t ipd : 1;
4497 uint64_t pko : 1;
4498 uint64_t tim : 1;
4499 uint64_t pow : 1;
4500 uint64_t rint_13 : 1;
4501 uint64_t rint_14 : 1;
4502 uint64_t rint_15 : 1;
4503 uint64_t l2c : 1;
4504 uint64_t lmc : 1;
4505 uint64_t spx0 : 1;
4506 uint64_t spx1 : 1;
4507 uint64_t pip : 1;
4508 uint64_t rint_21 : 1;
4509 uint64_t asx0 : 1;
4510 uint64_t asx1 : 1;
4511 uint64_t rint_24 : 1;
4512 uint64_t rint_25 : 1;
4513 uint64_t rint_26 : 1;
4514 uint64_t rint_27 : 1;
4515 uint64_t rint_28 : 1;
4516 uint64_t rint_29 : 1;
4517 uint64_t iob : 1;
4518 uint64_t rint_31 : 1;
4519 uint64_t reserved_32_63 : 32;
4520 #endif
4521 } cn38xx;
4522 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
4523 struct cvmx_npi_rsl_int_blocks_cn50xx {
4524 #ifdef __BIG_ENDIAN_BITFIELD
4525 uint64_t reserved_31_63 : 33;
4526 uint64_t iob : 1; /**< IOB_INT_SUM */
4527 uint64_t lmc1 : 1; /**< Always reads as zero */
4528 uint64_t agl : 1; /**< Always reads as zero */
4529 uint64_t reserved_24_27 : 4;
4530 uint64_t asx1 : 1; /**< Always reads as zero */
4531 uint64_t asx0 : 1; /**< ASX0_INT_REG */
4532 uint64_t reserved_21_21 : 1;
4533 uint64_t pip : 1; /**< PIP_INT_REG. */
4534 uint64_t spx1 : 1; /**< Always reads as zero */
4535 uint64_t spx0 : 1; /**< Always reads as zero */
4536 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */
4537 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */
4538 uint64_t reserved_15_15 : 1;
4539 uint64_t rad : 1; /**< Always reads as zero */
4540 uint64_t usb : 1; /**< USBN_INT_SUM */
4541 uint64_t pow : 1; /**< POW_ECC_ERR */
4542 uint64_t tim : 1; /**< TIM_REG_ERROR */
4543 uint64_t pko : 1; /**< PKO_REG_ERROR */
4544 uint64_t ipd : 1; /**< IPD_INT_SUM */
4545 uint64_t reserved_8_8 : 1;
4546 uint64_t zip : 1; /**< Always reads as zero */
4547 uint64_t dfa : 1; /**< Always reads as zero */
4548 uint64_t fpa : 1; /**< FPA_INT_SUM */
4549 uint64_t key : 1; /**< Always reads as zero */
4550 uint64_t npi : 1; /**< NPI_INT_SUM */
4551 uint64_t gmx1 : 1; /**< Always reads as zero */
4552 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
4553 uint64_t mio : 1; /**< MIO_BOOT_ERR */
4554 #else
4555 uint64_t mio : 1;
4556 uint64_t gmx0 : 1;
4557 uint64_t gmx1 : 1;
4558 uint64_t npi : 1;
4559 uint64_t key : 1;
4560 uint64_t fpa : 1;
4561 uint64_t dfa : 1;
4562 uint64_t zip : 1;
4563 uint64_t reserved_8_8 : 1;
4564 uint64_t ipd : 1;
4565 uint64_t pko : 1;
4566 uint64_t tim : 1;
4567 uint64_t pow : 1;
4568 uint64_t usb : 1;
4569 uint64_t rad : 1;
4570 uint64_t reserved_15_15 : 1;
4571 uint64_t l2c : 1;
4572 uint64_t lmc : 1;
4573 uint64_t spx0 : 1;
4574 uint64_t spx1 : 1;
4575 uint64_t pip : 1;
4576 uint64_t reserved_21_21 : 1;
4577 uint64_t asx0 : 1;
4578 uint64_t asx1 : 1;
4579 uint64_t reserved_24_27 : 4;
4580 uint64_t agl : 1;
4581 uint64_t lmc1 : 1;
4582 uint64_t iob : 1;
4583 uint64_t reserved_31_63 : 33;
4584 #endif
4585 } cn50xx;
4586 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
4587 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
4588 };
4589 typedef union cvmx_npi_rsl_int_blocks cvmx_npi_rsl_int_blocks_t;
4590
4591 /**
4592 * cvmx_npi_size_input#
4593 *
4594 * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register
4595 *
4596 * The size (in instructions) of Instruction Queue-0.
4597 */
4598 union cvmx_npi_size_inputx {
4599 uint64_t u64;
4600 struct cvmx_npi_size_inputx_s {
4601 #ifdef __BIG_ENDIAN_BITFIELD
4602 uint64_t reserved_32_63 : 32;
4603 uint64_t size : 32; /**< The size of the Instruction Queue used by Octane.
4604 The value [SIZE] is in Instructions.
4605 A value of 0 in this field is illegal. */
4606 #else
4607 uint64_t size : 32;
4608 uint64_t reserved_32_63 : 32;
4609 #endif
4610 } s;
4611 struct cvmx_npi_size_inputx_s cn30xx;
4612 struct cvmx_npi_size_inputx_s cn31xx;
4613 struct cvmx_npi_size_inputx_s cn38xx;
4614 struct cvmx_npi_size_inputx_s cn38xxp2;
4615 struct cvmx_npi_size_inputx_s cn50xx;
4616 struct cvmx_npi_size_inputx_s cn58xx;
4617 struct cvmx_npi_size_inputx_s cn58xxp1;
4618 };
4619 typedef union cvmx_npi_size_inputx cvmx_npi_size_inputx_t;
4620
4621 /**
4622 * cvmx_npi_win_read_to
4623 *
4624 * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register
4625 *
4626 * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB.
4627 */
4628 union cvmx_npi_win_read_to {
4629 uint64_t u64;
4630 struct cvmx_npi_win_read_to_s {
4631 #ifdef __BIG_ENDIAN_BITFIELD
4632 uint64_t reserved_32_63 : 32;
4633 uint64_t time : 32; /**< Time to wait in core clocks. A value of 0 will
4634 cause no timeouts. */
4635 #else
4636 uint64_t time : 32;
4637 uint64_t reserved_32_63 : 32;
4638 #endif
4639 } s;
4640 struct cvmx_npi_win_read_to_s cn30xx;
4641 struct cvmx_npi_win_read_to_s cn31xx;
4642 struct cvmx_npi_win_read_to_s cn38xx;
4643 struct cvmx_npi_win_read_to_s cn38xxp2;
4644 struct cvmx_npi_win_read_to_s cn50xx;
4645 struct cvmx_npi_win_read_to_s cn58xx;
4646 struct cvmx_npi_win_read_to_s cn58xxp1;
4647 };
4648 typedef union cvmx_npi_win_read_to cvmx_npi_win_read_to_t;
4649
4650 #endif
4651