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Searched refs:CSR_WRITE_4 (Results 1 – 7 of 7) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_timer.c95 CSR_WRITE_4(sc, JZ_TC_TFCR, TFR_FFLAG5); in jz4780_hardclock()
96 CSR_WRITE_4(sc, JZ_TC_TECR, TESR_TCST5); in jz4780_hardclock()
115 CSR_WRITE_4(sc, JZ_TC_TDFR(5), ticks); in jz4780_timer_start()
116 CSR_WRITE_4(sc, JZ_TC_TCNT(5), 0); in jz4780_timer_start()
117 CSR_WRITE_4(sc, JZ_TC_TESR, TESR_TCST5); in jz4780_timer_start()
128 CSR_WRITE_4(sc, JZ_TC_TECR, TESR_TCST5); in jz4780_timer_stop()
185 CSR_WRITE_4(sc, JZ_TC_TECR, TESR_OST); in jz4780_timer_attach()
195 CSR_WRITE_4(sc, JZ_OST_CTRL, 0); in jz4780_timer_attach()
196 CSR_WRITE_4(sc, JZ_OST_CNT_LO, 0); in jz4780_timer_attach()
197 CSR_WRITE_4(sc, JZ_OST_CNT_HI, 0); in jz4780_timer_attach()
[all …]
H A Djz4780_gpio.c144 CSR_WRITE_4(sc, JZ_GPIO_INTC, mask); in jz4780_gpio_pin_set_func()
145 CSR_WRITE_4(sc, JZ_GPIO_MASKC, mask); in jz4780_gpio_pin_set_func()
147 CSR_WRITE_4(sc, JZ_GPIO_PAT1S, mask); in jz4780_gpio_pin_set_func()
149 CSR_WRITE_4(sc, JZ_GPIO_PAT1C, mask); in jz4780_gpio_pin_set_func()
151 CSR_WRITE_4(sc, JZ_GPIO_PAT0S, mask); in jz4780_gpio_pin_set_func()
153 CSR_WRITE_4(sc, JZ_GPIO_PAT0C, mask); in jz4780_gpio_pin_set_func()
169 CSR_WRITE_4(sc, JZ_GPIO_PAT1C, mask); in jz4780_gpio_pin_set_direction()
175 CSR_WRITE_4(sc, JZ_GPIO_PAT1S, mask); in jz4780_gpio_pin_set_direction()
201 CSR_WRITE_4(sc, JZ_GPIO_DPULLS, mask); in jz4780_gpio_pin_set_bias()
694 CSR_WRITE_4(sc, JZ_GPIO_MASKS, mask); in jz4780_gpio_pic_setup_intr()
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H A Djz4780_clock.c568 CSR_WRITE_4(sc, addr, val); in jz4780_clock_write_4()
593 CSR_WRITE_4(sc, addr, val); in jz4780_clock_modify_4()
688 CSR_WRITE_4(sc, JZ_OPCR, reg); in jz4780_ohci_enable()
719 CSR_WRITE_4(sc, JZ_USBPCR, reg); in jz4780_ehci_enable()
724 CSR_WRITE_4(sc, JZ_OPCR, reg); in jz4780_ehci_enable()
744 CSR_WRITE_4(sc, JZ_USBPCR, reg); in jz4780_ehci_enable()
748 CSR_WRITE_4(sc, JZ_USBPCR, reg); in jz4780_ehci_enable()
753 CSR_WRITE_4(sc, JZ_SRBC, reg); in jz4780_ehci_enable()
759 CSR_WRITE_4(sc, JZ_SRBC, reg); in jz4780_ehci_enable()
803 CSR_WRITE_4(sc, JZ_USBRDT, reg); in jz4780_otg_enable()
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H A Djz4780_efuse.c73 #define CSR_WRITE_4(sc, reg, val) \ macro
99 CSR_WRITE_4(sc, JZ_EFUCTRL, JZ_EFUSE_READ | in jz4780_efuse_read_chunk()
173 CSR_WRITE_4(sc, JZ_EFUCFG, 0x00040000); in jz4780_efuse_attach()
H A Djz4780_nemc.c76 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro
187 CSR_WRITE_4(sc, JZ_NEMC_SMCR(bank), smcr); in jz4780_nemc_configure_bank()
/f-stack/freebsd/mips/atheros/ar531x/
H A Dif_are.c460 CSR_WRITE_4(sc, CSR_MIIADDR, addr); in are_miibus_readreg()
477 CSR_WRITE_4(sc, CSR_MIIDATA, data); in are_miibus_writereg()
482 CSR_WRITE_4(sc, CSR_MIIADDR, addr); in are_miibus_writereg()
543 CSR_WRITE_4(sc, CSR_BUSMODE, 0); in are_reset()
602 CSR_WRITE_4(sc, CSR_BUSMODE, in are_init_locked()
913 CSR_WRITE_4(sc, CSR_INTEN, 0); in are_stop()
916 CSR_WRITE_4(sc, CSR_OPMODE, 0); in are_stop()
917 CSR_WRITE_4(sc, CSR_RXLIST, 0); in are_stop()
918 CSR_WRITE_4(sc, CSR_TXLIST, 0); in are_stop()
919 CSR_WRITE_4(sc, CSR_MACCTL, in are_stop()
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H A Dif_arereg.h138 #define CSR_WRITE_4(sc, reg, val) \ macro