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Searched refs:CSR_INTEN (Results 1 – 2 of 2) sorted by relevance

/f-stack/freebsd/mips/atheros/ar531x/
H A Dif_arereg.h265 #define CSR_INTEN 0x101C /* interrupt enable */ macro
H A Dif_are.c622 CSR_WRITE_4(sc, CSR_INTEN, sc->sc_inten); in are_init_locked()
913 CSR_WRITE_4(sc, CSR_INTEN, 0); in are_stop()