Searched refs:CLK_TOP_UNIVPLL1_D8 (Results 1 – 9 of 9) sorted by relevance
20 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
32 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
46 #define CLK_TOP_UNIVPLL1_D8 35 macro
52 #define CLK_TOP_UNIVPLL1_D8 42 macro
46 #define CLK_TOP_UNIVPLL1_D8 34 macro
70 #define CLK_TOP_UNIVPLL1_D8 60 macro
75 #define CLK_TOP_UNIVPLL1_D8 65 macro
59 #define CLK_TOP_UNIVPLL1_D8 28 macro
38 #define CLK_TOP_UNIVPLL1_D8 28 macro