Home
last modified time | relevance | path

Searched refs:CLK_RD_4 (Results 1 – 4 of 4) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_clk_pll.c107 reg = CLK_RD_4(sc, sc->clk_reg); in jz4780_clk_pll_init()
122 reg = CLK_RD_4(sc, sc->clk_reg); in jz4780_clk_pll_recalc_freq()
157 if (CLK_RD_4(sc, sc->clk_reg) & REG_VAL(CGU_PLL_LOCK, 1)) in jz4780_clk_pll_wait_lock()
193 reg = CLK_RD_4(sc, sc->clk_reg); in jz4780_clk_pll_set_freq()
H A Djz4780_clk_gen.c116 reg = CLK_RD_4(sc, sc->clk_descr->clk_mux.mux_reg); in jz4780_clk_gen_init()
140 reg = CLK_RD_4(sc, sc->clk_descr->clk_div.div_reg); in jz4780_clk_gen_recalc_freq()
204 reg = CLK_RD_4(sc, sc->clk_descr->clk_div.div_reg); in jz4780_clk_gen_set_freq()
222 reg = CLK_RD_4(sc, sc->clk_descr->clk_div.div_reg); in jz4780_clk_gen_set_freq()
252 reg = CLK_RD_4(sc, sc->clk_descr->clk_mux.mux_reg); in jz4780_clk_gen_set_mux()
282 reg = CLK_RD_4(sc, off); in jz4780_clk_gen_set_gate()
H A Djz4780_clk_otg.c81 reg = CLK_RD_4(sc, JZ_USBPCR1); in jz4780_clk_otg_init()
109 reg = CLK_RD_4(sc, JZ_USBPCR1); in jz4780_clk_otg_recalc_freq()
140 reg = CLK_RD_4(sc, JZ_USBPCR1); in jz4780_clk_otg_set_freq()
H A Djz4780_clk.h47 #define CLK_RD_4(_sc, off) bus_read_4((_sc)->clk_res, (off)) macro