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Searched refs:CHELSIO_CHIP_VERSION (Results 1 – 8 of 8) sorted by relevance

/f-stack/dpdk/drivers/net/cxgbe/base/
H A Dt4_chip_type.h27 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) macro
48 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); in is_t4()
53 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5()
58 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); in is_t6()
H A Dt4_hw.c554 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in t4_get_regs_len()
1918 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
2206 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && in t4_write_rss_key()
3054 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_enable()
3057 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in t4_intr_enable()
3081 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_disable()
3135 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_mps_bg_map()
3257 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
3294 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
3681 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_fl_pkt_align()
[all …]
H A Dt4vf_hw.c96 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in t4vf_wr_mbox_core()
482 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in t4vf_fl_pkt_align()
508 return (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4vf_get_pf_from_vf()
/f-stack/dpdk/drivers/net/cxgbe/
H A Dcxgbe_filter.c26 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { in cxgbe_init_hash_filter()
243 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6) in cxgbe_filter_slots()
500 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { in mk_act_open_req6()
552 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { in mk_act_open_req()
944 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); in cxgbe_del_filter()
1017 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); in cxgbe_set_filter()
H A Dsmt.c43 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) { in write_smt_entry()
H A Dsge.c772 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) in hwcsum()
1250 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_eth_xmit()
1845 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_sge_alloc_rxq()
2625 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { in t4vf_sge_init()
H A Dcxgbe_ethdev.c1149 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | in cxgbe_get_regs()
H A Dcxgbe_main.c2037 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? in cxgbe_probe()