1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2020 Broadcom 3 * All rights reserved. 4 */ 5 /* 6 * Name: cfa_p40_hw.h 7 * 8 * Description: header for SWE based on Truflow 9 * 10 * Date: taken from 12/16/19 17:18:12 11 * 12 * Note: This file was first generated using tflib_decode.py. 13 * 14 * Changes have been made due to lack of availability of xml for 15 * additional tables at this time (EEM Record and union table fields) 16 * Changes not autogenerated are noted in comments. 17 */ 18 19 #ifndef _CFA_P40_HW_H_ 20 #define _CFA_P40_HW_H_ 21 22 /** 23 * Valid TCAM entry. (for idx 5 ...) 24 */ 25 #define CFA_P40_PROF_L2_CTXT_TCAM_VALID_BITPOS 166 26 #define CFA_P40_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1 27 /** 28 * Key type (pass). (for idx 5 ...) 29 */ 30 #define CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_BITPOS 164 31 #define CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_NUM_BITS 2 32 /** 33 * Tunnel HDR type. (for idx 5 ...) 34 */ 35 #define CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_BITPOS 160 36 #define CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_NUM_BITS 4 37 /** 38 * Number of VLAN tags in tunnel l2 header. (for idx 4 ...) 39 */ 40 #define CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_BITPOS 158 41 #define CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_NUM_BITS 2 42 /** 43 * Number of VLAN tags in l2 header. (for idx 4 ...) 44 */ 45 #define CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_BITPOS 156 46 #define CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_NUM_BITS 2 47 /** 48 * Tunnel/Inner Source/Dest. MAC Address. 49 */ 50 #define CFA_P40_PROF_L2_CTXT_TCAM_MAC1_BITPOS 108 51 #define CFA_P40_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS 48 52 /** 53 * Tunnel Outer VLAN Tag ID. (for idx 3 ...) 54 */ 55 #define CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_BITPOS 96 56 #define CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_NUM_BITS 12 57 /** 58 * Tunnel Inner VLAN Tag ID. (for idx 2 ...) 59 */ 60 #define CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_BITPOS 84 61 #define CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_NUM_BITS 12 62 /** 63 * Source Partition. (for idx 2 ...) 64 */ 65 #define CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_BITPOS 80 66 #define CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS 4 67 /** 68 * Source Virtual I/F. (for idx 2 ...) 69 */ 70 #define CFA_P40_PROF_L2_CTXT_TCAM_SVIF_BITPOS 72 71 #define CFA_P40_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS 8 72 /** 73 * Tunnel/Inner Source/Dest. MAC Address. 74 */ 75 #define CFA_P40_PROF_L2_CTXT_TCAM_MAC0_BITPOS 24 76 #define CFA_P40_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS 48 77 /** 78 * Outer VLAN Tag ID. 79 */ 80 #define CFA_P40_PROF_L2_CTXT_TCAM_OVID_BITPOS 12 81 #define CFA_P40_PROF_L2_CTXT_TCAM_OVID_NUM_BITS 12 82 /** 83 * Inner VLAN Tag ID. 84 */ 85 #define CFA_P40_PROF_L2_CTXT_TCAM_IVID_BITPOS 0 86 #define CFA_P40_PROF_L2_CTXT_TCAM_IVID_NUM_BITS 12 87 88 enum cfa_p40_prof_l2_ctxt_tcam_flds { 89 CFA_P40_PROF_L2_CTXT_TCAM_VALID_FLD = 0, 90 CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_FLD = 1, 91 CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_FLD = 2, 92 CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_FLD = 3, 93 CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_FLD = 4, 94 CFA_P40_PROF_L2_CTXT_TCAM_MAC1_FLD = 5, 95 CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_FLD = 6, 96 CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_FLD = 7, 97 CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_FLD = 8, 98 CFA_P40_PROF_L2_CTXT_TCAM_SVIF_FLD = 9, 99 CFA_P40_PROF_L2_CTXT_TCAM_MAC0_FLD = 10, 100 CFA_P40_PROF_L2_CTXT_TCAM_OVID_FLD = 11, 101 CFA_P40_PROF_L2_CTXT_TCAM_IVID_FLD = 12, 102 CFA_P40_PROF_L2_CTXT_TCAM_MAX_FLD 103 }; 104 105 #define CFA_P40_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 167 106 107 /** 108 * Valid entry. (for idx 2 ...) 109 */ 110 #define CFA_P40_ACT_VEB_TCAM_VALID_BITPOS 79 111 #define CFA_P40_ACT_VEB_TCAM_VALID_NUM_BITS 1 112 /** 113 * reserved program to 0. (for idx 2 ...) 114 */ 115 #define CFA_P40_ACT_VEB_TCAM_RESERVED_BITPOS 78 116 #define CFA_P40_ACT_VEB_TCAM_RESERVED_NUM_BITS 1 117 /** 118 * PF Parif Number. (for idx 2 ...) 119 */ 120 #define CFA_P40_ACT_VEB_TCAM_PARIF_IN_BITPOS 74 121 #define CFA_P40_ACT_VEB_TCAM_PARIF_IN_NUM_BITS 4 122 /** 123 * Number of VLAN Tags. (for idx 2 ...) 124 */ 125 #define CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_BITPOS 72 126 #define CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_NUM_BITS 2 127 /** 128 * Dest. MAC Address. 129 */ 130 #define CFA_P40_ACT_VEB_TCAM_MAC_BITPOS 24 131 #define CFA_P40_ACT_VEB_TCAM_MAC_NUM_BITS 48 132 /** 133 * Outer VLAN Tag ID. 134 */ 135 #define CFA_P40_ACT_VEB_TCAM_OVID_BITPOS 12 136 #define CFA_P40_ACT_VEB_TCAM_OVID_NUM_BITS 12 137 /** 138 * Inner VLAN Tag ID. 139 */ 140 #define CFA_P40_ACT_VEB_TCAM_IVID_BITPOS 0 141 #define CFA_P40_ACT_VEB_TCAM_IVID_NUM_BITS 12 142 143 enum cfa_p40_act_veb_tcam_flds { 144 CFA_P40_ACT_VEB_TCAM_VALID_FLD = 0, 145 CFA_P40_ACT_VEB_TCAM_RESERVED_FLD = 1, 146 CFA_P40_ACT_VEB_TCAM_PARIF_IN_FLD = 2, 147 CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_FLD = 3, 148 CFA_P40_ACT_VEB_TCAM_MAC_FLD = 4, 149 CFA_P40_ACT_VEB_TCAM_OVID_FLD = 5, 150 CFA_P40_ACT_VEB_TCAM_IVID_FLD = 6, 151 CFA_P40_ACT_VEB_TCAM_MAX_FLD 152 }; 153 154 #define CFA_P40_ACT_VEB_TCAM_TOTAL_NUM_BITS 80 155 156 /** 157 * Entry is valid. 158 */ 159 #define CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_BITPOS 18 160 #define CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_NUM_BITS 1 161 /** 162 * Action Record Pointer 163 */ 164 #define CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_BITPOS 2 165 #define CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_NUM_BITS 16 166 /** 167 * for resolving TCAM/EM conflicts 168 */ 169 #define CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_BITPOS 0 170 #define CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_NUM_BITS 2 171 172 enum cfa_p40_lkup_tcam_record_mem_flds { 173 CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_FLD = 0, 174 CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_FLD = 1, 175 CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_FLD = 2, 176 CFA_P40_LKUP_TCAM_RECORD_MEM_MAX_FLD 177 }; 178 179 #define CFA_P40_LKUP_TCAM_RECORD_MEM_TOTAL_NUM_BITS 19 180 181 /** 182 * (for idx 1 ...) 183 */ 184 #define CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_BITPOS 62 185 #define CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_NUM_BITS 2 186 enum cfa_p40_prof_ctxt_remap_mem_tpid_anti_spoof_ctl { 187 CFA_P40_PROF_CTXT_REMAP_MEM_TPID_IGNORE = 0x0UL, 188 189 CFA_P40_PROF_CTXT_REMAP_MEM_TPID_DROP = 0x1UL, 190 191 CFA_P40_PROF_CTXT_REMAP_MEM_TPID_DEFAULT = 0x2UL, 192 193 CFA_P40_PROF_CTXT_REMAP_MEM_TPID_SPIF = 0x3UL, 194 CFA_P40_PROF_CTXT_REMAP_MEM_TPID_MAX = 0x3UL 195 }; 196 /** 197 * (for idx 1 ...) 198 */ 199 #define CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_BITPOS 60 200 #define CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_NUM_BITS 2 201 enum cfa_p40_prof_ctxt_remap_mem_pri_anti_spoof_ctl { 202 CFA_P40_PROF_CTXT_REMAP_MEM_PRI_IGNORE = 0x0UL, 203 204 CFA_P40_PROF_CTXT_REMAP_MEM_PRI_DROP = 0x1UL, 205 206 CFA_P40_PROF_CTXT_REMAP_MEM_PRI_DEFAULT = 0x2UL, 207 208 CFA_P40_PROF_CTXT_REMAP_MEM_PRI_SPIF = 0x3UL, 209 CFA_P40_PROF_CTXT_REMAP_MEM_PRI_MAX = 0x3UL 210 }; 211 /** 212 * Bypass Source Properties Lookup. (for idx 1 ...) 213 */ 214 #define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_BITPOS 59 215 #define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_NUM_BITS 1 216 /** 217 * SP Record Pointer. (for idx 1 ...) 218 */ 219 #define CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_BITPOS 43 220 #define CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_NUM_BITS 16 221 /** 222 * BD Action pointer passing enable. (for idx 1 ...) 223 */ 224 #define CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_BITPOS 42 225 #define CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_NUM_BITS 1 226 /** 227 * Default VLAN TPID. (for idx 1 ...) 228 */ 229 #define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_BITPOS 39 230 #define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_NUM_BITS 3 231 /** 232 * Allowed VLAN TPIDs. (for idx 1 ...) 233 */ 234 #define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_BITPOS 33 235 #define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_NUM_BITS 6 236 /** 237 * Default VLAN PRI. 238 */ 239 #define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_BITPOS 30 240 #define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_NUM_BITS 3 241 /** 242 * Allowed VLAN PRIs. 243 */ 244 #define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_BITPOS 22 245 #define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_NUM_BITS 8 246 /** 247 * Partition. 248 */ 249 #define CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_BITPOS 18 250 #define CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_NUM_BITS 4 251 /** 252 * Bypass Lookup. 253 */ 254 #define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_BITPOS 17 255 #define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_NUM_BITS 1 256 257 /** 258 * L2 Context Remap Data. Action bypass mode (1) {7'd0,prof_vnic[9:0]} Note: 259 * should also set byp_lkup_en. Action bypass mode (0) byp_lkup_en(0) - 260 * {prof_func[6:0],l2_context[9:0]} byp_lkup_en(1) - {1'b0,act_rec_ptr[15:0]} 261 */ 262 263 #define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_BITPOS 0 264 #define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_NUM_BITS 12 265 266 #define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_BITPOS 10 267 #define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_NUM_BITS 7 268 269 #define CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_BITPOS 0 270 #define CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_NUM_BITS 10 271 272 #define CFA_P40_PROF_CTXT_REMAP_MEM_ARP_BITPOS 0 273 #define CFA_P40_PROF_CTXT_REMAP_MEM_ARP_NUM_BITS 16 274 275 enum cfa_p40_prof_ctxt_remap_mem_flds { 276 CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_FLD = 0, 277 CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_FLD = 1, 278 CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_FLD = 2, 279 CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_FLD = 3, 280 CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_FLD = 4, 281 CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_FLD = 5, 282 CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_FLD = 6, 283 CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_FLD = 7, 284 CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_FLD = 8, 285 CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_FLD = 9, 286 CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_FLD = 10, 287 CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_FLD = 11, 288 CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_FLD = 12, 289 CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_FLD = 13, 290 CFA_P40_PROF_CTXT_REMAP_MEM_ARP_FLD = 14, 291 CFA_P40_PROF_CTXT_REMAP_MEM_MAX_FLD 292 }; 293 294 #define CFA_P40_PROF_CTXT_REMAP_MEM_TOTAL_NUM_BITS 64 295 296 /** 297 * Bypass action pointer look up (for idx 1 ...) 298 */ 299 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_BITPOS 37 300 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_NUM_BITS 1 301 /** 302 * Exact match search enable (for idx 1 ...) 303 */ 304 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_BITPOS 36 305 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_NUM_BITS 1 306 /** 307 * Exact match profile 308 */ 309 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_BITPOS 28 310 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_NUM_BITS 8 311 /** 312 * Exact match key format 313 */ 314 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_BITPOS 23 315 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_NUM_BITS 5 316 /** 317 * Exact match key mask 318 */ 319 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_BITPOS 13 320 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_NUM_BITS 10 321 /** 322 * TCAM search enable 323 */ 324 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_BITPOS 12 325 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_NUM_BITS 1 326 /** 327 * TCAM profile 328 */ 329 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_BITPOS 4 330 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_NUM_BITS 8 331 /** 332 * TCAM key format 333 */ 334 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_BITPOS 0 335 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_NUM_BITS 4 336 337 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_BITPOS 16 338 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_NUM_BITS 2 339 340 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_BITPOS 0 341 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_NUM_BITS 16 342 343 enum cfa_p40_prof_profile_tcam_remap_mem_flds { 344 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_FLD = 0, 345 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_FLD = 1, 346 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_FLD = 2, 347 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_FLD = 3, 348 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_FLD = 4, 349 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_FLD = 5, 350 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_FLD = 6, 351 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_FLD = 7, 352 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_FLD = 8, 353 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_FLD = 9, 354 CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_MAX_FLD 355 }; 356 357 #define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TOTAL_NUM_BITS 38 358 359 /** 360 * Valid TCAM entry (for idx 2 ...) 361 */ 362 #define CFA_P40_PROF_PROFILE_TCAM_VALID_BITPOS 80 363 #define CFA_P40_PROF_PROFILE_TCAM_VALID_NUM_BITS 1 364 /** 365 * Packet type (for idx 2 ...) 366 */ 367 #define CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS 76 368 #define CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS 4 369 /** 370 * Pass through CFA (for idx 2 ...) 371 */ 372 #define CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_BITPOS 74 373 #define CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_NUM_BITS 2 374 /** 375 * Aggregate error (for idx 2 ...) 376 */ 377 #define CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS 73 378 #define CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS 1 379 /** 380 * Profile function (for idx 2 ...) 381 */ 382 #define CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS 66 383 #define CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS 7 384 /** 385 * Reserved for future use. Set to 0. 386 */ 387 #define CFA_P40_PROF_PROFILE_TCAM_RESERVED_BITPOS 57 388 #define CFA_P40_PROF_PROFILE_TCAM_RESERVED_NUM_BITS 9 389 /** 390 * non-tunnel(0)/tunneled(1) packet (for idx 1 ...) 391 */ 392 #define CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS 56 393 #define CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS 1 394 /** 395 * Tunnel L2 tunnel valid (for idx 1 ...) 396 */ 397 #define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS 55 398 #define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS 1 399 /** 400 * Tunnel L2 header type (for idx 1 ...) 401 */ 402 #define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS 53 403 #define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS 2 404 /** 405 * Remapped tunnel L2 dest_type UC(0)/MC(2)/BC(3) (for idx 1 ...) 406 */ 407 #define CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS 51 408 #define CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS 2 409 /** 410 * Tunnel L2 1+ VLAN tags present (for idx 1 ...) 411 */ 412 #define CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS 50 413 #define CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS 1 414 /** 415 * Tunnel L2 2 VLAN tags present (for idx 1 ...) 416 */ 417 #define CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS 49 418 #define CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS 1 419 /** 420 * Tunnel L3 valid (for idx 1 ...) 421 */ 422 #define CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_BITPOS 48 423 #define CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_NUM_BITS 1 424 /** 425 * Tunnel L3 error (for idx 1 ...) 426 */ 427 #define CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_BITPOS 47 428 #define CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_NUM_BITS 1 429 /** 430 * Tunnel L3 header type (for idx 1 ...) 431 */ 432 #define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS 43 433 #define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS 4 434 /** 435 * Tunnel L3 header is IPV4 or IPV6. (for idx 1 ...) 436 */ 437 #define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS 42 438 #define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS 1 439 /** 440 * Tunnel L3 IPV6 src address is compressed (for idx 1 ...) 441 */ 442 #define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_BITPOS 41 443 #define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_NUM_BITS 1 444 /** 445 * Tunnel L3 IPV6 dest address is compressed (for idx 1 ...) 446 */ 447 #define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_BITPOS 40 448 #define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_NUM_BITS 1 449 /** 450 * Tunnel L4 valid (for idx 1 ...) 451 */ 452 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS 39 453 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS 1 454 /** 455 * Tunnel L4 error (for idx 1 ...) 456 */ 457 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS 38 458 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS 1 459 /** 460 * Tunnel L4 header type (for idx 1 ...) 461 */ 462 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS 34 463 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS 4 464 /** 465 * Tunnel L4 header is UDP or TCP (for idx 1 ...) 466 */ 467 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS 33 468 #define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS 1 469 /** 470 * Tunnel valid (for idx 1 ...) 471 */ 472 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS 32 473 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS 1 474 /** 475 * Tunnel error 476 */ 477 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_BITPOS 31 478 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_NUM_BITS 1 479 /** 480 * Tunnel header type 481 */ 482 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS 27 483 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS 4 484 /** 485 * Tunnel header flags 486 */ 487 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS 24 488 #define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS 3 489 /** 490 * L2 header valid 491 */ 492 #define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS 23 493 #define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS 1 494 /** 495 * L2 header error 496 */ 497 #define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS 22 498 #define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS 1 499 /** 500 * L2 header type 501 */ 502 #define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS 20 503 #define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS 2 504 /** 505 * Remapped L2 dest_type UC(0)/MC(2)/BC(3) 506 */ 507 #define CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS 18 508 #define CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS 2 509 /** 510 * L2 header 1+ VLAN tags present 511 */ 512 #define CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS 17 513 #define CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS 1 514 /** 515 * L2 header 2 VLAN tags present 516 */ 517 #define CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS 16 518 #define CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS 1 519 /** 520 * L3 header valid 521 */ 522 #define CFA_P40_PROF_PROFILE_TCAM_L3_VALID_BITPOS 15 523 #define CFA_P40_PROF_PROFILE_TCAM_L3_VALID_NUM_BITS 1 524 /** 525 * L3 header error 526 */ 527 #define CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_BITPOS 14 528 #define CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_NUM_BITS 1 529 /** 530 * L3 header type 531 */ 532 #define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS 10 533 #define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS 4 534 /** 535 * L3 header is IPV4 or IPV6. 536 */ 537 #define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS 9 538 #define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS 1 539 /** 540 * L3 header IPV6 src address is compressed 541 */ 542 #define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_BITPOS 8 543 #define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_NUM_BITS 1 544 /** 545 * L3 header IPV6 dest address is compressed 546 */ 547 #define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_BITPOS 7 548 #define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_NUM_BITS 1 549 /** 550 * L4 header valid 551 */ 552 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS 6 553 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS 1 554 /** 555 * L4 header error 556 */ 557 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS 5 558 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS 1 559 /** 560 * L4 header type 561 */ 562 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS 1 563 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS 4 564 /** 565 * L4 header is UDP or TCP 566 */ 567 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS 0 568 #define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS 1 569 570 enum cfa_p40_prof_profile_tcam_flds { 571 CFA_P40_PROF_PROFILE_TCAM_VALID_FLD = 0, 572 CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 1, 573 CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_FLD = 2, 574 CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 3, 575 CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 4, 576 CFA_P40_PROF_PROFILE_TCAM_RESERVED_FLD = 5, 577 CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 6, 578 CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 7, 579 CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 8, 580 CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 9, 581 CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 10, 582 CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 11, 583 CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_FLD = 12, 584 CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_FLD = 13, 585 CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 14, 586 CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 15, 587 CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_FLD = 16, 588 CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_FLD = 17, 589 CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 18, 590 CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 19, 591 CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 20, 592 CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 21, 593 CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 22, 594 CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_FLD = 23, 595 CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 24, 596 CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 25, 597 CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 26, 598 CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 27, 599 CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 28, 600 CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 29, 601 CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 30, 602 CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 31, 603 CFA_P40_PROF_PROFILE_TCAM_L3_VALID_FLD = 32, 604 CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_FLD = 33, 605 CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 34, 606 CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 35, 607 CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_FLD = 36, 608 CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_FLD = 37, 609 CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 38, 610 CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 39, 611 CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 40, 612 CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 41, 613 CFA_P40_PROF_PROFILE_TCAM_MAX_FLD 614 }; 615 616 #define CFA_P40_PROF_PROFILE_TCAM_TOTAL_NUM_BITS 81 617 618 /** 619 * CFA flexible key layout definition 620 */ 621 enum cfa_p40_key_fld_id { 622 CFA_P40_KEY_FLD_ID_MAX 623 }; 624 625 /**************************************************************************/ 626 /** 627 * Non-autogenerated fields 628 */ 629 630 /** 631 * Valid 632 */ 633 #define CFA_P40_EEM_KEY_TBL_VALID_BITPOS 0 634 #define CFA_P40_EEM_KEY_TBL_VALID_NUM_BITS 1 635 636 /** 637 * L1 Cacheable 638 */ 639 #define CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_BITPOS 1 640 #define CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_NUM_BITS 1 641 642 /** 643 * Strength 644 */ 645 #define CFA_P40_EEM_KEY_TBL_STRENGTH_BITPOS 2 646 #define CFA_P40_EEM_KEY_TBL_STRENGTH_NUM_BITS 2 647 648 /** 649 * Key Size 650 */ 651 #define CFA_P40_EEM_KEY_TBL_KEY_SZ_BITPOS 15 652 #define CFA_P40_EEM_KEY_TBL_KEY_SZ_NUM_BITS 9 653 654 /** 655 * Record Size 656 */ 657 #define CFA_P40_EEM_KEY_TBL_REC_SZ_BITPOS 24 658 #define CFA_P40_EEM_KEY_TBL_REC_SZ_NUM_BITS 5 659 660 /** 661 * Action Record Internal 662 */ 663 #define CFA_P40_EEM_KEY_TBL_ACT_REC_INT_BITPOS 29 664 #define CFA_P40_EEM_KEY_TBL_ACT_REC_INT_NUM_BITS 1 665 666 /** 667 * External Flow Counter 668 */ 669 #define CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_BITPOS 30 670 #define CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_NUM_BITS 1 671 672 /** 673 * Action Record Pointer 674 */ 675 #define CFA_P40_EEM_KEY_TBL_AR_PTR_BITPOS 31 676 #define CFA_P40_EEM_KEY_TBL_AR_PTR_NUM_BITS 33 677 678 /** 679 * EEM Key omitted - create using keybuilder 680 * Fields here cannot be larger than a uint64_t 681 */ 682 683 #define CFA_P40_EEM_KEY_TBL_TOTAL_NUM_BITS 64 684 685 enum cfa_p40_eem_key_tbl_flds { 686 CFA_P40_EEM_KEY_TBL_VALID_FLD = 0, 687 CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_FLD = 1, 688 CFA_P40_EEM_KEY_TBL_STRENGTH_FLD = 2, 689 CFA_P40_EEM_KEY_TBL_KEY_SZ_FLD = 3, 690 CFA_P40_EEM_KEY_TBL_REC_SZ_FLD = 4, 691 CFA_P40_EEM_KEY_TBL_ACT_REC_INT_FLD = 5, 692 CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_FLD = 6, 693 CFA_P40_EEM_KEY_TBL_AR_PTR_FLD = 7, 694 CFA_P40_EEM_KEY_TBL_MAX_FLD 695 }; 696 697 /** 698 * Mirror Destination 0 Source Property Record Pointer 699 */ 700 #define CFA_P40_MIRROR_TBL_SP_PTR_BITPOS 0 701 #define CFA_P40_MIRROR_TBL_SP_PTR_NUM_BITS 11 702 703 /** 704 * ignore or honor drop 705 */ 706 #define CFA_P40_MIRROR_TBL_IGN_DROP_BITPOS 13 707 #define CFA_P40_MIRROR_TBL_IGN_DROP_NUM_BITS 1 708 709 /** 710 * ingress or egress copy 711 */ 712 #define CFA_P40_MIRROR_TBL_COPY_BITPOS 14 713 #define CFA_P40_MIRROR_TBL_COPY_NUM_BITS 1 714 715 /** 716 * Mirror Destination enable. 717 */ 718 #define CFA_P40_MIRROR_TBL_EN_BITPOS 15 719 #define CFA_P40_MIRROR_TBL_EN_NUM_BITS 1 720 721 /** 722 * Action Record Pointer 723 */ 724 #define CFA_P40_MIRROR_TBL_AR_PTR_BITPOS 16 725 #define CFA_P40_MIRROR_TBL_AR_PTR_NUM_BITS 16 726 727 #define CFA_P40_MIRROR_TBL_TOTAL_NUM_BITS 32 728 729 enum cfa_p40_mirror_tbl_flds { 730 CFA_P40_MIRROR_TBL_SP_PTR_FLD = 0, 731 CFA_P40_MIRROR_TBL_IGN_DROP_FLD = 1, 732 CFA_P40_MIRROR_TBL_COPY_FLD = 2, 733 CFA_P40_MIRROR_TBL_EN_FLD = 3, 734 CFA_P40_MIRROR_TBL_AR_PTR_FLD = 4, 735 CFA_P40_MIRROR_TBL_MAX_FLD 736 }; 737 738 /** 739 * P45 Specific Updates (SR) - Non-autogenerated 740 */ 741 /** 742 * Valid TCAM entry. 743 */ 744 #define CFA_P45_PROF_L2_CTXT_TCAM_VALID_BITPOS 166 745 #define CFA_P45_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1 746 /** 747 * Source Partition. 748 */ 749 #define CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_BITPOS 166 750 #define CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS 4 751 752 /** 753 * Source Virtual I/F. 754 */ 755 #define CFA_P45_PROF_L2_CTXT_TCAM_SVIF_BITPOS 72 756 #define CFA_P45_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS 12 757 758 759 /* The SR layout of the l2 ctxt key is different from the Wh+. Switch to 760 * cfa_p45_hw.h definition when available. 761 */ 762 enum cfa_p45_prof_l2_ctxt_tcam_flds { 763 CFA_P45_PROF_L2_CTXT_TCAM_VALID_FLD = 0, 764 CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_FLD = 1, 765 CFA_P45_PROF_L2_CTXT_TCAM_KEY_TYPE_FLD = 2, 766 CFA_P45_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_FLD = 3, 767 CFA_P45_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_FLD = 4, 768 CFA_P45_PROF_L2_CTXT_TCAM_L2_NUMTAGS_FLD = 5, 769 CFA_P45_PROF_L2_CTXT_TCAM_MAC1_FLD = 6, 770 CFA_P45_PROF_L2_CTXT_TCAM_T_OVID_FLD = 7, 771 CFA_P45_PROF_L2_CTXT_TCAM_T_IVID_FLD = 8, 772 CFA_P45_PROF_L2_CTXT_TCAM_SVIF_FLD = 9, 773 CFA_P45_PROF_L2_CTXT_TCAM_MAC0_FLD = 10, 774 CFA_P45_PROF_L2_CTXT_TCAM_OVID_FLD = 11, 775 CFA_P45_PROF_L2_CTXT_TCAM_IVID_FLD = 12, 776 CFA_P45_PROF_L2_CTXT_TCAM_MAX_FLD 777 }; 778 779 #define CFA_P45_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 171 780 781 #endif /* _CFA_P40_HW_H_ */ 782