1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 5 * reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * NETLOGIC_BSD 31 * $FreeBSD$ 32 */ 33 34 #ifndef __NLM_HAL_BRIDGE_H__ 35 #define __NLM_HAL_BRIDGE_H__ 36 37 /** 38 * @file_name mio.h 39 * @author Netlogic Microsystems 40 * @brief Basic definitions of XLP memory and io subsystem 41 */ 42 43 /* 44 * BRIDGE specific registers 45 * 46 * These registers start after the PCIe header, which has 0x40 47 * standard entries 48 */ 49 #define BRIDGE_MODE 0x00 50 #define BRIDGE_PCI_CFG_BASE 0x01 51 #define BRIDGE_PCI_CFG_LIMIT 0x02 52 #define BRIDGE_PCIE_CFG_BASE 0x03 53 #define BRIDGE_PCIE_CFG_LIMIT 0x04 54 #define BRIDGE_BUSNUM_BAR0 0x05 55 #define BRIDGE_BUSNUM_BAR1 0x06 56 #define BRIDGE_BUSNUM_BAR2 0x07 57 #define BRIDGE_BUSNUM_BAR3 0x08 58 #define BRIDGE_BUSNUM_BAR4 0x09 59 #define BRIDGE_BUSNUM_BAR5 0x0a 60 #define BRIDGE_BUSNUM_BAR6 0x0b 61 #define BRIDGE_FLASH_BAR0 0x0c 62 #define BRIDGE_FLASH_BAR1 0x0d 63 #define BRIDGE_FLASH_BAR2 0x0e 64 #define BRIDGE_FLASH_BAR3 0x0f 65 #define BRIDGE_FLASH_LIMIT0 0x10 66 #define BRIDGE_FLASH_LIMIT1 0x11 67 #define BRIDGE_FLASH_LIMIT2 0x12 68 #define BRIDGE_FLASH_LIMIT3 0x13 69 70 #define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 71 #define BRIDGE_DRAM_BAR0 0x14 72 #define BRIDGE_DRAM_BAR1 0x15 73 #define BRIDGE_DRAM_BAR2 0x16 74 #define BRIDGE_DRAM_BAR3 0x17 75 #define BRIDGE_DRAM_BAR4 0x18 76 #define BRIDGE_DRAM_BAR5 0x19 77 #define BRIDGE_DRAM_BAR6 0x1a 78 #define BRIDGE_DRAM_BAR7 0x1b 79 80 #define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 81 #define BRIDGE_DRAM_LIMIT0 0x1c 82 #define BRIDGE_DRAM_LIMIT1 0x1d 83 #define BRIDGE_DRAM_LIMIT2 0x1e 84 #define BRIDGE_DRAM_LIMIT3 0x1f 85 #define BRIDGE_DRAM_LIMIT4 0x20 86 #define BRIDGE_DRAM_LIMIT5 0x21 87 #define BRIDGE_DRAM_LIMIT6 0x22 88 #define BRIDGE_DRAM_LIMIT7 0x23 89 90 #define BRIDGE_DRAM_NODE_TRANSLN0 0x24 91 #define BRIDGE_DRAM_NODE_TRANSLN1 0x25 92 #define BRIDGE_DRAM_NODE_TRANSLN2 0x26 93 #define BRIDGE_DRAM_NODE_TRANSLN3 0x27 94 #define BRIDGE_DRAM_NODE_TRANSLN4 0x28 95 #define BRIDGE_DRAM_NODE_TRANSLN5 0x29 96 #define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 97 #define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 98 #define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 99 #define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 100 #define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 101 #define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f 102 #define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 103 #define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 104 #define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 105 #define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 106 #define BRIDGE_PCIEMEM_BASE0 0x34 107 #define BRIDGE_PCIEMEM_BASE1 0x35 108 #define BRIDGE_PCIEMEM_BASE2 0x36 109 #define BRIDGE_PCIEMEM_BASE3 0x37 110 #define BRIDGE_PCIEMEM_LIMIT0 0x38 111 #define BRIDGE_PCIEMEM_LIMIT1 0x39 112 #define BRIDGE_PCIEMEM_LIMIT2 0x3a 113 #define BRIDGE_PCIEMEM_LIMIT3 0x3b 114 #define BRIDGE_PCIEIO_BASE0 0x3c 115 #define BRIDGE_PCIEIO_BASE1 0x3d 116 #define BRIDGE_PCIEIO_BASE2 0x3e 117 #define BRIDGE_PCIEIO_BASE3 0x3f 118 #define BRIDGE_PCIEIO_LIMIT0 0x40 119 #define BRIDGE_PCIEIO_LIMIT1 0x41 120 #define BRIDGE_PCIEIO_LIMIT2 0x42 121 #define BRIDGE_PCIEIO_LIMIT3 0x43 122 #define BRIDGE_PCIEMEM_BASE4 0x44 123 #define BRIDGE_PCIEMEM_BASE5 0x45 124 #define BRIDGE_PCIEMEM_BASE6 0x46 125 #define BRIDGE_PCIEMEM_LIMIT4 0x47 126 #define BRIDGE_PCIEMEM_LIMIT5 0x48 127 #define BRIDGE_PCIEMEM_LIMIT6 0x49 128 #define BRIDGE_PCIEIO_BASE4 0x4a 129 #define BRIDGE_PCIEIO_BASE5 0x4b 130 #define BRIDGE_PCIEIO_BASE6 0x4c 131 #define BRIDGE_PCIEIO_LIMIT4 0x4d 132 #define BRIDGE_PCIEIO_LIMIT5 0x4e 133 #define BRIDGE_PCIEIO_LIMIT6 0x4f 134 #define BRIDGE_NBU_EVENT_CNT_CTL 0x50 135 #define BRIDGE_EVNTCTR1_LOW 0x51 136 #define BRIDGE_EVNTCTR1_HI 0x52 137 #define BRIDGE_EVNT_CNT_CTL2 0x53 138 #define BRIDGE_EVNTCTR2_LOW 0x54 139 #define BRIDGE_EVNTCTR2_HI 0x55 140 #define BRIDGE_TRACEBUF_MATCH0 0x56 141 #define BRIDGE_TRACEBUF_MATCH1 0x57 142 #define BRIDGE_TRACEBUF_MATCH_LOW 0x58 143 #define BRIDGE_TRACEBUF_MATCH_HI 0x59 144 #define BRIDGE_TRACEBUF_CTRL 0x5a 145 #define BRIDGE_TRACEBUF_INIT 0x5b 146 #define BRIDGE_TRACEBUF_ACCESS 0x5c 147 #define BRIDGE_TRACEBUF_READ_DATA0 0x5d 148 #define BRIDGE_TRACEBUF_READ_DATA1 0x5d 149 #define BRIDGE_TRACEBUF_READ_DATA2 0x5f 150 #define BRIDGE_TRACEBUF_READ_DATA3 0x60 151 #define BRIDGE_TRACEBUF_STATUS 0x61 152 #define BRIDGE_ADDRESS_ERROR0 0x62 153 #define BRIDGE_ADDRESS_ERROR1 0x63 154 #define BRIDGE_ADDRESS_ERROR2 0x64 155 #define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 156 #define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 157 #define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 158 #define BRIDGE_LINE_FLUSH0 0x68 159 #define BRIDGE_LINE_FLUSH1 0x69 160 #define BRIDGE_NODE_ID 0x6a 161 #define BRIDGE_ERROR_INTERRUPT_EN 0x6b 162 #define BRIDGE_PCIE0_WEIGHT 0x2c0 163 #define BRIDGE_PCIE1_WEIGHT 0x2c1 164 #define BRIDGE_PCIE2_WEIGHT 0x2c2 165 #define BRIDGE_PCIE3_WEIGHT 0x2c3 166 #define BRIDGE_USB_WEIGHT 0x2c4 167 #define BRIDGE_NET_WEIGHT 0x2c5 168 #define BRIDGE_POE_WEIGHT 0x2c6 169 #define BRIDGE_CMS_WEIGHT 0x2c7 170 #define BRIDGE_DMAENG_WEIGHT 0x2c8 171 #define BRIDGE_SEC_WEIGHT 0x2c9 172 #define BRIDGE_COMP_WEIGHT 0x2ca 173 #define BRIDGE_GIO_WEIGHT 0x2cb 174 #define BRIDGE_FLASH_WEIGHT 0x2cc 175 176 #if !defined(LOCORE) && !defined(__ASSEMBLY__) 177 178 #define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 179 #define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 180 #define nlm_get_bridge_pcibase(node) \ 181 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) 182 #define nlm_get_bridge_regbase(node) \ 183 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 184 185 #endif 186 #endif 187