Home
last modified time | relevance | path

Searched refs:BIT_ULL (Results 1 – 25 of 55) sorted by relevance

123

/f-stack/dpdk/drivers/net/ice/
H A Dice_hash.c455 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA)},
457 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA)},
459 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA)},
461 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA)},
463 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA) |
464 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA)},
469 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA)},
471 BIT_ULL(ICE_FLOW_FIELD_IDX_C_VLAN)},
473 BIT_ULL(ICE_FLOW_FIELD_IDX_S_VLAN)},
475 BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI)},
[all …]
H A Dice_ethdev.h96 #define ICE_FLAG_RSS BIT_ULL(0)
97 #define ICE_FLAG_DCB BIT_ULL(1)
98 #define ICE_FLAG_VMDQ BIT_ULL(2)
99 #define ICE_FLAG_SRIOV BIT_ULL(3)
100 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
101 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
102 #define ICE_FLAG_FDIR BIT_ULL(6)
103 #define ICE_FLAG_VXLAN BIT_ULL(7)
104 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
105 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
/f-stack/dpdk/drivers/net/hns3/
H A Dhns3_rss.c80 BIT_ULL(HNS3_RSS_FIELD_IPV4_EN_FRAG_IP_S) },
82 BIT_ULL(HNS3_RSS_FIELD_IPV4_EN_FRAG_IP_D) },
84 BIT_ULL(HNS3_RSS_FIELD_IPV4_TCP_EN_IP_S) },
86 BIT_ULL(HNS3_RSS_FIELD_IPV4_TCP_EN_IP_D) },
92 BIT_ULL(HNS3_RSS_FIELD_IPV4_UDP_EN_IP_S) },
94 BIT_ULL(HNS3_RSS_FIELD_IPV4_UDP_EN_IP_D) },
112 BIT_ULL(HNS3_RSS_FIELD_IPV6_FRAG_IP_S) },
114 BIT_ULL(HNS3_RSS_FIELD_IPV6_FRAG_IP_D) },
152 BIT_ULL(HNS3_RSS_FIELD_IPV4_TCP_EN_IP_D) |
156 BIT_ULL(HNS3_RSS_FIELD_IPV4_TCP_EN_IP_D) |
[all …]
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_flow.h21 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
22 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
24 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
25 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
27 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
28 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
40 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
76 (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
115 (BIT_ULL(ICE_FLOW_FIELD_IDX_PFCP_SEID))
129 (BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI))
[all …]
H A Dice_adminq_cmd.h1213 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1214 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1215 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1219 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1220 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1221 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1223 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1224 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1225 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1256 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
[all …]
H A Dice_type.h13 #define BIT_ULL(a) (1ULL << (a)) macro
117 #define ICE_DBG_INIT BIT_ULL(1)
120 #define ICE_DBG_LINK BIT_ULL(4)
121 #define ICE_DBG_PHY BIT_ULL(5)
122 #define ICE_DBG_QCTX BIT_ULL(6)
123 #define ICE_DBG_NVM BIT_ULL(7)
124 #define ICE_DBG_LAN BIT_ULL(8)
125 #define ICE_DBG_FLOW BIT_ULL(9)
126 #define ICE_DBG_DCB BIT_ULL(10)
128 #define ICE_DBG_FD BIT_ULL(12)
[all …]
/f-stack/dpdk/drivers/net/octeontx2/
H A Dotx2_tm.h12 #define NIX_TM_DEFAULT_TREE BIT_ULL(0)
13 #define NIX_TM_COMMITTED BIT_ULL(1)
14 #define NIX_TM_RATE_LIMIT_TREE BIT_ULL(2)
15 #define NIX_TM_TL1_NO_SP BIT_ULL(3)
46 #define NIX_TM_NODE_HWRES BIT_ULL(0)
47 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
48 #define NIX_TM_NODE_USER BIT_ULL(2)
49 #define NIX_TM_NODE_RED_DISCARD BIT_ULL(3)
83 #define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)
H A Dotx2_ethdev_irq.c134 if (reg & BIT_ULL(42) /* OP_ERR */) { in nix_lf_q_irq_get_and_clear()
170 if (reg & BIT_ULL(44)) in nix_lf_sq_debug_reg()
209 if (irq & BIT_ULL(NIX_RQINT_DROP)) in nix_lf_q_irq()
212 if (irq & BIT_ULL(NIX_RQINT_RED)) in nix_lf_q_irq()
224 if (irq & BIT_ULL(NIX_CQERRINT_WR_FULL)) in nix_lf_q_irq()
236 if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) { in nix_lf_q_irq()
240 if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) { in nix_lf_q_irq()
244 if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) { in nix_lf_q_irq()
451 otx2_write64(BIT_ULL(0), dev->base + in otx2_nix_rx_queue_intr_enable()
464 otx2_write64(BIT_ULL(0), dev->base + in otx2_nix_rx_queue_intr_disable()
[all …]
/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_type.h27 #ifndef BIT_ULL
28 #define BIT_ULL(a) (1ULL << (a)) macro
310 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
741 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
742 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
743 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
744 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
745 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
746 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
747 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
[all …]
H A Di40e_adminq_cmd.h1961 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1963 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1964 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1965 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1966 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1967 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1974 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1975 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1976 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1977 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
[all …]
/f-stack/dpdk/drivers/raw/ifpga/base/
H A Dopae_spi.h32 #define CTRL_R BIT_ULL(9)
33 #define CTRL_W BIT_ULL(8)
36 #define READ_DATA_VALID BIT_ULL(32)
139 #define CONTROL_TYPE BIT_ULL(48)
143 #define CLOCK_PHASE BIT_ULL(15)
144 #define CLOCK_POLARITY BIT_ULL(14)
147 #define SHIFT_DIRECTION BIT_ULL(1)
148 #define SPI_TYPE BIT_ULL(0)
156 #define NIOS_SPI_VALID BIT_ULL(32)
H A Dopae_i2c.h50 #define I2C_CTRL_R BIT_ULL(9)
51 #define I2C_CTRL_W BIT_ULL(8)
54 #define I2C_READ_DATA_VALID BIT_ULL(32)
H A Dopae_eth_group.h36 #define CTRL_FEAT_SELECT BIT_ULL(48)
44 #define STAT_DATA_VAL BIT_ULL(32)
H A Dopae_osdep.h41 #ifndef BIT_ULL
42 #define BIT_ULL(a) (1ULL << (a)) macro
/f-stack/dpdk/drivers/mempool/octeontx2/
H A Dotx2_mempool.h55 #define AURA_ID_MASK (BIT_ULL(16) - 1)
91 wdata |= BIT_ULL(63); /* DROP */ in npa_lf_aura_op_alloc()
104 reg |= BIT_ULL(63); /* FABS */ in npa_lf_aura_op_free()
122 if (reg & BIT_ULL(42) /* OP_ERR */) in npa_lf_aura_op_cnt_get()
131 uint64_t reg = count & (BIT_ULL(36) - 1); in npa_lf_aura_op_cnt_set()
134 reg |= BIT_ULL(43); /* CNT_ADD */ in npa_lf_aura_op_cnt_set()
154 if (reg & BIT_ULL(42) /* OP_ERR */) in npa_lf_aura_op_limit_get()
163 uint64_t reg = limit & (BIT_ULL(36) - 1); in npa_lf_aura_op_limit_set()
183 if (reg & BIT_ULL(42) /* OP_ERR */) in npa_lf_aura_op_available()
H A Dotx2_mempool_irq.c119 if (reg & BIT_ULL(42) /* OP_ERR */) { in npa_lf_q_irq_get_and_clear()
167 if (irq & BIT_ULL(NPA_POOL_ERR_INT_OVFLS)) in npa_lf_q_irq()
170 if (irq & BIT_ULL(NPA_POOL_ERR_INT_RANGE)) in npa_lf_q_irq()
173 if (irq & BIT_ULL(NPA_POOL_ERR_INT_PERR)) in npa_lf_q_irq()
187 if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_OVER)) in npa_lf_q_irq()
190 if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_UNDER)) in npa_lf_q_irq()
193 if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_FREE_UNDER)) in npa_lf_q_irq()
196 if (irq & BIT_ULL(NPA_AURA_ERR_INT_POOL_DIS)) in npa_lf_q_irq()
/f-stack/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_nsp_eth.c47 #define NSP_ETH_PORT_FEC_SUPP_RS BIT_ULL(61)
51 #define NSP_ETH_STATE_CONFIGURED BIT_ULL(0)
52 #define NSP_ETH_STATE_ENABLED BIT_ULL(1)
53 #define NSP_ETH_STATE_TX_ENABLED BIT_ULL(2)
54 #define NSP_ETH_STATE_RX_ENABLED BIT_ULL(3)
62 #define NSP_ETH_CTRL_CONFIGURED BIT_ULL(0)
63 #define NSP_ETH_CTRL_ENABLED BIT_ULL(1)
66 #define NSP_ETH_CTRL_SET_RATE BIT_ULL(4)
67 #define NSP_ETH_CTRL_SET_LANES BIT_ULL(5)
68 #define NSP_ETH_CTRL_SET_ANEG BIT_ULL(6)
[all …]
/f-stack/dpdk/drivers/common/octeontx2/hw/
H A Dotx2_tim.h21 #define TIM_AF_FLAGS_REG_ENA_TIM BIT_ULL(0)
22 #define TIM_AF_RINGX_CTL1_ENA BIT_ULL(47)
23 #define TIM_AF_RINGX_CTL1_RCF_BUSY BIT_ULL(50)
H A Dotx2_sso.h173 #define SSO_HWGRP_AW_CFG_RWEN BIT_ULL(0)
174 #define SSO_HWGRP_AW_CFG_LDWB BIT_ULL(1)
175 #define SSO_HWGRP_AW_CFG_LDT BIT_ULL(2)
176 #define SSO_HWGRP_AW_CFG_STT BIT_ULL(3)
177 #define SSO_HWGRP_AW_CFG_XAQ_BYP_DIS BIT_ULL(4)
179 #define SSO_HWGRP_AW_STS_TPTR_VLD BIT_ULL(8)
180 #define SSO_HWGRP_AW_STS_NPA_FETCH BIT_ULL(9)
/f-stack/dpdk/drivers/common/iavf/
H A Diavf_type.h24 #define BIT_ULL(a) (1ULL << (a)) macro
347 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
348 #define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
349 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
350 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
351 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
631 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
860 #define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
892 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
897 BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
[all …]
/f-stack/dpdk/drivers/net/nfp/nfpcore/nfp-common/
H A Dnfp_platform.h20 #ifndef BIT_ULL
22 #define BIT_ULL(x) (1ULL << (x)) macro
/f-stack/dpdk/drivers/event/octeontx2/
H A Dotx2_worker.c324 val |= BIT_ULL(18); /* Grouped */ in ssogws_flush_events()
325 val |= BIT_ULL(16); /* WAIT */ in ssogws_flush_events()
364 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58))); in ssogws_reset()
379 } while (pend_state & BIT_ULL(58)); in ssogws_reset()
H A Dotx2_worker.h27 otx2_write64(BIT_ULL(16) | /* wait for work. */ in otx2_ssogws_get_work()
55 while ((BIT_ULL(63)) & event.get_work0) in otx2_ssogws_get_work()
127 while ((BIT_ULL(63)) & event.get_work0) in otx2_ssogws_get_work_empty()
233 while (otx2_read64(ws->tag_op) & BIT_ULL(62)) in otx2_ssogws_swtag_wait()
257 while (!(otx2_read64(ws->tag_op) & BIT_ULL(35))) in otx2_ssogws_head_wait()
H A Dotx2_tim_worker.h265 } while (hbt_state & BIT_ULL(33)); in tim_add_entry_sp()
268 if (!(hbt_state & BIT_ULL(34))) { in tim_add_entry_sp()
350 } while (hbt_state & BIT_ULL(33)); in tim_add_entry_mp()
353 if (!(hbt_state & BIT_ULL(34))) { in tim_add_entry_mp()
490 } while (hbt_state & BIT_ULL(33)); in tim_add_entry_brst()
493 if (!(hbt_state & BIT_ULL(34))) { in tim_add_entry_brst()
H A Dotx2_worker_dual.h23 const uint64_t set_gw = BIT_ULL(16) | 1; in otx2_ssogws_dual_get_work()
52 while ((BIT_ULL(63)) & event.get_work0) in otx2_ssogws_dual_get_work()

123