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Searched refs:BIT (Results 1 – 25 of 168) sorted by relevance

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/f-stack/freebsd/mips/atheros/
H A Dqca955xreg.h31 #define BIT(x) (1 << (x)) macro
148 #define QCA955X_RESET_HOST BIT(31)
149 #define QCA955X_RESET_SLIC BIT(30)
150 #define QCA955X_RESET_HDMA BIT(29)
152 #define QCA955X_RESET_RTC BIT(27)
163 #define QCA955X_RESET_DDR BIT(16)
171 #define QCA955X_RESET_SGMII BIT(8)
173 #define QCA955X_RESET_PCIE BIT(6)
177 #define QCA955X_RESET_LUT BIT(2)
178 #define QCA955X_RESET_MBOX BIT(1)
[all …]
H A Dqca953xreg.h31 #define BIT(x) (1 << (x)) macro
111 #define QCA953X_RESET_RTC BIT(27)
115 #define QCA953X_RESET_CPU_NMI BIT(21)
117 #define QCA953X_RESET_DDR BIT(16)
119 #define QCA953X_RESET_GE1_MAC BIT(13)
122 #define QCA953X_RESET_GE0_MAC BIT(9)
124 #define QCA953X_RESET_PCIE_PHY BIT(7)
125 #define QCA953X_RESET_PCIE BIT(6)
126 #define QCA953X_RESET_USB_HOST BIT(5)
127 #define QCA953X_RESET_USB_PHY BIT(4)
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H A Dar934x_nfcreg.h41 #define BIT(x) (1 << (x)) macro
84 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
86 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
96 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
97 #define AR934X_NFC_CTRL_INT_EN BIT(4)
98 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
117 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
118 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
125 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
138 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
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/f-stack/dpdk/drivers/net/pfe/base/cbus/
H A Dhif.h31 #define HIF_INT BIT(0)
32 #define HIF_RXBD_INT BIT(1)
33 #define HIF_RXPKT_INT BIT(2)
34 #define HIF_TXBD_INT BIT(3)
35 #define HIF_TXPKT_INT BIT(4)
46 #define HIF_INT_EN BIT(0)
47 #define HIF_RXBD_INT_EN BIT(1)
48 #define HIF_RXPKT_INT_EN BIT(2)
64 #define BD_CTRL_LIFM BIT(18)
66 #define BD_CTRL_DIR BIT(20)
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H A Dtmu_csr.h132 #define SW_RESET BIT(0) /* Global software reset */
133 #define INQ_RESET BIT(2)
134 #define TEQ_RESET BIT(3)
135 #define TDQ_RESET BIT(4)
136 #define PE_RESET BIT(5)
137 #define MEM_INIT BIT(6)
138 #define MEM_INIT_DONE BIT(7)
139 #define LLM_INIT BIT(8)
140 #define LLM_INIT_DONE BIT(9)
141 #define ECC_MEM_INIT_DONE BIT(10)
H A Dclass_csr.h248 #define TWO_LEVEL_ROUTE BIT(0)
249 #define PHYNO_IN_HASH BIT(1)
250 #define HW_ROUTE_FETCH BIT(3)
251 #define HW_BRIDGE_FETCH BIT(5)
252 #define IP_ALIGNED BIT(6)
253 #define ARC_HIT_CHECK_EN BIT(7)
254 #define CLASS_TOE BIT(11)
256 #define HASH_CRC_PORT BIT(12)
259 #define QB2BUS_LE BIT(15)
261 #define TCP_CHKSUM_DROP BIT(0)
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/f-stack/freebsd/amd64/vmm/amd/
H A Dvmcb.h34 #define BIT(n) (1ULL << n) macro
49 #define VMCB_INTCPT_INTR BIT(0)
50 #define VMCB_INTCPT_NMI BIT(1)
51 #define VMCB_INTCPT_SMI BIT(2)
52 #define VMCB_INTCPT_INIT BIT(3)
53 #define VMCB_INTCPT_VINTR BIT(4)
66 #define VMCB_INTCPT_POPF BIT(17)
68 #define VMCB_INTCPT_RSM BIT(19)
76 #define VMCB_INTCPT_IO BIT(27)
87 #define VMCB_INTCPT_STGI BIT(4)
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H A Damdvi_priv.h36 #define BIT(n) (1ULL << (n)) macro
291 #define AMDVI_CTRL_PPW BIT(8)
292 #define AMDVI_CTRL_RPPW BIT(9)
293 #define AMDVI_CTRL_COH BIT(10)
294 #define AMDVI_CTRL_ISOC BIT(11)
296 #define AMDVI_CTRL_PPRLOG BIT(13)
298 #define AMDVI_CTRL_PPREN BIT(15)
323 #define AMDVI_PT_PRESENT BIT(0)
325 #define AMDVI_PT_READ BIT(61)
326 #define AMDVI_PT_WRITE BIT(62)
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/f-stack/dpdk/drivers/net/ice/base/
H A Dice_hw_autogen.h11 #define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
13 #define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1)
15 #define GL_RDPU_CNTRL_BLNC_EN_M BIT(2)
43 #define MSIX_TVCTRL_MASK_M BIT(0)
1986 #define GLTCB_WB_RL_EN_M BIT(16)
1991 #define GLTPB_WB_RL_EN_M BIT(16)
3087 #define GL_FWSTS_FWRI_M BIT(9)
5113 #define QRX_CTRL_CDE_M BIT(3)
5115 #define QRX_CTRL_CDS_M BIT(4)
8991 #define PFPM_WUS_MAG_M BIT(1)
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H A Dice_adminq_cmd.h51 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
183 #define ICE_AQC_FORCE_NO_DROP BIT(0)
349 #define ICE_AQ_VSI_IS_VALID BIT(15)
531 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
855 #define ICE_LG_ACT_EGRESS BIT(14)
856 #define ICE_LG_ACT_INGRESS BIT(15)
857 #define ICE_LG_ACT_PRUNET BIT(16)
1194 #define ICE_AQC_GET_PHY_RQM BIT(0)
1451 #define ICE_AQ_LINK_FAULT BIT(1)
1462 #define ICE_AQ_FEC_EN BIT(3)
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/f-stack/dpdk/drivers/common/dpaax/caamflib/
H A Ddesc.h90 #define HDR_EXT BIT(24)
95 #define HDR_RIF BIT(25)
100 #define HDR_RSLS BIT(25)
106 #define HDR_DNR BIT(24)
112 #define HDR_ONE BIT(23)
113 #define HDR_ZRO BIT(15)
216 #define KEY_TK BIT(15)
406 #define CIRQ_ADI BIT(1)
407 #define CIRQ_DDI BIT(2)
409 #define CIRQ_KDI BIT(4)
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/f-stack/dpdk/drivers/raw/ifpga/base/
H A Dopae_intel_max10.h20 #define MAX10_FLAGS_NO_I2C2 BIT(0)
26 #define MAX10_FLAGS_SECURE BIT(6)
101 #define FPGA_RP_LOAD BIT(3)
102 #define NIOS2_PRERESET BIT(4)
103 #define NIOS2_HANG BIT(5)
104 #define RSU_ENABLE BIT(6)
105 #define NIOS2_RESET BIT(7)
110 #define COUNTDOWN_START BIT(18)
116 #define DT_AVAIL BIT(0)
119 #define RSU_REQUEST BIT(0)
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H A Dopae_i2c.h11 #define ALTERA_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
12 #define ALTERA_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
13 #define ALTERA_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
18 #define ALTERA_I2C_CTRL_BSPEED BIT(1) /* Bus Speed */
19 #define ALTERA_I2C_CTRL_EN BIT(0) /* Enable Core */
27 #define ALTERA_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW */
28 #define ALTERA_I2C_ISR_ARB BIT(3) /* ARB LOST */
29 #define ALTERA_I2C_ISR_NACK BIT(2) /* NACK DET */
30 #define ALTERA_I2C_ISR_RXRDY BIT(1) /* RX Ready */
31 #define ALTERA_I2C_ISR_TXRDY BIT(0) /* TX Ready */
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/f-stack/dpdk/drivers/common/dpaax/caamflib/rta/
H A Dsec_run_time_asm.h268 #define AIDF BIT(9)
280 #define DCOPY BIT(30)
294 #define SOP BIT(21)
295 #define RST BIT(22)
296 #define EWS BIT(23)
318 #define SC BIT(25)
320 #define DSV BIT(7)
322 #define FTD BIT(8)
359 #define SIZE_WORD BIT(17)
360 #define SIZE_BYTE BIT(18)
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/f-stack/dpdk/drivers/net/hns3/
H A Dhns3_intr.c31 { .int_msk = BIT(0),
34 { .int_msk = BIT(1),
37 { .int_msk = BIT(2),
40 { .int_msk = BIT(3),
43 { .int_msk = BIT(4),
46 { .int_msk = BIT(5),
49 { .int_msk = BIT(6),
52 { .int_msk = BIT(7),
55 { .int_msk = BIT(8),
58 { .int_msk = BIT(9),
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/f-stack/dpdk/drivers/net/mvpp2/
H A Dmrvl_ethdev.h88 F_DMAC = BIT(0),
89 F_SMAC = BIT(1),
90 F_TYPE = BIT(2),
92 F_VLAN_PRI = BIT(3),
93 F_VLAN_ID = BIT(4),
96 F_IP4_TOS = BIT(6),
97 F_IP4_SIP = BIT(7),
98 F_IP4_DIP = BIT(8),
99 F_IP4_PROTO = BIT(9),
102 F_IP6_SIP = BIT(11),
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/f-stack/dpdk/drivers/net/enetc/base/
H A Denetc_hw.h9 #define BIT(x) ((uint64_t)1 << ((x))) macro
23 #define ENETC_SIMR_EN BIT(31)
45 #define ENETC_RBMR_EN BIT(31)
55 #define ENETC_RBIER_RXTIE BIT(0)
77 #define ENETC_TBMR_EN BIT(31)
82 #define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18))
95 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
96 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
106 #define ENETC_PM0_CRC BIT(6)
109 #define L3_CKSUM BIT(0)
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/f-stack/dpdk/drivers/net/atlantic/
H A Datl_common.h41 #define AQ_NIC_RATE_10G BIT(0)
42 #define AQ_NIC_RATE_5G BIT(1)
43 #define AQ_NIC_RATE_5G5R BIT(2)
44 #define AQ_NIC_RATE_2G5 BIT(3)
45 #define AQ_NIC_RATE_1G BIT(4)
46 #define AQ_NIC_RATE_100M BIT(5)
48 #define AQ_NIC_RATE_EEE_10G BIT(6)
49 #define AQ_NIC_RATE_EEE_5G BIT(7)
50 #define AQ_NIC_RATE_EEE_2G5 BIT(8)
51 #define AQ_NIC_RATE_EEE_1G BIT(9)
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/f-stack/dpdk/drivers/net/bnxt/
H A Dbnxt.h333 #define BNXT_PTP_MSG_SYNC BIT(0)
619 #define BNXT_FLAG_REGISTERED BIT(0)
620 #define BNXT_FLAG_VF BIT(1)
621 #define BNXT_FLAG_PORT_STATS BIT(2)
622 #define BNXT_FLAG_JUMBO BIT(3)
623 #define BNXT_FLAG_SHORT_CMD BIT(4)
633 #define BNXT_FLAG_STINGRAY BIT(14)
634 #define BNXT_FLAG_FW_RESET BIT(15)
639 #define BNXT_FLAG_NEW_RM BIT(20)
640 #define BNXT_FLAG_NPAR_PF BIT(21)
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/f-stack/dpdk/drivers/net/atlantic/hw_atl/
H A Dhw_atl_b0_internal.h49 #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)
50 #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)
51 #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)
52 #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)
53 #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)
54 #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)
55 #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)
57 #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)
58 #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)
H A Dhw_atl_utils_fw2x.c142 BIT(CAPS_LO_SMBUS_WRITE) | in aq_fw2x_set_link_speed()
143 BIT(CAPS_LO_MACSEC)) & reg_val); in aq_fw2x_set_link_speed()
153 *mpi_state |= BIT(CAPS_HI_PAUSE); in aq_fw2x_set_mpi_flow_control()
155 *mpi_state &= ~BIT(CAPS_HI_PAUSE); in aq_fw2x_set_mpi_flow_control()
170 mpi_state &= ~BIT(CAPS_HI_LINK_DROP); in aq_fw2x_set_state()
174 mpi_state |= BIT(CAPS_HI_LINK_DROP); in aq_fw2x_set_state()
281 BIT(CAPS_HI_STATISTICS)), in aq_fw2x_update_stats()
563 BIT(CAPS_LO_SMBUS_READ)) == (mpi_opts & BIT(CAPS_LO_SMBUS_READ)), in aq_fw2x_get_eeprom()
677 BIT(CAPS_LO_SMBUS_WRITE)) == (mpi_opts & BIT(CAPS_LO_SMBUS_WRITE)), in aq_fw2x_set_eeprom()
727 mpi_opts ^= BIT(CAPS_LO_MACSEC); in aq_fw2x_send_macsec_request()
[all …]
/f-stack/freebsd/contrib/ena-com/ena_defs/
H A Dena_eth_io_defs.h310 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
312 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
314 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
316 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
321 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
323 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
370 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
373 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
375 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
377 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
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/f-stack/dpdk/drivers/net/ena/base/ena_defs/
H A Dena_eth_io_defs.h282 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
284 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
286 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
288 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
293 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
295 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
342 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
345 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
347 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
349 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
[all …]
/f-stack/freebsd/contrib/ena-com/
H A Dena_eth_io_defs.h314 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
316 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
318 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
320 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
323 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
325 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
372 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
375 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
377 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
379 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
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/f-stack/dpdk/drivers/net/pfe/base/
H A Dcbus.h33 #define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */
34 #define PE_MEM_ACCESS_IMEM BIT(15)
35 #define PE_MEM_ACCESS_DMEM BIT(16)
40 (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
59 #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
64 #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)

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