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Searched refs:BAR0 (Results 1 – 4 of 4) sorted by relevance

/f-stack/dpdk/drivers/net/bnx2x/
H A Dbnx2x.h1432 #define BAR0 0 macro
1441 rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_write8()
1454 rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_write16()
1469 rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_write32()
1477 val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset); in bnx2x_reg_read8()
1495 val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_read16()
1513 val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset)); in bnx2x_reg_read32()
1520 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
H A Dbnx2x_ethdev.c665 sc->bar[BAR0].base_addr = (void *)pci_dev->mem_resource[0].addr; in bnx2x_common_dev_init()
672 assert(sc->bar[BAR0].base_addr); in bnx2x_common_dev_init()
H A Dbnx2x.c11939 sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
/f-stack/freebsd/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a.dtsi888 /* PF0-6 BAR0 - non-prefetchable memory */
892 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
896 /* PF1: VF0-1 BAR0 - non-prefetchable memory */