Home
last modified time | relevance | path

Searched refs:AR_PHY_TIMING5 (Results 1 – 5 of 5) sorted by relevance

/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_spectral.c159 val = OS_REG_READ(ah, AR_PHY_TIMING5); in ar9300_disable_strong_signal()
161 OS_REG_WRITE(ah, AR_PHY_TIMING5, val); in ar9300_disable_strong_signal()
163 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_RSSI_THR1A, 0x7f); in ar9300_disable_strong_signal()
H A Dar9300_ani.c339 OS_REG_READ_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1); in ar9300_ani_init_defaults()
678 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, value); in ar9300_ani_control()
H A Dar9300phy.h47 #define AR_PHY_TIMING5 AR_CHAN_OFFSET(BB_timing_control_5) macro
H A Dar9300_reset.c3848 …OS_REG_WRITE(ah, AR_PHY_TIMING5, OS_REG_READ(ah,AR_PHY_TIMING5) & ~AR_PHY_TIMING5_CYCPWR_THR1_ENAB… in ar9300_init_cal_internal()
H A Dar9300_misc.c1461 reg = OS_REG_READ(ah, AR_PHY_TIMING5); in ar9300_dma_reg_dump()