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Searched refs:AR_PHY_MC_GAIN_CTRL (Results 1 – 4 of 4) sorted by relevance

/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_eeprom.c1743 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_ctrl_apply()
1768 OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9300_ant_ctrl_apply()
1778 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9300_ant_ctrl_apply()
1798 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_ctrl_apply()
1808 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9300_ant_ctrl_apply()
1816 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_ctrl_apply()
1831 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); in ar9300_ant_ctrl_apply()
1843 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); in ar9300_ant_ctrl_apply()
H A Dar9300_reset.c6484 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6494 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6509 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6519 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6527 OS_REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, ANT_DIV_ENABLE); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6528 …OS_REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, (1 << MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT)); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6533 OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, ANT_DIV_ENABLE); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6534 …OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, (1 << MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT)); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6539 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6549 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
H A Dar9300_attach.c4042 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_div_comb_get_config()
4075 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_div_comb_set_config()
4096 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); in ar9300_ant_div_comb_set_config()
H A Dar9300phy.h349 #define AR_PHY_MC_GAIN_CTRL AR_AGC_OFFSET(BB_multichain_gain_ctrl) macro