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Searched refs:AR_HOSTIF_REG (Results 1 – 9 of 9) sorted by relevance

/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_gpio.c89 addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3); in ar9300_gpio_cfg_output_mux()
91 addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2); in ar9300_gpio_cfg_output_mux()
93 addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1); in ar9300_gpio_cfg_output_mux()
230 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), in ar9300_gpio_cfg_output()
332 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), in ar9300_gpio_cfg_output_led_off()
364 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), in ar9300_gpio_cfg_input()
383 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT), in ar9300_gpio_set()
403 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN), in ar9300_gpio_get()
439 regs[1] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK); in ar9300_gpio_set_intr()
443 regs[0] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE); in ar9300_gpio_set_intr()
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H A Dar9300_interrupts.c42 host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)); in ar9300_is_interrupt_pending()
47 host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)); in ar9300_is_interrupt_pending()
161 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)) & in ar9300_get_pending_interrupts()
436 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); in ar9300_get_pending_interrupts()
437 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0); in ar9300_get_pending_interrupts()
480 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI), in ar9300_get_pending_interrupts()
525 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), 0);
528 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE), 0);
700 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI),
722 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE),
[all …]
H A Dar9300_attach.c4104 AR_HOSTIF_REG(ah, AR_RC) = in ar9300_init_hostif_offsets()
4106 AR_HOSTIF_REG(ah, AR_WA) = in ar9300_init_hostif_offsets()
4120 AR_HOSTIF_REG(ah, AR_SREV) = in ar9300_init_hostif_offsets()
4166 AR_HOSTIF_REG(ah, AR_SPARE) = in ar9300_init_hostif_offsets()
4174 AR_HOSTIF_REG(ah, AR_OBS) = in ar9300_init_hostif_offsets()
4182 AR_HOSTIF_REG(ah, AR_MISC) = in ar9300_init_hostif_offsets()
4219 AR_HOSTIF_REG(ah, AR_RC) = in ar9340_init_hostif_offsets()
4221 AR_HOSTIF_REG(ah, AR_WA) = in ar9340_init_hostif_offsets()
4227 AR_HOSTIF_REG(ah, AR_SREV) = in ar9340_init_hostif_offsets()
4273 AR_HOSTIF_REG(ah, AR_OBS) = in ar9340_init_hostif_offsets()
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H A Dar9300_power.c585 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), in ar9300_set_power_mode_sleep()
643 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), in ar9300_set_power_mode_network_sleep()
1099 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); in ar9300_wow_enable()
1110 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); in ar9300_wow_enable()
1112 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); in ar9300_wow_enable()
1346 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); in ar9300_wow_enable()
1352 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); in ar9300_wow_enable()
1510 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); in ar9300_wow_wake_up()
1560 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)); in ar9300_wow_set_gpio_reset_low()
1562 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), val); in ar9300_wow_set_gpio_reset_low()
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H A Dar9300_reset.c1700 tmp_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)); in ar9300_set_reset()
1704 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); in ar9300_set_reset()
1709 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); in ar9300_set_reset()
1875 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0); in ar9300_set_reset()
4244 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), sync_en_def); in ar9300_init_interrupt_masks()
4247 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK), 0); in ar9300_init_interrupt_masks()
4250 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK), 0); in ar9300_init_interrupt_masks()
4252 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK), 0); in ar9300_init_interrupt_masks()
5075 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8); in ar9300_reset()
5078 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8); in ar9300_reset()
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H A Dar9300_misc.c189 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), in ar9300_enable_rf_kill()
194 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), in ar9300_enable_rf_kill()
205 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), in ar9300_enable_rf_kill()
207 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), in ar9300_enable_rf_kill()
432 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); in ar9300_detect_card_present()
2649 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), in ar9300_bt_coex_enable()
2683 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), in ar9300_init_bt_coex()
2687 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), in ar9300_init_bt_coex()
2708 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), in ar9300_init_bt_coex()
2712 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), in ar9300_init_bt_coex()
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H A Dar9300_mci.c536 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE); in ar9300_mci_observation_set_up()
548 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 0x4b); in ar9300_mci_observation_set_up()
H A Dar9300_eeprom.c232 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA), in ar9300_eeprom_read_word()
239 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA)), AR_EEPROM_STATUS_DATA_VAL); in ar9300_eeprom_read_word()
H A Dar9300reg.h727 #define AR_HOSTIF_REG(_ah, _reg) (AH9300(_ah)->ah_hostifregs._reg) macro