Searched refs:AR934X_SRIF_DDR_DPLL2_REG (Results 1 – 2 of 2) sorted by relevance
223 #define AR934X_SRIF_DDR_DPLL2_REG (AR934X_SRIF_BASE + 0x244) macro
132 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG); in ar934x_chip_detect_sys_frequency()