Searched refs:AR934X_SRIF_DDR_DPLL1_REG (Results 1 – 2 of 2) sorted by relevance
222 #define AR934X_SRIF_DDR_DPLL1_REG (AR934X_SRIF_BASE + 0x240) macro
136 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG); in ar934x_chip_detect_sys_frequency()