Searched refs:AR934X_SRIF_CPU_DPLL1_REG (Results 1 – 2 of 2) sorted by relevance
218 #define AR934X_SRIF_CPU_DPLL1_REG (AR934X_SRIF_BASE + 0x1c0) macro
109 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG); in ar934x_chip_detect_sys_frequency()