Searched refs:AR934X_PLL_DDR_CONFIG_REG (Results 1 – 2 of 2) sorted by relevance
67 #define AR934X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04) macro
144 pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG); in ar934x_chip_detect_sys_frequency()