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Searched refs:AR71XX_APB_BASE (Results 1 – 8 of 8) sorted by relevance

/f-stack/freebsd/mips/atheros/
H A Dqca955xreg.h57 #define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
58 #define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
64 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
191 #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
208 #define QCA955X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
209 #define QCA955X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
210 #define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
211 #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
212 #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
214 #define QCA955X_DDR_REG_FLUSH_SRC1 (AR71XX_APB_BASE + 0xb0)
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H A Dar933xreg.h41 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
44 #define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
61 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
66 #define AR933X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x7c)
67 #define AR933X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0x80)
68 #define AR933X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0x84)
69 #define AR933X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0x88)
H A Dqca953xreg.h48 #define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
50 #define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
54 #define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
58 #define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
59 #define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
140 #define QCA953X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
141 #define QCA953X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
142 #define QCA953X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
143 #define QCA953X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
144 #define QCA953X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
H A Dar934xreg.h34 #define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
36 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
40 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
60 #define AR934X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
61 #define AR934X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
62 #define AR934X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
63 #define AR934X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
64 #define AR934X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
H A Dar91xxreg.h63 #define AR91XX_DDR_CTRLBASE (AR71XX_APB_BASE + 0)
71 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
H A Dar724xreg.h75 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
80 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
H A Dapb.c126 AR71XX_APB_BASE, in apb_attach()
127 AR71XX_APB_BASE + AR71XX_APB_SIZE - 1) != 0) in apb_attach()
H A Dar71xxreg.h73 #define AR71XX_APB_BASE 0x18000000 macro