Searched refs:AR5315_SYSREG_BASE (Results 1 – 4 of 4) sorted by relevance
121 const uint32_t pllc = ATH_READ_REG(AR5315_SYSREG_BASE + in ar5315_chip_detect_sys_frequency()151 const uint32_t cpu_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE + in ar5315_chip_detect_sys_frequency()166 ATH_WRITE_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_COLDRESET, in ar5315_chip_device_reset()173 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR0, in ar5315_chip_device_start()175 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR1); in ar5315_chip_device_start()176 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_WDOG_CTL, in ar5315_chip_device_start()181 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL, in ar5315_chip_device_start()182 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL) | in ar5315_chip_device_start()192 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_GPIO_INT, 0); in ar5315_chip_device_start()195 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL)); in ar5315_chip_device_start()[all …]
102 reg = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_mask_irq()104 ATH_WRITE_REG(AR5315_SYSREG_BASE in apb_mask_irq()121 reg = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_unmask_irq()123 ATH_WRITE_REG(AR5315_SYSREG_BASE + in apb_unmask_irq()254 ATH_WRITE_REG(AR5315_SYSREG_BASE in apb_attach()489 reg = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_filter()498 ATH_WRITE_REG(AR5315_SYSREG_BASE + in apb_filter()542 intr = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_filter()695 reg = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_pic_post_filter()697 ATH_WRITE_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_MISC_INTSTAT, in apb_pic_post_filter()
55 #define AR5315_SYSREG_BASE 0x11000000 macro221 #define AR5315_APB_BASE AR5315_SYSREG_BASE
109 ver = ATH_READ_REG(AR5315_SYSREG_BASE + in ar5315_detect_sys_type()