Searched refs:AR5312_SYSREG_BASE (Results 1 – 4 of 4) sorted by relevance
90 const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL); in ar5312_chip_detect_sys_frequency()114 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL, in ar5312_chip_device_reset()139 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBPERR); in ar5312_chip_device_start()140 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBDMAE); in ar5312_chip_device_start()142 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_ENABLE, 0); in ar5312_chip_device_start()144 ATH_WRITE_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE, in ar5312_chip_device_start()145 ATH_READ_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE) | in ar5312_chip_device_start()155 reg = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL); in ar5312_chip_device_stopped()
107 reg = ATH_READ_REG(AR5312_SYSREG_BASE + in apb_mask_irq()109 ATH_WRITE_REG(AR5312_SYSREG_BASE in apb_mask_irq()126 reg = ATH_READ_REG(AR5312_SYSREG_BASE + in apb_unmask_irq()128 ATH_WRITE_REG(AR5312_SYSREG_BASE + in apb_unmask_irq()257 ATH_WRITE_REG(AR5312_SYSREG_BASE in apb_attach()492 reg = ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()502 ATH_WRITE_REG(AR5312_SYSREG_BASE + in apb_filter()510 ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()512 ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()553 ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()[all …]
60 #define AR5312_SYSREG_BASE 0x1C003000 macro185 #define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE)186 #define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v)
133 ver = ATH_READ_REG(AR5312_SYSREG_BASE + in ar5315_detect_sys_type()