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/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dvexpress-v2p-ca15_a7.dts275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
349 /* A7 CPU core voltage */
352 regulator-name = "A7 Vcore";
356 label = "A7 Vcore";
367 /* Total current for the three A7 cores */
370 label = "A7 Icore";
388 /* Total power for the three A7 cores */
391 label = "A7 Pcore";
402 /* Total energy for the three A7 cores */
[all …]
H A Dexynos5422-cpus.dtsi8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
16 * from the LITTLE: Cortex-A7.
H A Dexynos5422-odroidxu3.dts44 /* A7 cluster: VDD_KFC */
H A Dexynos5422-odroidxu3-lite.dts35 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
H A Dexynos5420-cpus.dtsi17 * from the LITTLE: Cortex-A7.
H A Dkirkwood-openblocks_a7.dts3 * Device Tree file for OpenBlocks A7 board
H A Daspeed-bmc-opp-zaius.dts472 pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
482 /*A0-A7*/ "","cfam-reset","","","","","","",
H A Daspeed-bmc-opp-romulus.dts235 /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
H A Daspeed-bmc-opp-nicole.dts219 /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
H A Daspeed-bmc-facebook-tiogapass.dts128 /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","",
H A Daspeed-bmc-opp-witherspoon.dts202 /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dimx7ulp-scg-clock.yaml18 and A7 domain. Except for a few clock sources shared between two
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
26 Note: this binding doc is only for A7 clock domain.
H A Dimx7ulp-pcc-clock.yaml18 and A7 domain. Except for a few clock sources shared between two
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
26 Note: this binding doc is only for A7 clock domain.
H A Dimx7ulp-clock.txt8 and A7 domain. Except for a few clock sources shared between two
14 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
16 Note: this binding doc is only for A7 clock domain.
H A Dbrcm,bcm53573-ilp.txt8 on Broadcom BCM53573 devices using Cortex-A7 CPU.
/f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx7ulp-pinctrl.txt3 i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
7 This binding doc is only for the IOMUXC1 support in A7 Domain and it only
/f-stack/freebsd/contrib/device-tree/Bindings/timer/
H A Dnxp,sysctr-timer.yaml14 which provides a shared time base to Cortex A15, A7, A53, A73,
/f-stack/freebsd/mips/include/
H A Dregnum.h68 #define A7 11 macro
/f-stack/freebsd/contrib/device-tree/src/mips/pic32/
H A Dpic32mzda_sk.dts102 pins = "A6", "D4", "G13", "G12", "G14", "A7", "A0";
/f-stack/app/nginx-1.16.1/conf/
H A Dkoi-win16 A7 BF ; # small Ukrainian yi
H A Dkoi-utf22 A7 D197 ; # small Ukrainian yi
H A Dwin-utf34 A7 C2A7 ; # section sign
/f-stack/app/nginx-1.16.1/contrib/unicode2nginx/
H A Dwin-utf41 A7 C2A7 ; #SECTION SIGN
H A Dkoi-utf42 A7 E29596 ; # BOX DRAWINGS DOWN DOUBLE AND LEFT SINGLE
/f-stack/freebsd/contrib/device-tree/Bindings/arm/
H A Dl2c2x0.yaml22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These

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