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/dpdk/drivers/net/cxgbe/base/
H A Dt4_regs.h64 #define V_QID(x) ((x) << S_QID) argument
68 #define V_DBPRIO(x) ((x) << S_DBPRIO) argument
73 #define V_PIDX(x) ((x) << S_PIDX) argument
77 #define V_DBTYPE(x) ((x) << S_DBTYPE) argument
378 #define V_BUSY(x) ((x) << S_BUSY) argument
397 #define V_BIR(x) ((x) << S_BIR) argument
554 #define V_TOS(x) ((x) << S_TOS) argument
615 #define V_PF(x) ((x) << S_PF) argument
624 #define V_VF(x) ((x) << S_VF) argument
907 #define V_OP(x) ((x) << S_OP) argument
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H A Dt4fw_interface.h80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) argument
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) argument
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) argument
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) argument
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) argument
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) argument
392 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) argument
403 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) argument
409 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) argument
415 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) argument
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H A Dt4_msg.h57 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) argument
59 #define G_TID(x) ((x) & 0xFFFFFF) argument
75 #define V_TID_QID(x) ((x) << S_TID_QID) argument
120 #define V_COOKIE(x) ((x) << S_COOKIE) argument
125 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) argument
128 #define V_DELACK(x) ((x) << S_DELACK) argument
135 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) argument
169 #define V_SACK_EN(x) ((x) << S_SACK_EN) argument
236 #define V_WORD(x) ((x) << S_WORD) argument
240 #define V_QUEUENO(x) ((x) << S_QUEUENO) argument
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H A Dt4_hw.h69 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) argument
74 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) argument
75 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) argument
78 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) argument
83 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) argument
84 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) argument
88 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) argument
93 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) argument
94 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) argument
H A Dt4_tcb.h13 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) argument
22 #define V_TCB_RSS_INFO(x) ((x) << S_TCB_RSS_INFO) argument
28 #define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) argument
34 #define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) argument
39 #define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) argument
/dpdk/lib/eal/ppc/include/
H A Drte_byteorder.h81 #define rte_cpu_to_le_16(x) (x) argument
82 #define rte_cpu_to_le_32(x) (x) argument
83 #define rte_cpu_to_le_64(x) (x) argument
89 #define rte_le_to_cpu_16(x) (x) argument
90 #define rte_le_to_cpu_32(x) (x) argument
91 #define rte_le_to_cpu_64(x) (x) argument
103 #define rte_cpu_to_be_16(x) (x) argument
104 #define rte_cpu_to_be_32(x) (x) argument
105 #define rte_cpu_to_be_64(x) (x) argument
111 #define rte_be_to_cpu_16(x) (x) argument
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/dpdk/lib/eal/arm/include/
H A Drte_byteorder.h42 #define rte_cpu_to_le_16(x) (x) argument
43 #define rte_cpu_to_le_32(x) (x) argument
44 #define rte_cpu_to_le_64(x) (x) argument
50 #define rte_le_to_cpu_16(x) (x) argument
51 #define rte_le_to_cpu_32(x) (x) argument
52 #define rte_le_to_cpu_64(x) (x) argument
64 #define rte_cpu_to_be_16(x) (x) argument
65 #define rte_cpu_to_be_32(x) (x) argument
66 #define rte_cpu_to_be_64(x) (x) argument
72 #define rte_be_to_cpu_16(x) (x) argument
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/dpdk/lib/eal/x86/include/
H A Drte_byteorder.h45 : [x] "+r" (x) in rte_arch_bswap32()
73 #define rte_cpu_to_le_16(x) (x) argument
74 #define rte_cpu_to_le_32(x) (x) argument
75 #define rte_cpu_to_le_64(x) (x) argument
77 #define rte_cpu_to_be_16(x) rte_bswap16(x) argument
78 #define rte_cpu_to_be_32(x) rte_bswap32(x) argument
79 #define rte_cpu_to_be_64(x) rte_bswap64(x) argument
81 #define rte_le_to_cpu_16(x) (x) argument
82 #define rte_le_to_cpu_32(x) (x) argument
83 #define rte_le_to_cpu_64(x) (x) argument
[all …]
/dpdk/drivers/event/dlb2/pf/base/
H A Ddlb2_regs.h192 (0x100000c + (x) * 0x10)
201 (0x20 + (x) * 0x4)
854 (0x18002024 + (x) * 0x40)
861 (0x18002020 + (x) * 0x40)
868 (0x1800201c + (x) * 0x40)
875 (0x18002018 + (x) * 0x40)
882 (0x18002014 + (x) * 0x40)
3765 (0xa4000074 + (x) * 4)
3767 (0x94000074 + (x) * 4)
4161 (0x1000 + (x) * 0x4)
[all …]
/dpdk/drivers/common/dpaax/
H A Dcompat.h62 #define __stringify_1(x) #x argument
63 #define __stringify(x) __stringify_1(x) argument
96 #define DPAA_BUG_ON(x) RTE_ASSERT(x) argument
216 #define lower_32_bits(x) ((u32)(x)) argument
284 #define cpu_to_be48(x) (x) argument
285 #define be48_to_cpu(x) (x) argument
287 #define cpu_to_be40(x) (x) argument
288 #define be40_to_cpu(x) (x) argument
290 #define cpu_to_be24(x) (x) argument
291 #define be24_to_cpu(x) (x) argument
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/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_vf.h28 #define IXGBE_VTEITR(x) (0x00820 + (4 * (x))) argument
29 #define IXGBE_VTIVAR(x) (0x00120 + (4 * (x))) argument
31 #define IXGBE_VTRSCINT(x) (0x00180 + (4 * (x))) argument
33 #define IXGBE_VFRDBAL(x) (0x01000 + (0x40 * (x))) argument
34 #define IXGBE_VFRDBAH(x) (0x01004 + (0x40 * (x))) argument
35 #define IXGBE_VFRDLEN(x) (0x01008 + (0x40 * (x))) argument
36 #define IXGBE_VFRDH(x) (0x01010 + (0x40 * (x))) argument
37 #define IXGBE_VFRDT(x) (0x01018 + (0x40 * (x))) argument
45 #define IXGBE_VFTDH(x) (0x02010 + (0x40 * (x))) argument
60 #define IXGBE_VFRSSRK(x) (0x3100 + ((x) * 4)) argument
[all …]
/dpdk/drivers/common/dpaax/caamflib/
H A Dcompat.h71 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) argument
75 #define ALIGN(x, a) (((x) + ((__typeof__(x))(a) - 1)) & \ argument
76 ~((__typeof__(x))(a) - 1))
101 #define swab16(x) rte_bswap16(x) argument
102 #define swab32(x) rte_bswap32(x) argument
103 #define swab64(x) rte_bswap64(x) argument
107 #define cpu_to_be32(x) (x) argument
109 #define cpu_to_be32(x) swab32(x) argument
115 #define cpu_to_le32(x) swab32(x) argument
117 #define cpu_to_le32(x) (x) argument
/dpdk/lib/eal/include/generic/
H A Drte_byteorder.h124 rte_constant_bswap16(uint16_t x) in rte_constant_bswap16() argument
126 return (uint16_t)RTE_STATIC_BSWAP16(x); in rte_constant_bswap16()
136 rte_constant_bswap32(uint32_t x) in rte_constant_bswap32() argument
138 return (uint32_t)RTE_STATIC_BSWAP32(x); in rte_constant_bswap32()
148 rte_constant_bswap64(uint64_t x) in rte_constant_bswap64() argument
150 return (uint64_t)RTE_STATIC_BSWAP64(x); in rte_constant_bswap64()
164 static uint32_t rte_bswap32(uint32_t x);
169 static uint64_t rte_bswap64(uint64_t x);
238 #define rte_bswap16(x) __builtin_bswap16(x) argument
241 #define rte_bswap32(x) __builtin_bswap32(x) argument
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H A Drte_rwlock.h63 int32_t x; in rte_rwlock_read_lock() local
67 x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED); in rte_rwlock_read_lock()
69 if (x < 0) { in rte_rwlock_read_lock()
73 success = __atomic_compare_exchange_n(&rwl->cnt, &x, x + 1, 1, in rte_rwlock_read_lock()
95 int32_t x; in rte_rwlock_read_trylock() local
101 if (x < 0) in rte_rwlock_read_trylock()
103 success = __atomic_compare_exchange_n(&rwl->cnt, &x, x + 1, 1, in rte_rwlock_read_trylock()
139 int32_t x; in rte_rwlock_write_trylock() local
142 if (x != 0 || __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1, in rte_rwlock_write_trylock()
158 int32_t x; in rte_rwlock_write_lock() local
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/dpdk/lib/eal/include/
H A Drte_common.h101 #define RTE_PRAGMA(x) _Pragma(#x) argument
138 #define RTE_SET_USED(x) (void)(x) argument
492 x |= x >> 1; in rte_combine32ms1b()
493 x |= x >> 2; in rte_combine32ms1b()
494 x |= x >> 4; in rte_combine32ms1b()
495 x |= x >> 8; in rte_combine32ms1b()
496 x |= x >> 16; in rte_combine32ms1b()
556 x = rte_combine32ms1b(x); in rte_align32pow2()
573 x = rte_combine32ms1b(x); in rte_align32prevpow2()
575 return x - (x >> 1); in rte_align32prevpow2()
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/dpdk/drivers/net/qede/base/
H A Decore_utils.h14 #define PTR_LO(x) ((u32)(((osal_uintptr_t)(x)) & 0xffffffff)) argument
15 #define PTR_HI(x) ((u32)((((osal_uintptr_t)(x)) >> 16) >> 16)) argument
17 #define DMA_LO(x) ((u32)(((dma_addr_t)(x)) & 0xffffffff)) argument
18 #define DMA_HI(x) ((u32)(((dma_addr_t)(x)) >> 32)) argument
20 #define DMA_LO_LE(x) OSAL_CPU_TO_LE32(DMA_LO(x)) argument
21 #define DMA_HI_LE(x) OSAL_CPU_TO_LE32(DMA_HI(x)) argument
26 #define DMA_REGPAIR_LE(x, val) (x).hi = DMA_HI_LE((val)); \ argument
27 (x).lo = DMA_LO_LE((val))
/dpdk/drivers/dma/dpaa/
H A Ddpaa_qdma.h33 #define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x)) argument
34 #define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x)) argument
35 #define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x)) argument
36 #define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x)) argument
37 #define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x)) argument
38 #define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x)) argument
39 #define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x)) argument
40 #define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x)) argument
58 #define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20) argument
59 #define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16) argument
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/dpdk/drivers/net/ena/base/
H A Dena_plat_dpdk.h65 #define ENA_MSLEEP(x) rte_delay_us_sleep(x * 1000) argument
66 #define ENA_USLEEP(x) rte_delay_us_sleep(x) argument
67 #define ENA_UDELAY(x) rte_delay_us_block(x) argument
69 #define ENA_TOUCH(x) ((void)(x)) argument
108 #define U64_C(x) x ## ULL argument
267 #define msleep(x) rte_delay_us(x * 1000) argument
268 #define udelay(x) rte_delay_us(x) argument
278 #define prefetch(x) rte_prefetch0(x) argument
279 #define prefetchw(x) rte_prefetch0_write(x) argument
281 #define lower_32_bits(x) ((uint32_t)(x)) argument
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/dpdk/drivers/net/cxgbe/
H A Dcxgbe_compat.h31 #define dev_err(x, fmt, ...) \ argument
51 #define ASSERT(x) do {\ argument
52 if (!(x)) \
55 #define BUG_ON(x) ASSERT(!(x)) argument
58 #define WARN_ON(x) do { \ argument
59 int ret = !!(x); \
75 #define CXGBE_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) argument
176 #define DELAY(x) rte_delay_us(x) argument
177 #define udelay(x) DELAY(x) argument
178 #define msleep(x) DELAY(1000 * (x)) argument
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/dpdk/lib/sched/
H A Drte_sched_common.h19 rte_min_pos_4_u16(uint16_t *x)
23 pos0 = (x[0] <= x[1])? 0 : 1;
24 pos1 = (x[2] <= x[3])? 2 : 3;
26 return (x[pos0] <= x[pos1])? pos0 : pos1;
33 rte_min_pos_4_u16(uint16_t *x) in rte_min_pos_4_u16() argument
38 if (x[1] <= x[0]) pos0 = 1; in rte_min_pos_4_u16()
39 if (x[3] <= x[2]) pos1 = 3; in rte_min_pos_4_u16()
40 if (x[pos1] <= x[pos0]) pos0 = pos1; in rte_min_pos_4_u16()
H A Drte_approx.c98 aa = matches(p_b + x * p_a, q_b + x * q_a, alpha_num, d_num, denum); in find_best_rational_approximation()
99 bb = matches(p_b + (x-1) * p_a, q_b + (x - 1) * q_a, alpha_num, d_num, denum); in find_best_rational_approximation()
109 new_q_b = q_b + x * q_a; in find_best_rational_approximation()
122 aa = matches(p_b + x * p_a, q_b + x * q_a, alpha_num, d_num, denum); in find_best_rational_approximation()
123 bb = matches(p_b + (x - 1) * p_a, q_b + (x - 1) * q_a, alpha_num, d_num, denum); in find_best_rational_approximation()
132 new_p_b = p_b + x * p_a; in find_best_rational_approximation()
133 new_q_b = q_b + x * q_a; in find_best_rational_approximation()
249 aa = matches_64(p_b + x * p_a, q_b + x * q_a, alpha_num, d_num, denum); in find_best_rational_approximation_64()
250 bb = matches_64(p_b + (x-1) * p_a, q_b + (x - 1) * q_a, in find_best_rational_approximation_64()
275 aa = matches_64(p_b + x * p_a, q_b + x * q_a, alpha_num, d_num, denum); in find_best_rational_approximation_64()
[all …]
/dpdk/drivers/net/bnxt/hcapi/cfa/
H A Dhcapi_cfa_defs.h25 #define __CFA_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) argument
26 #define CFA_ALIGN(x, a) __CFA_ALIGN_MASK((x), (a) - 1) argument
27 #define CFA_ALIGN_256(x) CFA_ALIGN(x, 256) argument
28 #define CFA_ALIGN_128(x) CFA_ALIGN(x, 128) argument
29 #define CFA_ALIGN_32(x) CFA_ALIGN(x, 32) argument
31 #define NUM_WORDS_ALIGN_32BIT(x) (CFA_ALIGN_32(x) / CFA_BITS_PER_WORD) argument
32 #define NUM_WORDS_ALIGN_128BIT(x) (CFA_ALIGN_128(x) / CFA_BITS_PER_WORD) argument
33 #define NUM_WORDS_ALIGN_256BIT(x) (CFA_ALIGN_256(x) / CFA_BITS_PER_WORD) argument
62 #define crc32(x, y) crc32i(~0, x, y) argument
/dpdk/examples/ipsec-secgw/test/
H A Ddata_rxtx.sh51 x=`basename $0`.${sz}
52 dd if=/dev/urandom of=${x} bs=${sz} count=1
53 scp ${x} [${dst}]:${x}
54 scp [${dst}]:${x} ${x}.copy1
55 diff -u ${x} ${x}.copy1
57 rm -f ${x} ${x}.copy1
58 ssh ${REMOTE_HOST} rm -f ${x}
/dpdk/drivers/net/thunderx/base/
H A Dnicvf_plat.h24 #define nicvf_delay_us(x) rte_delay_us(x) argument
33 #define nicvf_min(x, y) RTE_MIN(x, y) argument
34 #define nicvf_log2_u32(x) rte_log2_u32(x) argument
38 #define nicvf_cpu_to_be_64(x) rte_cpu_to_be_64(x) argument
39 #define nicvf_be_to_cpu_64(x) rte_be_to_cpu_64(x) argument
50 #define ether_addr_copy(x, y) memcpy(y, x, RTE_ETHER_ADDR_LEN) argument
/dpdk/lib/table/
H A Drte_lru.h48 uint64_t x, pos, x0, x1, x2, mask; \
50 x = bucket->lru_list; \
53 if ((x >> 48) == ((uint64_t) mru_val)) \
56 if (((x >> 32) & 0xFFFFLLU) == ((uint64_t) mru_val)) \
59 if (((x >> 16) & 0xFFFFLLU) == ((uint64_t) mru_val)) \
62 if ((x & 0xFFFFLLU) == ((uint64_t) mru_val)) \
68 x0 = x & (~mask); \
69 x1 = (x >> 16) & mask; \
70 x2 = (x << (48 - pos)) & (0xFFFFLLU << 48); \
71 x = x0 | x1 | x2; \
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