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Searched refs:width (Results 1 – 25 of 68) sorted by relevance

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/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_cpp_pcie_ops.c141 switch (width) { in nfp_compute_bar()
399 } width; member
424 priv->width.write > 0 && priv->width.read != priv->width.write) in nfp6000_area_init()
428 priv->width.bar = priv->width.read; in nfp6000_area_init()
430 priv->width.bar = priv->width.write; in nfp6000_area_init()
513 int width; in nfp6000_area_read() local
524 width = priv->width.read; in nfp6000_area_read()
526 if (width <= 0) in nfp6000_area_read()
581 int width; in nfp6000_area_write() local
592 width = priv->width.write; in nfp6000_area_write()
[all …]
/dpdk/drivers/net/ice/base/
H A Dice_acl_ctrl.c105 if (width > 1) { in ice_acl_tbl_calc_end_idx()
324 width = ROUND_UP(params->width, (u16)ICE_AQC_ACL_KEY_WIDTH_BYTES); in ice_acl_create_tbl()
341 tbl_alloc.width = width; in ice_acl_create_tbl()
384 tbl->info.width = width; in ice_acl_create_tbl()
431 u16 width, r_entries, row; in ice_acl_alloc_partition() local
436 width = DIVIDE_AND_ROUND_UP(req->width, ICE_AQC_ACL_KEY_WIDTH_BYTES); in ice_acl_alloc_partition()
470 if (width == 1) { in ice_acl_alloc_partition()
525 width); in ice_acl_alloc_partition()
529 row = dir > 0 ? row + width : row - width; in ice_acl_alloc_partition()
542 if (off >= width) in ice_acl_alloc_partition()
[all …]
H A Dice_acl.h12 u16 width; /* Select/match bytes */ member
83 u16 width; /* Number of select/mask bytes */ member
98 u16 width; member
H A Dice_common.c4440 mask = BIT(ce_info->width) - 1; in ice_write_word()
4488 if (ce_info->width < 32) in ice_write_dword()
4489 mask = BIT(ce_info->width) - 1; in ice_write_dword()
4539 if (ce_info->width < 64) in ice_write_qword()
4540 mask = BIT_ULL(ce_info->width) - 1; in ice_write_qword()
4579 for (f = 0; ce_info[f].width; f++) { in ice_set_ctx()
4712 mask = BIT(ce_info->width) - 1; in ice_read_word()
4760 if (ce_info->width < 32) in ice_read_dword()
4761 mask = BIT(ce_info->width) - 1; in ice_read_dword()
4811 if (ce_info->width < 64) in ice_read_qword()
[all …]
/dpdk/drivers/net/fm10k/base/
H A Dfm10k_common.c25 hw->bus_caps.width = fm10k_bus_width_pcie_x1; in fm10k_get_bus_info_generic()
28 hw->bus_caps.width = fm10k_bus_width_pcie_x2; in fm10k_get_bus_info_generic()
31 hw->bus_caps.width = fm10k_bus_width_pcie_x4; in fm10k_get_bus_info_generic()
34 hw->bus_caps.width = fm10k_bus_width_pcie_x8; in fm10k_get_bus_info_generic()
37 hw->bus_caps.width = fm10k_bus_width_unknown; in fm10k_get_bus_info_generic()
79 hw->bus.width = fm10k_bus_width_pcie_x1; in fm10k_get_bus_info_generic()
82 hw->bus.width = fm10k_bus_width_pcie_x2; in fm10k_get_bus_info_generic()
85 hw->bus.width = fm10k_bus_width_pcie_x4; in fm10k_get_bus_info_generic()
88 hw->bus.width = fm10k_bus_width_pcie_x8; in fm10k_get_bus_info_generic()
91 hw->bus.width = fm10k_bus_width_unknown; in fm10k_get_bus_info_generic()
/dpdk/doc/guides/prog_guide/img/
H A Drib_pic.svg1 <svg width="1280.324" height="563.481" viewBox="0 0 960.246 422.611" xml:space="preserve" color-int…
3 …width:.25}.st2{fill:#bfbfbf}.st3{fill:#00b0f0}.st4{marker-end:url(#mrkr4-16);stroke:#000;stroke-li…
6 …isible" style="fill:#000;fill-opacity:1;stroke:#000;stroke-opacity:1;stroke-width:.28409090909091">
7 …<use xlink:href="#lend4" transform="scale(-3.52)" id="use14" x="0" y="0" width="100%" height="100%…
10 …<use xlink:href="#lend4" transform="scale(-3.52)" id="use17" x="0" y="0" width="100%" height="100%…
13 …<use xlink:href="#lend4" transform="scale(-3.52)" id="use20" x="0" y="0" width="100%" height="100%…
15 …" style="fill:#eb94e0;fill-opacity:1;stroke:#eb94e0;stroke-opacity:1;stroke-width:.28409090909091">
16 …<use xlink:href="#lend4" transform="scale(-3.52)" id="use23" x="0" y="0" width="100%" height="100%…
111 …ker-end:url(#mrkr4-107);stroke:#00b0f0;stroke-linecap:round;stroke-linejoin:round;stroke-width:1"/>
H A Drib_internals.svg1 <svg width="1740.327" height="670.034" viewBox="0 0 1305.249 502.526" xml:space="preserve" color-in…
3 …width:.75}.st2,.st3{fill:#fee599;stroke:#c7c8c8;stroke-width:.25}.st3{fill:#bfbfbf}.st4{marker-end…
6 …isible" style="fill:#000;fill-opacity:1;stroke:#000;stroke-opacity:1;stroke-width:.28409090909091">
7 …<use xlink:href="#lend4" transform="scale(-3.52)" id="use745" x="0" y="0" width="100%" height="100…
H A Ddir_24_8_alg.svg1 <svg width="945.881" height="658.889" viewBox="0 0 709.411 494.167" xml:space="preserve" color-inte…
3 …width:.749999}.st2{fill:#3c63ac;font-family:Calibri;font-size:1.16666em}.st3{marker-end:url(#mrkr4…
30 …" style="fill:#4672c4;fill-opacity:1;stroke:#4672c4;stroke-opacity:1;stroke-width:.28409061414099">
31 …<use xlink:href="#lend4" transform="scale(-3.52)" id="use15" x="0" y="0" width="100%" height="100%…
/dpdk/drivers/net/i40e/base/
H A Di40e_lan_hmc.c672 u16 width; member
789 mask = BIT(ce_info->width) - 1; in i40e_write_word()
838 if (ce_info->width < 32) in i40e_write_dword()
839 mask = BIT(ce_info->width) - 1; in i40e_write_dword()
890 if (ce_info->width < 64) in i40e_write_qword()
891 mask = BIT_ULL(ce_info->width) - 1; in i40e_write_qword()
971 mask = BIT(ce_info->width) - 1; in i40e_read_word()
1020 if (ce_info->width < 32) in i40e_read_dword()
1021 mask = BIT(ce_info->width) - 1; in i40e_read_dword()
1073 if (ce_info->width < 64) in i40e_read_qword()
[all …]
/dpdk/drivers/net/mlx5/
H A Dmlx5_flow_flex.c118 uint32_t pos, uint32_t width, uint32_t shift) in mlx5_flex_get_bitfield() argument
124 MLX5_ASSERT(width <= sizeof(uint32_t) * CHAR_BIT && width); in mlx5_flex_get_bitfield()
125 MLX5_ASSERT(width + shift <= sizeof(uint32_t) * CHAR_BIT); in mlx5_flex_get_bitfield()
131 vbits = RTE_MIN(vbits, width); in mlx5_flex_get_bitfield()
133 while (vbits < width && pos < item->length) { in mlx5_flex_get_bitfield()
241 uint32_t def = (RTE_BIT64(map->width) - 1) << map->shift; in mlx5_flex_flow_translate_item()
246 pos += map->width; in mlx5_flex_flow_translate_item()
251 MLX5_ASSERT(map->width); in mlx5_flex_flow_translate_item()
263 pos += map->width; in mlx5_flex_flow_translate_item()
774 trans->width = part; in mlx5_flex_map_sample()
[all …]
H A Dmlx5_flow_dv.c1484 width = 0; in mlx5_flow_field_id_to_modify_info()
1489 if (!width) in mlx5_flow_field_id_to_modify_info()
1514 width = 0; in mlx5_flow_field_id_to_modify_info()
1519 if (!width) in mlx5_flow_field_id_to_modify_info()
1597 width = 0; in mlx5_flow_field_id_to_modify_info()
1602 if (!width) in mlx5_flow_field_id_to_modify_info()
1613 width = 0; in mlx5_flow_field_id_to_modify_info()
1618 if (!width) in mlx5_flow_field_id_to_modify_info()
1629 width = 0; in mlx5_flow_field_id_to_modify_info()
1634 if (!width) in mlx5_flow_field_id_to_modify_info()
[all …]
/dpdk/lib/ethdev/
H A Drte_dev_info.h21 uint32_t width; /**< Size of device register */ member
/dpdk/app/test-crypto-perf/
H A Ddpdk-graph-crypto-perf.py56 height=1400, width=2400)
70 width=2400)
89 buffer, height=1400, width=2400)
/dpdk/doc/guides/rel_notes/
H A Drelease_22_07.rst15 Variable and config names should be quoted as fixed width text:
129 Use fixed width quotes for ``function_names`` or ``struct_names``.
145 Use fixed width quotes for ``function_names`` or ``struct_names``.
/dpdk/doc/guides/
H A Dconf.py166 fill='.', align='<', width=max_header_len-3)
169 fill=' ', align='<', width=max_header_len)
/dpdk/drivers/common/sfc_efx/base/
H A Defx_mac.c672 unsigned int width; in efx_mac_stats_mask_add_range() local
693 width = high - low + 1; in efx_mac_stats_mask_add_range()
695 (width == EFX_MAC_STATS_MASK_BITS_PER_PAGE) ? in efx_mac_stats_mask_add_range()
696 (~0ULL) : (((1ULL << width) - 1) << (low - el_min)); in efx_mac_stats_mask_add_range()
/dpdk/lib/bpf/
H A Dbpf_jit_arm64.c50 const unsigned int width = is64 ? 64 : 32; in check_immr_imms() local
52 if (immr >= width || imms >= width) in check_immr_imms()
550 const unsigned int width = is64 ? 64 : 32; in emit_lsl() local
553 immr = (width - imm) & (width - 1); in emit_lsl()
554 imms = width - 1 - imm; in emit_lsl()
/dpdk/drivers/net/ena/base/
H A Dena_com.c1605 u32 width; in ena_com_get_dma_width() local
1612 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> in ena_com_get_dma_width()
1615 ena_trc_dbg(ena_dev, "ENA dma width: %d\n", width); in ena_com_get_dma_width()
1617 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { in ena_com_get_dma_width()
1618 ena_trc_err(ena_dev, "DMA width illegal value: %d\n", width); in ena_com_get_dma_width()
1622 ena_dev->dma_addr_bits = width; in ena_com_get_dma_width()
1624 return width; in ena_com_get_dma_width()
/dpdk/drivers/net/ice/
H A Dice_acl_filter.c114 params.width = ICE_AQC_ACL_KEY_WIDTH_BYTES * 6; in ice_acl_setup()
116 params.width = ICE_AQC_ACL_KEY_WIDTH_BYTES * 3; in ice_acl_setup()
126 err = ice_acl_create_scen(hw, params.width, params.depth, in ice_acl_setup()
/dpdk/drivers/net/igc/base/
H A Digc_mac.c184 bus->width = (status & IGC_STATUS_BUS64) in igc_get_bus_info_pci_generic()
216 bus->width = igc_bus_width_unknown; in igc_get_bus_info_pcie_generic()
231 bus->width = (enum igc_bus_width)((pcie_link_status & in igc_get_bus_info_pcie_generic()
/dpdk/drivers/net/qede/
H A Dqede_regs.c93 regs->width = sizeof(uint32_t); in qede_get_regs()
/dpdk/examples/ethtool/lib/
H A Drte_ethtool.c100 return reg_info.length * reg_info.width; in rte_ethtool_get_regs_len()
/dpdk/drivers/net/e1000/base/
H A De1000_mac.c186 bus->width = (status & E1000_STATUS_BUS64) in e1000_get_bus_info_pci_generic()
218 bus->width = e1000_bus_width_unknown; in e1000_get_bus_info_pcie_generic()
233 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000_get_bus_info_pcie_generic()
H A De1000_82542.c151 hw->bus.width = e1000_bus_width_unknown; in e1000_get_bus_info_82542()
/dpdk/doc/guides/contributing/
H A Ddocumentation.rst339 * Inline text that is required to be rendered with a fixed width font should be enclosed in backquo…
342 * Fixed width, literal blocks of texts should be indented at least 3 spaces and prefixed with ``::`…
344 Here is some fixed width text::
623 * Doxygen supports Markdown style syntax such as bold, italics, fixed width text and lists.

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