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Searched refs:val (Results 1 – 25 of 512) sorted by relevance

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/dpdk/lib/eal/arm/include/
H A Drte_io_64.h22 uint8_t val; in rte_read8_relaxed() local
26 : [val] "=r" (val) in rte_read8_relaxed()
28 return val; in rte_read8_relaxed()
38 : [val] "=r" (val) in rte_read16_relaxed()
40 return val; in rte_read16_relaxed()
50 : [val] "=r" (val) in rte_read32_relaxed()
62 : [val] "=r" (val) in rte_read64_relaxed()
73 : [val] "r" (val), [addr] "r" (addr)); in rte_write8_relaxed()
82 : [val] "r" (val), [addr] "r" (addr)); in rte_write16_relaxed()
91 : [val] "r" (val), [addr] "r" (addr)); in rte_write32_relaxed()
[all …]
/dpdk/drivers/net/cnxk/
H A Dcnxk_lookup.c74 uint16_t val; in nix_create_non_tunnel_ptype_array() local
82 val = RTE_PTYPE_UNKNOWN; in nix_create_non_tunnel_ptype_array()
107 val |= RTE_PTYPE_L3_IPV4; in nix_create_non_tunnel_ptype_array()
125 val |= RTE_PTYPE_L4_TCP; in nix_create_non_tunnel_ptype_array()
128 val |= RTE_PTYPE_L4_UDP; in nix_create_non_tunnel_ptype_array()
174 ptype[idx] = val; in nix_create_non_tunnel_ptype_array()
183 uint16_t val; in nix_create_tunnel_ptype_array() local
193 val = RTE_PTYPE_UNKNOWN; in nix_create_tunnel_ptype_array()
224 ptype[idx] = val; in nix_create_tunnel_ptype_array()
232 uint32_t val, *ol_flags; in nix_create_rx_ol_flags_array() local
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H A Dcnxk_ethdev_devargs.c26 uint32_t val; in parse_outb_nb_desc() local
39 uint32_t val; in parse_outb_nb_crypto_qs() local
43 if (val < 1 || val > 64) in parse_outb_nb_crypto_qs()
55 uint32_t val; in parse_ipsec_in_spi_range() local
60 val = 0; in parse_ipsec_in_spi_range()
71 uint32_t val; in parse_ipsec_out_max_sa() local
76 val = 0; in parse_ipsec_out_max_sa()
87 uint16_t val; in parse_flow_max_priority() local
92 if (val < 1 || val > 32) in parse_flow_max_priority()
104 uint16_t val; in parse_flow_prealloc_size() local
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/dpdk/examples/fips_validation/
H A Dfips_validation_tdes.c128 if (val->val) { in parse_tdes_uint8_hex_str()
129 memcpy(tmp_key, val->val, val->len); in parse_tdes_uint8_hex_str()
134 if (!val->val) in parse_tdes_uint8_hex_str()
147 memcpy(val->val + 8, val->val, 8); in parse_tdes_uint8_hex_str()
148 memcpy(val->val + 16, val->val, 8); in parse_tdes_uint8_hex_str()
159 memcpy(val->val + 16, val->val, 8); in parse_tdes_uint8_hex_str()
184 rte_free(val->val); in parse_tdes_uint8_hex_str()
212 tmp_val.val = val->val; in writeback_tdes_hex_str()
214 tmp_val.val = val->val + 8; in writeback_tdes_hex_str()
216 tmp_val.val = val->val + 16; in writeback_tdes_hex_str()
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H A Dmain.c1309 memcpy(vec.pt.val, val.val, in fips_mct_tdes_test()
1314 memcpy(vec.iv.val, val.val, in fips_mct_tdes_test()
1320 memcpy(vec.ct.val, val.val, in fips_mct_tdes_test()
1325 memcpy(vec.ct.val, val.val, in fips_mct_tdes_test()
1334 memcpy(vec.pt.val, val.val, in fips_mct_tdes_test()
1337 memcpy(vec.iv.val, val.val, in fips_mct_tdes_test()
1344 memcpy(vec.ct.val, val.val, in fips_mct_tdes_test()
1349 memcpy(vec.ct.val, val.val, in fips_mct_tdes_test()
1386 val_key.val[k] ^= val.val[k]; in fips_mct_tdes_test()
1391 val_key.val[k] ^= val.val[k]; in fips_mct_tdes_test()
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H A Dfips_validation.c476 rte_free(val->val); in parse_uint8_known_len_hex_str()
477 val->val = NULL; in parse_uint8_known_len_hex_str()
488 val->val = tmp_val.val; in parse_uint8_known_len_hex_str()
497 val->val = rte_zmalloc(NULL, val->len, 0); in parse_uint8_known_len_hex_str()
498 if (!val->val) { in parse_uint8_known_len_hex_str()
504 memcpy(val->val, tmp_val.val, val->len); in parse_uint8_known_len_hex_str()
519 if (val->val) { in parse_uint8_hex_str()
520 rte_free(val->val); in parse_uint8_hex_str()
521 val->val = NULL; in parse_uint8_hex_str()
525 if (!val->val) in parse_uint8_hex_str()
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H A Dfips_validation_ccm.c67 val->len = vec.pt.len; in parse_dvpt_ct_hex_str()
77 rte_free(val->val); in parse_dvpt_ct_hex_str()
78 memset(val, 0, sizeof(*val)); in parse_dvpt_ct_hex_str()
88 uint32_t len = val->len, j; in parse_uint8_ccm_aad_str()
93 val->val = rte_zmalloc(NULL, len + 18, 0); in parse_uint8_ccm_aad_str()
94 if (!val->val) in parse_uint8_ccm_aad_str()
100 if (parser_read_uint8_hex(&val->val[j + 18], byte) < 0) { in parse_uint8_ccm_aad_str()
101 rte_free(val->val); in parse_uint8_ccm_aad_str()
102 memset(val, 0, sizeof(*val)); in parse_uint8_ccm_aad_str()
221 tmp_val.val = val->val; in parse_test_ccm_writeback()
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H A Dfips_validation_gcm.c49 __rte_unused struct fips_val *val) in parser_read_gcm_pt_len() argument
71 __rte_unused struct fips_val *val) in parse_gcm_aad_str() argument
88 if (!vec.iv.val) { in parse_gcm_pt_ct_str()
90 if (!vec.iv.val) in parse_gcm_pt_ct_str()
96 vec.iv.val[i] = (uint8_t)random; in parse_gcm_pt_ct_str()
150 tmp_val.val = vec.iv.val; in parse_test_gcm_writeback()
154 rte_free(vec.iv.val); in parse_test_gcm_writeback()
155 vec.iv.val = NULL; in parse_test_gcm_writeback()
161 tmp_val.val = val->val; in parse_test_gcm_writeback()
170 tmp_val.val = val->val + vec.pt.len; in parse_test_gcm_writeback()
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/dpdk/drivers/net/bnxt/tf_core/
H A Dtfp.h204 #define tfp_cpu_to_le_16(val) rte_cpu_to_le_16(val) argument
205 #define tfp_le_to_cpu_16(val) rte_le_to_cpu_16(val) argument
206 #define tfp_cpu_to_le_32(val) rte_cpu_to_le_32(val) argument
207 #define tfp_le_to_cpu_32(val) rte_le_to_cpu_32(val) argument
208 #define tfp_cpu_to_le_64(val) rte_cpu_to_le_64(val) argument
209 #define tfp_le_to_cpu_64(val) rte_le_to_cpu_64(val) argument
210 #define tfp_cpu_to_be_16(val) rte_cpu_to_be_16(val) argument
211 #define tfp_be_to_cpu_16(val) rte_be_to_cpu_16(val) argument
216 #define tfp_bswap_16(val) rte_bswap16(val) argument
217 #define tfp_bswap_32(val) rte_bswap32(val) argument
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/dpdk/drivers/net/ena/base/ena_defs/
H A Dena_eth_io_defs.h398 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK; in set_ena_eth_io_tx_desc_length()
468 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; in set_ena_eth_io_tx_desc_l3_proto_idx()
558 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; in set_ena_eth_io_tx_desc_addr_hi()
578 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; in set_ena_eth_io_tx_meta_desc_req_id_lo()
678 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; in set_ena_eth_io_tx_meta_desc_req_id_hi()
688 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; in set_ena_eth_io_tx_meta_desc_l3_hdr_len()
728 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; in set_ena_eth_io_tx_cdesc_phase()
738 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; in set_ena_eth_io_rx_desc_phase()
778 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; in set_ena_eth_io_rx_cdesc_base_l3_proto_idx()
898 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; in set_ena_eth_io_intr_reg_rx_intr_delay()
[all …]
H A Dena_admin_defs.h1218 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; in set_ena_admin_aq_common_desc_command_id()
1228 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; in set_ena_admin_aq_common_desc_phase()
1268 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; in set_ena_admin_acq_common_desc_command_id()
1278 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; in set_ena_admin_acq_common_desc_phase()
1348 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; in set_ena_admin_get_set_feature_common_desc_select()
1358 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; in set_ena_admin_get_feature_link_desc_autoneg()
1378 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; in set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4()
1558 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK; in set_ena_admin_host_info_major()
1598 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK; in set_ena_admin_host_info_function()
1678 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; in set_ena_admin_aenq_common_desc_phase()
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/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_api_cmd.h18 #define HINIC_API_CMD_CELL_CTRL_SET(val, member) \ argument
22 #define HINIC_API_CMD_CELL_CTRL_CLEAR(val, member) \ argument
44 #define HINIC_API_CMD_DESC_SET(val, member) \ argument
48 #define HINIC_API_CMD_DESC_CLEAR(val, member) \ argument
107 #define HINIC_API_CMD_RESP_HEADER_VALID(val) \ argument
115 #define HINIC_API_CMD_RESP_HEAD_ERR(val) \ argument
124 #define HINIC_API_CMD_RESP_HEAD_CHAIN_ID(val) \ argument
153 #define HINIC_API_CMD_STATUS_CHAIN_ID(val) \ argument
157 #define HINIC_API_CMD_STATUS_CONS_IDX(val) \ argument
158 ((val) & HINIC_API_CMD_STATUS_CONS_IDX_MASK)
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H A Dhinic_pmd_cmd.h297 #define HINIC_RSS_TYPE_SET(val, member) \ argument
300 #define HINIC_RSS_TYPE_GET(val, member) \ argument
332 #define HINIC_AF0_GET(val, member) \ argument
351 #define HINIC_AF1_GET(val, member) \ argument
357 #define HINIC_AF2_GET(val, member) \ argument
365 #define HINIC_AF4_GET(val, member) \ argument
368 #define HINIC_AF4_SET(val, member) \ argument
371 #define HINIC_AF4_CLEAR(val, member) \ argument
378 #define HINIC_AF5_SET(val, member) \ argument
381 #define HINIC_AF5_GET(val, member) \ argument
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/dpdk/app/test-eventdev/
H A Dparser.c82 uint64_t val; in parser_read_uint64() local
114 *value = val; in parser_read_uint64()
122 int32_t val; in parser_read_int32() local
132 *value = val; in parser_read_int32()
140 uint64_t val; in parser_read_uint64_hex() local
152 *value = val; in parser_read_uint64_hex()
168 *value = val; in parser_read_uint32()
184 *value = val; in parser_read_uint32_hex()
200 *value = val; in parser_read_uint16()
216 *value = val; in parser_read_uint16_hex()
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/dpdk/drivers/net/softnic/
H A Dparser.c83 int32_t val; in softnic_parser_read_int32() local
93 *value = val; in softnic_parser_read_int32()
101 uint64_t val; in softnic_parser_read_uint64() local
133 *value = val; in softnic_parser_read_uint64()
141 uint64_t val; in softnic_parser_read_uint64_hex() local
153 *value = val; in softnic_parser_read_uint64_hex()
169 *value = val; in softnic_parser_read_uint32()
185 *value = val; in softnic_parser_read_uint32_hex()
201 *value = val; in softnic_parser_read_uint16()
506 s = val; in softnic_parse_cpu_core()
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/dpdk/examples/ip_pipeline/
H A Dparser.c84 uint64_t val; in parser_read_uint64() local
116 *value = val; in parser_read_uint64()
124 uint64_t val; in parser_read_uint64_hex() local
136 *value = val; in parser_read_uint64_hex()
152 *value = val; in parser_read_uint32()
168 *value = val; in parser_read_uint32_hex()
184 *value = val; in parser_read_uint16()
200 *value = val; in parser_read_uint16_hex()
216 *value = val; in parser_read_uint8()
489 s = val; in parse_cpu_core()
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/dpdk/drivers/common/qat/qat_adf/
H A Dicp_qat_fw_la.h166 #define ICP_QAT_FW_LA_PROTO_SET(flags, val) \ argument
167 QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \
170 #define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \ argument
174 #define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \ argument
186 #define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \ argument
187 QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
340 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
351 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
361 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
372 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
[all …]
H A Dicp_qat_fw.h9 #define QAT_FIELD_SET(flags, val, bitpos, mask) \ argument
11 (((val) & (mask)) << (bitpos))) ; }
131 icp_qat_fw_comn_req_hdr_t.service_type = val
137 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
153 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
163 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ argument
164 QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
195 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ argument
199 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ argument
215 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
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/dpdk/lib/eal/include/
H A Drte_trace_point.h118 #define rte_trace_point_emit_u64(val) argument
120 #define rte_trace_point_emit_i64(val) argument
122 #define rte_trace_point_emit_u32(val) argument
124 #define rte_trace_point_emit_i32(val) argument
126 #define rte_trace_point_emit_u16(val) argument
130 #define rte_trace_point_emit_u8(val) argument
132 #define rte_trace_point_emit_i8(val) argument
333 uint64_t val; in __rte_trace_point_emit_ev_header() local
336 val = rte_get_tsc_cycles() & in __rte_trace_point_emit_ev_header()
342 *(uint64_t *)mem = val; in __rte_trace_point_emit_ev_header()
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/dpdk/drivers/raw/ifpga/base/osdep_raw/
H A Dosdep_generic.h15 uint8_t val; in opae_readb() local
17 val = *(const volatile uint8_t *)addr; in opae_readb()
19 return val; in opae_readb()
24 uint16_t val; in opae_readw() local
26 val = *(const volatile uint16_t *)addr; in opae_readw()
28 return val; in opae_readw()
33 uint32_t val; in opae_readl() local
35 val = *(const volatile uint32_t *)addr; in opae_readl()
37 return val; in opae_readl()
42 uint64_t val; in opae_readq() local
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/dpdk/drivers/vdpa/ifc/base/
H A Difcvf_osdep.h23 #define IFCVF_WRITE_REG8(val, reg) rte_write8((val), (reg)) argument
25 #define IFCVF_WRITE_REG16(val, reg) rte_write16((val), (reg)) argument
27 #define IFCVF_WRITE_REG32(val, reg) rte_write32((val), (reg)) argument
31 #define PCI_READ_CONFIG_BYTE(dev, val, where) \ argument
32 rte_pci_read_config(dev, val, 1, where)
34 #define PCI_READ_CONFIG_DWORD(dev, val, where) \ argument
35 rte_pci_read_config(dev, val, 4, where)
47 PCI_READ_CONFIG_RANGE(PCI_DEV *dev, uint32_t *val, int size, int where) in PCI_READ_CONFIG_RANGE() argument
49 return rte_pci_read_config(dev, val, size, where); in PCI_READ_CONFIG_RANGE()
/dpdk/lib/telemetry/
H A Dtelemetry_json.h96 uint64_t val) in rte_tel_json_add_array_u64() argument
128 const char *name, uint64_t val) in rte_tel_json_add_obj_u64() argument
133 val); in rte_tel_json_add_obj_u64()
136 name, val); in rte_tel_json_add_obj_u64()
146 const char *name, int val) in rte_tel_json_add_obj_int() argument
151 val); in rte_tel_json_add_obj_int()
154 name, val); in rte_tel_json_add_obj_int()
164 const char *name, const char *val) in rte_tel_json_add_obj_str() argument
171 name, val); in rte_tel_json_add_obj_str()
181 const char *name, const char *val) in rte_tel_json_add_obj_json() argument
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/dpdk/drivers/net/enetc/base/
H A Denetc_hw.h100 #define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff) argument
101 #define ENETC_PVCFGR_SET_RXBDR(val) (((val) & 0xff) << 16) argument
113 #define ENETC_SET_TX_MTU(val) ((val) << 16) argument
114 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) argument
164 #define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg)) argument
166 #define enetc_wr(hw, off, val) enetc_wr_reg((size_t)(hw)->reg + (off), val) argument
169 #define enetc_port_wr(hw, off, val) \ argument
174 #define enetc_global_wr(hw, off, val) \ argument
184 #define enetc_txbdr_wr(hw, n, off, val) \ argument
185 enetc_bdr_wr(hw, TX, n, off, val)
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/dpdk/drivers/raw/ifpga/base/
H A Difpga_fme_error.c15 *val = fme_error0.csr; in fme_err_get_errors()
54 writeq(val, &fme_err->fme_err); in fme_err_set_clear()
69 *val = header.revision; in fme_err_get_revision()
82 *val = pcie0_err.csr; in fme_err_get_pcie0_errors()
99 if (val != pcie0_err.csr) in fme_err_set_pcie0_errors()
119 *val = pcie1_err.csr; in fme_err_get_pcie1_errors()
136 if (val != pcie1_err.csr) in fme_err_set_pcie1_errors()
156 *val = ras_nonfaterr.csr; in fme_err_get_nonfatal_errors()
169 *val = ras_catfaterr.csr; in fme_err_get_catfatal_errors()
198 ras_error_inj.csr = val; in fme_err_set_inject_errors()
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/dpdk/lib/ring/
H A Drte_ring_rts_elem_pvt.h41 if (++nt.val.cnt == h.val.cnt) in __rte_ring_rts_update_tail()
42 nt.val.pos = h.val.pos; in __rte_ring_rts_update_tail()
60 while (h->val.pos - ht->tail.val.pos > max) { in __rte_ring_rts_head_wait()
98 *free_entries = capacity + r->cons.tail - oh.val.pos; in __rte_ring_rts_move_prod_head()
108 nh.val.pos = oh.val.pos + n; in __rte_ring_rts_move_prod_head()
109 nh.val.cnt = oh.val.cnt + 1; in __rte_ring_rts_move_prod_head()
120 *old_head = oh.val.pos; in __rte_ring_rts_move_prod_head()
154 *entries = r->prod.tail - oh.val.pos; in __rte_ring_rts_move_cons_head()
163 nh.val.pos = oh.val.pos + n; in __rte_ring_rts_move_cons_head()
164 nh.val.cnt = oh.val.cnt + 1; in __rte_ring_rts_move_cons_head()
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