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/dpdk/drivers/net/qede/base/
H A Decore_attn_values.h15 u16 num_of_bits; /* number of valid attention bits */
26 u16 num_of_prty_regs; /* Number of parity regs */
51 static const u16 grc_int0_bb_a0_attn_idx[4] = {
63 static const u16 grc_int0_bb_b0_attn_idx[4] = {
75 static const u16 grc_int0_k2_attn_idx[5] = {
97 static const u16 grc_prty1_bb_a0_attn_idx[2] = {
109 static const u16 grc_prty1_bb_b0_attn_idx[2] = {
121 static const u16 grc_prty1_k2_attn_idx[2] = {
194 static const u16 miscs_int0_k2_attn_idx[3] = {
270 static const u16 misc_int0_k2_attn_idx[1] = {
[all …]
H A Decore_iov_api.h90 u16 forced_vlan;
101 u16 rel_vf_id;
107 u16 num_queues;
152 u16 rel_vf_id);
198 u16 rel_vf_id,
256 u16 vf_id,
295 u16 vfid,
310 u16 vfid,
738 u16 rx_coal, u16 tx_coal,
739 u16 vf_id, u16 qid);
[all …]
H A Decore_vfpf_if.h48 u16 type;
49 u16 length;
167 u16 fw_rev;
168 u16 fw_eng;
367 u16 dep1;
368 u16 mtu;
522 u16 qid;
528 u16 qid;
535 u16 coal;
547 u16 mtu;
[all …]
/dpdk/drivers/net/ice/base/
H A Dice_switch.h94 u16 vsi_num;
97 u16 flags;
147 u16 flag;
150 u16 src;
163 u16 tpid;
205 u16 rid;
206 u16 fv_idx;
208 u16 mask;
226 u16 src;
227 u16 flag;
[all …]
H A Dice_acl.h13 u16 depth; /* Number of entries */
33 u16 first_entry;
35 u16 last_entry;
46 u16 id;
80 u16 id;
98 u16 width;
100 u16 depth;
125 u16 first_cntr;
126 u16 last_cntr;
133 ice_acl_create_scen(struct ice_hw *hw, u16 match_width, u16 num_entries,
[all …]
H A Dice_bitops.h178 u16 i; in ice_and_bitmap()
215 u16 i; in ice_or_bitmap()
246 u16 i; in ice_xor_bitmap()
277 u16 i; in ice_andnot_bitmap()
301 static inline u16
302 ice_find_next_bit(const ice_bitmap_t *bitmap, u16 size, u16 offset) in ice_find_next_bit()
304 u16 i, j; in ice_find_next_bit()
394 ice_bitmap_set(ice_bitmap_t *dst, u16 pos, u16 num_bits) in ice_bitmap_set()
396 u16 i; in ice_bitmap_set()
415 u16 bit = 0; in ice_bitmap_hweight()
[all …]
H A Dice_flex_pipe.h29 u8 *prot, u16 *off);
32 u16 *value);
46 u16 buf_size, struct ice_sq_cd *cd);
49 u16 *port);
54 bool ice_tunnel_port_in_use(struct ice_hw *hw, u16 port, u16 *index);
59 bool ice_hw_ptype_ena(struct ice_hw *hw, u16 ptype);
63 ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);
74 ice_add_vsi_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig);
81 u16 dest_vsi_handle, u16 fdir_vsi_handle, int id);
99 ice_set_key(u8 *key, u16 size, u8 *val, u8 *upd, u8 *dc, u8 *nm, u16 off,
[all …]
H A Dice_common.h39 struct ice_rq_event_info *e, u16 *pending);
48 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
50 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
71 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
72 u16 *ret_next_table, u32 *ret_next_index,
150 u16 link_speeds_bitmap);
216 u16 *q_handle, u16 *q_ids, u32 *q_teids,
220 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
221 u16 *max_lanqs);
223 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
[all …]
/dpdk/drivers/net/i40e/base/
H A Di40e_prototype.h212 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
214 u16 *rule_id, u16 *rules_used, u16 *rules_free);
216 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
231 u16 buf_size, u16 *start_seid,
326 u16 vsi_seid, u16 tag, u16 queue_num,
330 u16 tag, u16 *tags_used, u16 *tags_free,
337 u16 etag, u16 *tags_used, u16 *tags_free,
340 u16 old_tag, u16 new_tag, u16 *tags_used,
347 u16 vlan_id, u16 stat_index,
476 u16 data_offset, u16 words_data_size, u16 *data_ptr);
[all …]
H A Dvirtchnl.h215 u16 vsi_id;
272 u16 vsi_id;
296 u16 vsi_id;
328 u16 vsi_id;
359 u16 vsi_id;
385 u16 vsi_id;
386 u16 pad;
440 u16 vsi_id;
479 u16 vsi_id;
492 u16 vsi_id;
[all …]
/dpdk/drivers/net/e1000/base/
H A De1000_nvm.h9 u16 word[2];
10 u16 *pba_block;
15 u16 eep_major;
16 u16 eep_minor;
24 u16 or_major;
25 u16 or_build;
31 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);
34 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);
50 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
52 u16 words, u16 *data);
[all …]
H A De1000_vf.h65 u16 pkt_info;
67 u16 hdr_info;
175 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
192 u16 mta_reg_count;
200 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
201 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
202 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
203 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
223 u16 size;
245 u16 device_id;
[all …]
H A De1000_hw.h631 u16 vlan_id;
751 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
757 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
857 u16 func;
874 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
875 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
876 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
877 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
897 u16 size;
928 u16 value;
[all …]
H A De1000_phy.h9 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
12 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
13 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data);
45 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
61 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
94 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
95 u16 *data);
96 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
97 u16 data);
140 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
[all …]
/dpdk/drivers/net/igc/base/
H A Digc_nvm.h9 u16 word[2];
10 u16 *pba_block;
15 u16 eep_major;
16 u16 eep_minor;
24 u16 or_major;
25 u16 or_build;
31 s32 igc_null_read_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
34 s32 igc_null_write_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
50 s32 igc_read_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
52 u16 words, u16 *data);
[all …]
H A Digc_phy.h9 s32 igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);
12 s32 igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);
13 s32 igc_null_set_page(struct igc_hw *hw, u16 data);
45 s32 igc_set_page_igp(struct igc_hw *hw, u16 page);
61 s32 igc_write_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 data);
96 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
97 u16 *data);
98 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
99 u16 data);
164 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
[all …]
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_niccfg.h268 u16 rsvd1;
289 u16 rsvd;
298 u16 rsvd;
335 u16 rsvd1;
344 u16 rsvd1;
346 u16 rsvd2;
354 u16 rsvd1;
370 u16 rsvd1;
562 u16 rsvd;
807 u16 rsvd;
[all …]
H A Dhinic_pmd_nicio.h177 u16 q_id;
178 u16 owner;
179 u16 sq_depth;
187 u16 irq_id;
189 u16 q_id;
190 u16 rq_depth;
212 u16 max_qps;
213 u16 num_qps;
215 u16 num_sqs;
216 u16 num_rqs;
[all …]
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_mbx.h90 s32 txgbe_read_mbx(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
91 s32 txgbe_write_mbx(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
92 s32 txgbe_read_posted_mbx(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
93 s32 txgbe_write_posted_mbx(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
94 s32 txgbe_check_for_msg(struct txgbe_hw *hw, u16 mbx_id);
95 s32 txgbe_check_for_ack(struct txgbe_hw *hw, u16 mbx_id);
96 s32 txgbe_check_for_rst(struct txgbe_hw *hw, u16 mbx_id);
100 s32 txgbe_read_mbx_pf(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
101 s32 txgbe_write_mbx_pf(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
106 s32 txgbe_read_mbx_vf(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id);
[all …]
/dpdk/drivers/net/ena/base/
H A Dena_com.h61 u16 len;
73 u16 mss;
117 u16 qid;
120 u16 idx;
121 u16 head;
138 u16 idx;
161 u16 qid;
163 u16 idx;
164 u16 tail;
179 u16 head;
[all …]
/dpdk/drivers/common/iavf/
H A Dvirtchnl.h377 u16 vsi_id;
449 u16 vsi_id;
533 u16 vsi_id;
577 u16 vsi_id;
643 u16 pad;
1144 u16 flags;
1373 u16 vf_id;
1374 u16 tpid;
1831 u16 pad;
1942 u16 rsvd;
[all …]
H A Diavf_adminq.h27 u16 count; /* Number of descriptors */
28 u16 rx_buf_len; /* Admin Receive Queue buffer length */
31 u16 next_to_use;
32 u16 next_to_clean;
46 u16 flags_ena;
47 u16 flags_dis;
59 u16 msg_len;
60 u16 buf_len;
70 u16 num_asq_entries; /* send queue depth */
76 u16 api_maj_ver; /* api major version */
[all …]
H A Dvirtchnl_inline_ipsec.h115 u16 block_size;
147 u16 max_sa_num;
165 u16 desc_id;
181 u16 iv_len;
184 u16 digest_len;
190 u16 key_len;
240 u16 spd_ref;
291 u16 sa_domain;
423 u16 spd_ref;
457 u16 udp_port;
[all …]
/dpdk/drivers/bus/dpaa/include/
H A Dfsl_qman.h297 u16 seqnum;
427 u16 mant:8;
428 u16 exp:5;
430 u16 exp:5;
431 u16 mant:8;
471 u16 wq:3;
473 u16 wq:3;
649 u16 hword;
653 u16 TA:8;
1231 u16 ch_id;
[all …]
/dpdk/drivers/net/hinic/
H A Dhinic_pmd_tx.h31 u16 outer_l3_len;
35 u16 inner_l3_len;
49 u16 pi;
50 u16 owner;
51 u16 around;
52 u16 seq_wqebbs;
53 u16 sge_cnt;
54 u16 cpy_mbuf_cnt;
114 u16 port_id;
115 u16 q_id;
[all …]

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