1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _I40E_ADMINQ_CMD_H_ 6 #define _I40E_ADMINQ_CMD_H_ 7 8 /* This header file defines the i40e Admin Queue commands and is shared between 9 * i40e Firmware and Software. 10 * 11 * This file needs to comply with the Linux Kernel coding style. 12 */ 13 14 #define I40E_FW_API_VERSION_MAJOR 0x0001 15 #define I40E_FW_API_VERSION_MINOR_X722 0x000C 16 #define I40E_FW_API_VERSION_MINOR_X710 0x000F 17 18 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 19 I40E_FW_API_VERSION_MINOR_X710 : \ 20 I40E_FW_API_VERSION_MINOR_X722) 21 22 /* API version 1.7 implements additional link and PHY-specific APIs */ 23 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 24 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */ 25 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009 26 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 27 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 28 /* API version 1.10 for X722 devices adds ability to request FEC encoding */ 29 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A 30 31 struct i40e_aq_desc { 32 __le16 flags; 33 __le16 opcode; 34 __le16 datalen; 35 __le16 retval; 36 __le32 cookie_high; 37 __le32 cookie_low; 38 union { 39 struct { 40 __le32 param0; 41 __le32 param1; 42 __le32 param2; 43 __le32 param3; 44 } internal; 45 struct { 46 __le32 param0; 47 __le32 param1; 48 __le32 addr_high; 49 __le32 addr_low; 50 } external; 51 u8 raw[16]; 52 } params; 53 }; 54 55 /* Flags sub-structure 56 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 57 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 58 */ 59 60 /* command flags and offsets*/ 61 #define I40E_AQ_FLAG_DD_SHIFT 0 62 #define I40E_AQ_FLAG_CMP_SHIFT 1 63 #define I40E_AQ_FLAG_ERR_SHIFT 2 64 #define I40E_AQ_FLAG_VFE_SHIFT 3 65 #define I40E_AQ_FLAG_LB_SHIFT 9 66 #define I40E_AQ_FLAG_RD_SHIFT 10 67 #define I40E_AQ_FLAG_VFC_SHIFT 11 68 #define I40E_AQ_FLAG_BUF_SHIFT 12 69 #define I40E_AQ_FLAG_SI_SHIFT 13 70 #define I40E_AQ_FLAG_EI_SHIFT 14 71 #define I40E_AQ_FLAG_FE_SHIFT 15 72 73 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 74 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 75 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 76 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 77 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 78 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 79 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 80 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 81 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 82 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 83 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 84 85 /* error codes */ 86 enum i40e_admin_queue_err { 87 I40E_AQ_RC_OK = 0, /* success */ 88 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 89 I40E_AQ_RC_ENOENT = 2, /* No such element */ 90 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 91 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 92 I40E_AQ_RC_EIO = 5, /* I/O error */ 93 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 94 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 95 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 96 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 97 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 98 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 99 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 100 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 101 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 102 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 103 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 104 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 105 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 106 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 107 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 108 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 109 I40E_AQ_RC_EFBIG = 22, /* File too large */ 110 }; 111 112 /* Admin Queue command opcodes */ 113 enum i40e_admin_queue_opc { 114 /* aq commands */ 115 i40e_aqc_opc_get_version = 0x0001, 116 i40e_aqc_opc_driver_version = 0x0002, 117 i40e_aqc_opc_queue_shutdown = 0x0003, 118 i40e_aqc_opc_set_pf_context = 0x0004, 119 120 /* resource ownership */ 121 i40e_aqc_opc_request_resource = 0x0008, 122 i40e_aqc_opc_release_resource = 0x0009, 123 124 i40e_aqc_opc_list_func_capabilities = 0x000A, 125 i40e_aqc_opc_list_dev_capabilities = 0x000B, 126 127 /* Proxy commands */ 128 i40e_aqc_opc_set_proxy_config = 0x0104, 129 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 130 131 /* LAA */ 132 i40e_aqc_opc_mac_address_read = 0x0107, 133 i40e_aqc_opc_mac_address_write = 0x0108, 134 135 /* PXE */ 136 i40e_aqc_opc_clear_pxe_mode = 0x0110, 137 138 /* WoL commands */ 139 i40e_aqc_opc_set_wol_filter = 0x0120, 140 i40e_aqc_opc_get_wake_reason = 0x0121, 141 i40e_aqc_opc_clear_all_wol_filters = 0x025E, 142 143 /* internal switch commands */ 144 i40e_aqc_opc_get_switch_config = 0x0200, 145 i40e_aqc_opc_add_statistics = 0x0201, 146 i40e_aqc_opc_remove_statistics = 0x0202, 147 i40e_aqc_opc_set_port_parameters = 0x0203, 148 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 149 i40e_aqc_opc_set_switch_config = 0x0205, 150 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 151 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 152 153 i40e_aqc_opc_add_vsi = 0x0210, 154 i40e_aqc_opc_update_vsi_parameters = 0x0211, 155 i40e_aqc_opc_get_vsi_parameters = 0x0212, 156 157 i40e_aqc_opc_add_pv = 0x0220, 158 i40e_aqc_opc_update_pv_parameters = 0x0221, 159 i40e_aqc_opc_get_pv_parameters = 0x0222, 160 161 i40e_aqc_opc_add_veb = 0x0230, 162 i40e_aqc_opc_update_veb_parameters = 0x0231, 163 i40e_aqc_opc_get_veb_parameters = 0x0232, 164 165 i40e_aqc_opc_delete_element = 0x0243, 166 167 i40e_aqc_opc_add_macvlan = 0x0250, 168 i40e_aqc_opc_remove_macvlan = 0x0251, 169 i40e_aqc_opc_add_vlan = 0x0252, 170 i40e_aqc_opc_remove_vlan = 0x0253, 171 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 172 i40e_aqc_opc_add_tag = 0x0255, 173 i40e_aqc_opc_remove_tag = 0x0256, 174 i40e_aqc_opc_add_multicast_etag = 0x0257, 175 i40e_aqc_opc_remove_multicast_etag = 0x0258, 176 i40e_aqc_opc_update_tag = 0x0259, 177 i40e_aqc_opc_add_control_packet_filter = 0x025A, 178 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 179 i40e_aqc_opc_add_cloud_filters = 0x025C, 180 i40e_aqc_opc_remove_cloud_filters = 0x025D, 181 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 182 i40e_aqc_opc_replace_cloud_filters = 0x025F, 183 184 i40e_aqc_opc_add_mirror_rule = 0x0260, 185 i40e_aqc_opc_delete_mirror_rule = 0x0261, 186 187 /* Dynamic Device Personalization */ 188 i40e_aqc_opc_write_personalization_profile = 0x0270, 189 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 190 191 /* DCB commands */ 192 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 193 i40e_aqc_opc_dcb_updated = 0x0302, 194 i40e_aqc_opc_set_dcb_parameters = 0x0303, 195 196 /* TX scheduler */ 197 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 198 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 199 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 200 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 201 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 202 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 203 204 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 205 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 206 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 207 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 208 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 209 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 210 i40e_aqc_opc_query_port_ets_config = 0x0419, 211 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 212 i40e_aqc_opc_suspend_port_tx = 0x041B, 213 i40e_aqc_opc_resume_port_tx = 0x041C, 214 i40e_aqc_opc_configure_partition_bw = 0x041D, 215 /* hmc */ 216 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 217 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 218 219 /* phy commands*/ 220 i40e_aqc_opc_get_phy_abilities = 0x0600, 221 i40e_aqc_opc_set_phy_config = 0x0601, 222 i40e_aqc_opc_set_mac_config = 0x0603, 223 i40e_aqc_opc_set_link_restart_an = 0x0605, 224 i40e_aqc_opc_get_link_status = 0x0607, 225 i40e_aqc_opc_set_phy_int_mask = 0x0613, 226 i40e_aqc_opc_get_local_advt_reg = 0x0614, 227 i40e_aqc_opc_set_local_advt_reg = 0x0615, 228 i40e_aqc_opc_get_partner_advt = 0x0616, 229 i40e_aqc_opc_set_lb_modes = 0x0618, 230 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 231 i40e_aqc_opc_set_phy_debug = 0x0622, 232 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 233 i40e_aqc_opc_run_phy_activity = 0x0626, 234 i40e_aqc_opc_set_phy_register = 0x0628, 235 i40e_aqc_opc_get_phy_register = 0x0629, 236 237 /* NVM commands */ 238 i40e_aqc_opc_nvm_read = 0x0701, 239 i40e_aqc_opc_nvm_erase = 0x0702, 240 i40e_aqc_opc_nvm_update = 0x0703, 241 i40e_aqc_opc_nvm_config_read = 0x0704, 242 i40e_aqc_opc_nvm_config_write = 0x0705, 243 i40e_aqc_opc_nvm_update_in_process = 0x0706, 244 i40e_aqc_opc_rollback_revision_update = 0x0707, 245 i40e_aqc_opc_oem_post_update = 0x0720, 246 i40e_aqc_opc_thermal_sensor = 0x0721, 247 248 /* virtualization commands */ 249 i40e_aqc_opc_send_msg_to_pf = 0x0801, 250 i40e_aqc_opc_send_msg_to_vf = 0x0802, 251 i40e_aqc_opc_send_msg_to_peer = 0x0803, 252 253 /* alternate structure */ 254 i40e_aqc_opc_alternate_write = 0x0900, 255 i40e_aqc_opc_alternate_write_indirect = 0x0901, 256 i40e_aqc_opc_alternate_read = 0x0902, 257 i40e_aqc_opc_alternate_read_indirect = 0x0903, 258 i40e_aqc_opc_alternate_write_done = 0x0904, 259 i40e_aqc_opc_alternate_set_mode = 0x0905, 260 i40e_aqc_opc_alternate_clear_port = 0x0906, 261 262 /* LLDP commands */ 263 i40e_aqc_opc_lldp_get_mib = 0x0A00, 264 i40e_aqc_opc_lldp_update_mib = 0x0A01, 265 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 266 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 267 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 268 i40e_aqc_opc_lldp_stop = 0x0A05, 269 i40e_aqc_opc_lldp_start = 0x0A06, 270 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 271 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 272 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 273 i40e_aqc_opc_lldp_restore = 0x0A0A, 274 275 /* Tunnel commands */ 276 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 277 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 278 i40e_aqc_opc_set_rss_key = 0x0B02, 279 i40e_aqc_opc_set_rss_lut = 0x0B03, 280 i40e_aqc_opc_get_rss_key = 0x0B04, 281 i40e_aqc_opc_get_rss_lut = 0x0B05, 282 283 /* Async Events */ 284 i40e_aqc_opc_event_lan_overflow = 0x1001, 285 286 /* OEM commands */ 287 i40e_aqc_opc_oem_parameter_change = 0xFE00, 288 i40e_aqc_opc_oem_device_status_change = 0xFE01, 289 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 290 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 291 292 /* debug commands */ 293 i40e_aqc_opc_debug_read_reg = 0xFF03, 294 i40e_aqc_opc_debug_write_reg = 0xFF04, 295 i40e_aqc_opc_debug_modify_reg = 0xFF07, 296 i40e_aqc_opc_debug_dump_internals = 0xFF08, 297 }; 298 299 /* command structures and indirect data structures */ 300 301 /* Structure naming conventions: 302 * - no suffix for direct command descriptor structures 303 * - _data for indirect sent data 304 * - _resp for indirect return data (data which is both will use _data) 305 * - _completion for direct return data 306 * - _element_ for repeated elements (may also be _data or _resp) 307 * 308 * Command structures are expected to overlay the params.raw member of the basic 309 * descriptor, and as such cannot exceed 16 bytes in length. 310 */ 311 312 /* This macro is used to generate a compilation error if a structure 313 * is not exactly the correct length. It gives a divide by zero error if the 314 * structure is not of the correct size, otherwise it creates an enum that is 315 * never used. 316 */ 317 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 318 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 319 320 /* This macro is used extensively to ensure that command structures are 16 321 * bytes in length as they have to map to the raw array of that size. 322 */ 323 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 324 325 /* internal (0x00XX) commands */ 326 327 /* Get version (direct 0x0001) */ 328 struct i40e_aqc_get_version { 329 __le32 rom_ver; 330 __le32 fw_build; 331 __le16 fw_major; 332 __le16 fw_minor; 333 __le16 api_major; 334 __le16 api_minor; 335 }; 336 337 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 338 339 /* Send driver version (indirect 0x0002) */ 340 struct i40e_aqc_driver_version { 341 u8 driver_major_ver; 342 u8 driver_minor_ver; 343 u8 driver_build_ver; 344 u8 driver_subbuild_ver; 345 u8 reserved[4]; 346 __le32 address_high; 347 __le32 address_low; 348 }; 349 350 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 351 352 /* Queue Shutdown (direct 0x0003) */ 353 struct i40e_aqc_queue_shutdown { 354 __le32 driver_unloading; 355 #define I40E_AQ_DRIVER_UNLOADING 0x1 356 u8 reserved[12]; 357 }; 358 359 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 360 361 /* Set PF context (0x0004, direct) */ 362 struct i40e_aqc_set_pf_context { 363 u8 pf_id; 364 u8 reserved[15]; 365 }; 366 367 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 368 369 /* Request resource ownership (direct 0x0008) 370 * Release resource ownership (direct 0x0009) 371 */ 372 #define I40E_AQ_RESOURCE_NVM 1 373 #define I40E_AQ_RESOURCE_SDP 2 374 #define I40E_AQ_RESOURCE_ACCESS_READ 1 375 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 376 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 377 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 378 379 struct i40e_aqc_request_resource { 380 __le16 resource_id; 381 __le16 access_type; 382 __le32 timeout; 383 __le32 resource_number; 384 u8 reserved[4]; 385 }; 386 387 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 388 389 /* Get function capabilities (indirect 0x000A) 390 * Get device capabilities (indirect 0x000B) 391 */ 392 struct i40e_aqc_list_capabilites { 393 u8 command_flags; 394 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 395 u8 pf_index; 396 u8 reserved[2]; 397 __le32 count; 398 __le32 addr_high; 399 __le32 addr_low; 400 }; 401 402 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 403 404 struct i40e_aqc_list_capabilities_element_resp { 405 __le16 id; 406 u8 major_rev; 407 u8 minor_rev; 408 __le32 number; 409 __le32 logical_id; 410 __le32 phys_id; 411 u8 reserved[16]; 412 }; 413 414 /* list of caps */ 415 416 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 417 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 418 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 419 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 420 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 421 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 422 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 423 #define I40E_AQ_CAP_ID_SRIOV 0x0012 424 #define I40E_AQ_CAP_ID_VF 0x0013 425 #define I40E_AQ_CAP_ID_VMDQ 0x0014 426 #define I40E_AQ_CAP_ID_8021QBG 0x0015 427 #define I40E_AQ_CAP_ID_8021QBR 0x0016 428 #define I40E_AQ_CAP_ID_VSI 0x0017 429 #define I40E_AQ_CAP_ID_DCB 0x0018 430 #define I40E_AQ_CAP_ID_FCOE 0x0021 431 #define I40E_AQ_CAP_ID_ISCSI 0x0022 432 #define I40E_AQ_CAP_ID_RSS 0x0040 433 #define I40E_AQ_CAP_ID_RXQ 0x0041 434 #define I40E_AQ_CAP_ID_TXQ 0x0042 435 #define I40E_AQ_CAP_ID_MSIX 0x0043 436 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 437 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 438 #define I40E_AQ_CAP_ID_1588 0x0046 439 #define I40E_AQ_CAP_ID_IWARP 0x0051 440 #define I40E_AQ_CAP_ID_LED 0x0061 441 #define I40E_AQ_CAP_ID_SDP 0x0062 442 #define I40E_AQ_CAP_ID_MDIO 0x0063 443 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 444 #define I40E_AQ_CAP_ID_DIS_UNUSED_PORTS 0x0067 445 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 446 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 447 #define I40E_AQ_CAP_ID_CEM 0x00F2 448 449 /* Set CPPM Configuration (direct 0x0103) */ 450 struct i40e_aqc_cppm_configuration { 451 __le16 command_flags; 452 #define I40E_AQ_CPPM_EN_LTRC 0x0800 453 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 454 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 455 #define I40E_AQ_CPPM_EN_HPTC 0x4000 456 #define I40E_AQ_CPPM_EN_DMARC 0x8000 457 __le16 ttlx; 458 __le32 dmacr; 459 __le16 dmcth; 460 u8 hptc; 461 u8 reserved; 462 __le32 pfltrc; 463 }; 464 465 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 466 467 /* Set ARP Proxy command / response (indirect 0x0104) */ 468 struct i40e_aqc_arp_proxy_data { 469 __le16 command_flags; 470 #define I40E_AQ_ARP_INIT_IPV4 0x0800 471 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 472 #define I40E_AQ_ARP_ENA 0x2000 473 #define I40E_AQ_ARP_ADD_IPV4 0x4000 474 #define I40E_AQ_ARP_DEL_IPV4 0x8000 475 __le16 table_id; 476 __le32 enabled_offloads; 477 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 478 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 479 __le32 ip_addr; 480 u8 mac_addr[6]; 481 u8 reserved[2]; 482 }; 483 484 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 485 486 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 487 struct i40e_aqc_ns_proxy_data { 488 __le16 table_idx_mac_addr_0; 489 __le16 table_idx_mac_addr_1; 490 __le16 table_idx_ipv6_0; 491 __le16 table_idx_ipv6_1; 492 __le16 control; 493 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 494 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 495 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 496 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 497 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 498 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 499 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 500 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 501 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 502 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 503 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 504 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 505 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 506 u8 mac_addr_0[6]; 507 u8 mac_addr_1[6]; 508 u8 local_mac_addr[6]; 509 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 510 u8 ipv6_addr_1[16]; 511 }; 512 513 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 514 515 /* Manage LAA Command (0x0106) - obsolete */ 516 struct i40e_aqc_mng_laa { 517 __le16 command_flags; 518 #define I40E_AQ_LAA_FLAG_WR 0x8000 519 u8 reserved[2]; 520 __le32 sal; 521 __le16 sah; 522 u8 reserved2[6]; 523 }; 524 525 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 526 527 /* Manage MAC Address Read Command (indirect 0x0107) */ 528 struct i40e_aqc_mac_address_read { 529 __le16 command_flags; 530 #define I40E_AQC_LAN_ADDR_VALID 0x10 531 #define I40E_AQC_SAN_ADDR_VALID 0x20 532 #define I40E_AQC_PORT_ADDR_VALID 0x40 533 #define I40E_AQC_WOL_ADDR_VALID 0x80 534 #define I40E_AQC_MC_MAG_EN_VALID 0x100 535 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 536 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 537 u8 reserved[6]; 538 __le32 addr_high; 539 __le32 addr_low; 540 }; 541 542 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 543 544 struct i40e_aqc_mac_address_read_data { 545 u8 pf_lan_mac[6]; 546 u8 pf_san_mac[6]; 547 u8 port_mac[6]; 548 u8 pf_wol_mac[6]; 549 }; 550 551 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 552 553 /* Manage MAC Address Write Command (0x0108) */ 554 struct i40e_aqc_mac_address_write { 555 __le16 command_flags; 556 #define I40E_AQC_MC_MAG_EN 0x0100 557 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 558 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 559 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 560 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 561 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 562 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 563 564 __le16 mac_sah; 565 __le32 mac_sal; 566 u8 reserved[8]; 567 }; 568 569 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 570 571 /* PXE commands (0x011x) */ 572 573 /* Clear PXE Command and response (direct 0x0110) */ 574 struct i40e_aqc_clear_pxe { 575 u8 rx_cnt; 576 u8 reserved[15]; 577 }; 578 579 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 580 581 /* Set WoL Filter (0x0120) */ 582 583 struct i40e_aqc_set_wol_filter { 584 __le16 filter_index; 585 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 586 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 587 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 588 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 589 590 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 591 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 592 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 593 __le16 cmd_flags; 594 #define I40E_AQC_SET_WOL_FILTER 0x8000 595 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 596 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 597 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 598 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 599 __le16 valid_flags; 600 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 601 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 602 u8 reserved[2]; 603 __le32 address_high; 604 __le32 address_low; 605 }; 606 607 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 608 609 struct i40e_aqc_set_wol_filter_data { 610 u8 filter[128]; 611 u8 mask[16]; 612 }; 613 614 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 615 616 /* Get Wake Reason (0x0121) */ 617 618 struct i40e_aqc_get_wake_reason_completion { 619 u8 reserved_1[2]; 620 __le16 wake_reason; 621 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 622 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 623 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 624 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 625 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 626 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 627 u8 reserved_2[12]; 628 }; 629 630 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 631 632 /* Switch configuration commands (0x02xx) */ 633 634 /* Used by many indirect commands that only pass an seid and a buffer in the 635 * command 636 */ 637 struct i40e_aqc_switch_seid { 638 __le16 seid; 639 u8 reserved[6]; 640 __le32 addr_high; 641 __le32 addr_low; 642 }; 643 644 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 645 646 /* Get Switch Configuration command (indirect 0x0200) 647 * uses i40e_aqc_switch_seid for the descriptor 648 */ 649 struct i40e_aqc_get_switch_config_header_resp { 650 __le16 num_reported; 651 __le16 num_total; 652 u8 reserved[12]; 653 }; 654 655 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 656 657 struct i40e_aqc_switch_config_element_resp { 658 u8 element_type; 659 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 660 #define I40E_AQ_SW_ELEM_TYPE_PF 2 661 #define I40E_AQ_SW_ELEM_TYPE_VF 3 662 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 663 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 664 #define I40E_AQ_SW_ELEM_TYPE_PV 16 665 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 666 #define I40E_AQ_SW_ELEM_TYPE_PA 18 667 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 668 u8 revision; 669 #define I40E_AQ_SW_ELEM_REV_1 1 670 __le16 seid; 671 __le16 uplink_seid; 672 __le16 downlink_seid; 673 u8 reserved[3]; 674 u8 connection_type; 675 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 676 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 677 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 678 __le16 scheduler_id; 679 __le16 element_info; 680 }; 681 682 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 683 684 /* Get Switch Configuration (indirect 0x0200) 685 * an array of elements are returned in the response buffer 686 * the first in the array is the header, remainder are elements 687 */ 688 struct i40e_aqc_get_switch_config_resp { 689 struct i40e_aqc_get_switch_config_header_resp header; 690 struct i40e_aqc_switch_config_element_resp element[1]; 691 }; 692 693 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 694 695 /* Add Statistics (direct 0x0201) 696 * Remove Statistics (direct 0x0202) 697 */ 698 struct i40e_aqc_add_remove_statistics { 699 __le16 seid; 700 __le16 vlan; 701 __le16 stat_index; 702 u8 reserved[10]; 703 }; 704 705 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 706 707 /* Set Port Parameters command (direct 0x0203) */ 708 struct i40e_aqc_set_port_parameters { 709 __le16 command_flags; 710 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 711 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 712 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 713 __le16 bad_frame_vsi; 714 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 715 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 716 __le16 default_seid; /* reserved for command */ 717 u8 reserved[10]; 718 }; 719 720 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 721 722 /* Get Switch Resource Allocation (indirect 0x0204) */ 723 struct i40e_aqc_get_switch_resource_alloc { 724 u8 num_entries; /* reserved for command */ 725 u8 reserved[7]; 726 __le32 addr_high; 727 __le32 addr_low; 728 }; 729 730 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 731 732 /* expect an array of these structs in the response buffer */ 733 struct i40e_aqc_switch_resource_alloc_element_resp { 734 u8 resource_type; 735 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 736 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 737 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 738 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 739 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 740 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 741 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 742 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 743 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 744 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 745 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 746 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 747 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 748 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 749 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 750 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 751 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 752 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 753 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 754 u8 reserved1; 755 __le16 guaranteed; 756 __le16 total; 757 __le16 used; 758 __le16 total_unalloced; 759 u8 reserved2[6]; 760 }; 761 762 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 763 764 /* Set Switch Configuration (direct 0x0205) */ 765 struct i40e_aqc_set_switch_config { 766 __le16 flags; 767 /* flags used for both fields below */ 768 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 769 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 770 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 771 #define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008 772 __le16 valid_flags; 773 /* The ethertype in switch_tag is dropped on ingress and used 774 * internally by the switch. Set this to zero for the default 775 * of 0x88a8 (802.1ad). Should be zero for firmware API 776 * versions lower than 1.7. 777 */ 778 __le16 switch_tag; 779 /* The ethertypes in first_tag and second_tag are used to 780 * match the outer and inner VLAN tags (respectively) when HW 781 * double VLAN tagging is enabled via the set port parameters 782 * AQ command. Otherwise these are both ignored. Set them to 783 * zero for their defaults of 0x8100 (802.1Q). Should be zero 784 * for firmware API versions lower than 1.7. 785 */ 786 __le16 first_tag; 787 __le16 second_tag; 788 /* Next byte is split into following: 789 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 790 * Bit 6 : 0 : Destination Port, 1: source port 791 * Bit 5..4 : L4 type 792 * 0: rsvd 793 * 1: TCP 794 * 2: UDP 795 * 3: Both TCP and UDP 796 * Bits 3:0 Mode 797 * 0: default mode 798 * 1: L4 port only mode 799 * 2: non-tunneled mode 800 * 3: tunneled mode 801 */ 802 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 803 804 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 805 806 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 807 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 808 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 809 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 810 811 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 812 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 813 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 814 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 815 u8 mode; 816 u8 rsvd5[5]; 817 }; 818 819 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 820 821 /* Read Receive control registers (direct 0x0206) 822 * Write Receive control registers (direct 0x0207) 823 * used for accessing Rx control registers that can be 824 * slow and need special handling when under high Rx load 825 */ 826 struct i40e_aqc_rx_ctl_reg_read_write { 827 __le32 reserved1; 828 __le32 address; 829 __le32 reserved2; 830 __le32 value; 831 }; 832 833 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 834 835 /* Add VSI (indirect 0x0210) 836 * this indirect command uses struct i40e_aqc_vsi_properties_data 837 * as the indirect buffer (128 bytes) 838 * 839 * Update VSI (indirect 0x211) 840 * uses the same data structure as Add VSI 841 * 842 * Get VSI (indirect 0x0212) 843 * uses the same completion and data structure as Add VSI 844 */ 845 struct i40e_aqc_add_get_update_vsi { 846 __le16 uplink_seid; 847 u8 connection_type; 848 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 849 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 850 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 851 u8 reserved1; 852 u8 vf_id; 853 u8 reserved2; 854 __le16 vsi_flags; 855 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 856 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 857 #define I40E_AQ_VSI_TYPE_VF 0x0 858 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 859 #define I40E_AQ_VSI_TYPE_PF 0x2 860 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 861 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 862 __le32 addr_high; 863 __le32 addr_low; 864 }; 865 866 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 867 868 struct i40e_aqc_add_get_update_vsi_completion { 869 __le16 seid; 870 __le16 vsi_number; 871 __le16 vsi_used; 872 __le16 vsi_free; 873 __le32 addr_high; 874 __le32 addr_low; 875 }; 876 877 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 878 879 struct i40e_aqc_vsi_properties_data { 880 /* first 96 byte are written by SW */ 881 __le16 valid_sections; 882 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 883 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 884 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 885 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 886 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 887 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 888 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 889 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 890 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 891 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 892 /* switch section */ 893 __le16 switch_id; /* 12bit id combined with flags below */ 894 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 895 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 896 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 897 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 898 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 899 u8 sw_reserved[2]; 900 /* security section */ 901 u8 sec_flags; 902 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 903 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 904 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 905 u8 sec_reserved; 906 /* VLAN section */ 907 __le16 pvid; /* VLANS include priority bits */ 908 __le16 outer_vlan; 909 u8 port_vlan_flags; 910 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 911 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 912 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 913 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 914 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 915 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 916 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 917 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 918 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 919 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 920 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 921 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 922 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 923 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 924 u8 outer_vlan_flags; 925 #define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00 926 #define I40E_AQ_VSI_OVLAN_MODE_MASK (0x03 << \ 927 I40E_AQ_VSI_OVLAN_MODE_SHIFT) 928 #define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED 0x01 929 #define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02 930 #define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03 931 #define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04 932 #define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03 933 #define I40E_AQ_VSI_OVLAN_EMOD_MASK (0x03 <<\ 934 I40E_AQ_VSI_OVLAN_EMOD_SHIFT) 935 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL 0x00 936 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01 937 #define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL 0x02 938 #define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03 939 #define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04 940 941 u8 pvlan_reserved[2]; 942 /* ingress egress up sections */ 943 __le32 ingress_table; /* bitmap, 3 bits per up */ 944 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 945 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 946 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 947 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 948 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 949 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 950 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 951 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 952 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 953 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 954 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 955 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 956 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 957 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 958 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 959 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 960 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 961 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 962 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 963 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 964 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 965 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 966 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 967 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 968 __le32 egress_table; /* same defines as for ingress table */ 969 /* cascaded PV section */ 970 __le16 cas_pv_tag; 971 u8 cas_pv_flags; 972 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 973 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 974 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 975 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 976 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 977 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 978 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 979 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 980 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 981 u8 cas_pv_reserved; 982 /* queue mapping section */ 983 __le16 mapping_flags; 984 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 985 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 986 __le16 queue_mapping[16]; 987 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 988 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 989 __le16 tc_mapping[8]; 990 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 991 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 992 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 993 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 994 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 995 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 996 /* queueing option section */ 997 u8 queueing_opt_flags; 998 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 999 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 1000 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 1001 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 1002 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 1003 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 1004 u8 queueing_opt_reserved[3]; 1005 /* scheduler section */ 1006 u8 up_enable_bits; 1007 u8 sched_reserved; 1008 /* outer up section */ 1009 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1010 u8 cmd_reserved[8]; 1011 /* last 32 bytes are written by FW */ 1012 __le16 qs_handle[8]; 1013 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1014 __le16 stat_counter_idx; 1015 __le16 sched_id; 1016 u8 resp_reserved[12]; 1017 }; 1018 1019 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1020 1021 /* Add Port Virtualizer (direct 0x0220) 1022 * also used for update PV (direct 0x0221) but only flags are used 1023 * (IS_CTRL_PORT only works on add PV) 1024 */ 1025 struct i40e_aqc_add_update_pv { 1026 __le16 command_flags; 1027 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1028 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1029 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1030 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1031 __le16 uplink_seid; 1032 __le16 connected_seid; 1033 u8 reserved[10]; 1034 }; 1035 1036 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1037 1038 struct i40e_aqc_add_update_pv_completion { 1039 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1040 __le16 pv_seid; 1041 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1042 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1043 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1044 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1045 u8 reserved[14]; 1046 }; 1047 1048 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1049 1050 /* Get PV Params (direct 0x0222) 1051 * uses i40e_aqc_switch_seid for the descriptor 1052 */ 1053 1054 struct i40e_aqc_get_pv_params_completion { 1055 __le16 seid; 1056 __le16 default_stag; 1057 __le16 pv_flags; /* same flags as add_pv */ 1058 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1059 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1060 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1061 u8 reserved[8]; 1062 __le16 default_port_seid; 1063 }; 1064 1065 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1066 1067 /* Add VEB (direct 0x0230) */ 1068 struct i40e_aqc_add_veb { 1069 __le16 uplink_seid; 1070 __le16 downlink_seid; 1071 __le16 veb_flags; 1072 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1073 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1074 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1075 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1076 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1077 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1078 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1079 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1080 u8 enable_tcs; 1081 u8 reserved[9]; 1082 }; 1083 1084 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1085 1086 struct i40e_aqc_add_veb_completion { 1087 u8 reserved[6]; 1088 __le16 switch_seid; 1089 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1090 __le16 veb_seid; 1091 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1092 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1093 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1094 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1095 __le16 statistic_index; 1096 __le16 vebs_used; 1097 __le16 vebs_free; 1098 }; 1099 1100 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1101 1102 /* Get VEB Parameters (direct 0x0232) 1103 * uses i40e_aqc_switch_seid for the descriptor 1104 */ 1105 struct i40e_aqc_get_veb_parameters_completion { 1106 __le16 seid; 1107 __le16 switch_id; 1108 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1109 __le16 statistic_index; 1110 __le16 vebs_used; 1111 __le16 vebs_free; 1112 u8 reserved[4]; 1113 }; 1114 1115 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1116 1117 /* Delete Element (direct 0x0243) 1118 * uses the generic i40e_aqc_switch_seid 1119 */ 1120 1121 /* Add MAC-VLAN (indirect 0x0250) */ 1122 1123 /* used for the command for most vlan commands */ 1124 struct i40e_aqc_macvlan { 1125 __le16 num_addresses; 1126 __le16 seid[3]; 1127 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1128 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1129 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1130 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1131 __le32 addr_high; 1132 __le32 addr_low; 1133 }; 1134 1135 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1136 1137 /* indirect data for command and response */ 1138 struct i40e_aqc_add_macvlan_element_data { 1139 u8 mac_addr[6]; 1140 __le16 vlan_tag; 1141 __le16 flags; 1142 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1143 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1144 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1145 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1146 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1147 __le16 queue_number; 1148 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1149 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1150 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1151 /* response section */ 1152 u8 match_method; 1153 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1154 #define I40E_AQC_MM_HASH_MATCH 0x02 1155 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1156 u8 reserved1[3]; 1157 }; 1158 1159 struct i40e_aqc_add_remove_macvlan_completion { 1160 __le16 perfect_mac_used; 1161 __le16 perfect_mac_free; 1162 __le16 unicast_hash_free; 1163 __le16 multicast_hash_free; 1164 __le32 addr_high; 1165 __le32 addr_low; 1166 }; 1167 1168 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1169 1170 /* Remove MAC-VLAN (indirect 0x0251) 1171 * uses i40e_aqc_macvlan for the descriptor 1172 * data points to an array of num_addresses of elements 1173 */ 1174 1175 struct i40e_aqc_remove_macvlan_element_data { 1176 u8 mac_addr[6]; 1177 __le16 vlan_tag; 1178 u8 flags; 1179 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1180 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1181 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1182 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1183 u8 reserved[3]; 1184 /* reply section */ 1185 u8 error_code; 1186 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1187 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1188 u8 reply_reserved[3]; 1189 }; 1190 1191 /* Add VLAN (indirect 0x0252) 1192 * Remove VLAN (indirect 0x0253) 1193 * use the generic i40e_aqc_macvlan for the command 1194 */ 1195 struct i40e_aqc_add_remove_vlan_element_data { 1196 __le16 vlan_tag; 1197 u8 vlan_flags; 1198 /* flags for add VLAN */ 1199 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1200 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1201 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1202 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1203 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1204 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1205 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1206 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1207 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1208 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1209 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1210 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1211 /* flags for remove VLAN */ 1212 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1213 u8 reserved; 1214 u8 result; 1215 /* flags for add VLAN */ 1216 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1217 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1218 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1219 /* flags for remove VLAN */ 1220 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1221 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1222 u8 reserved1[3]; 1223 }; 1224 1225 struct i40e_aqc_add_remove_vlan_completion { 1226 u8 reserved[4]; 1227 __le16 vlans_used; 1228 __le16 vlans_free; 1229 __le32 addr_high; 1230 __le32 addr_low; 1231 }; 1232 1233 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1234 struct i40e_aqc_set_vsi_promiscuous_modes { 1235 __le16 promiscuous_flags; 1236 __le16 valid_flags; 1237 /* flags used for both fields above */ 1238 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1239 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1240 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1241 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1242 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1243 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000 1244 __le16 seid; 1245 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1246 __le16 vlan_tag; 1247 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1248 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1249 u8 reserved[8]; 1250 }; 1251 1252 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1253 1254 /* Add S/E-tag command (direct 0x0255) 1255 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1256 */ 1257 struct i40e_aqc_add_tag { 1258 __le16 flags; 1259 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1260 __le16 seid; 1261 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1262 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1263 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1264 __le16 tag; 1265 __le16 queue_number; 1266 u8 reserved[8]; 1267 }; 1268 1269 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1270 1271 struct i40e_aqc_add_remove_tag_completion { 1272 u8 reserved[12]; 1273 __le16 tags_used; 1274 __le16 tags_free; 1275 }; 1276 1277 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1278 1279 /* Remove S/E-tag command (direct 0x0256) 1280 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1281 */ 1282 struct i40e_aqc_remove_tag { 1283 __le16 seid; 1284 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1285 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1286 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1287 __le16 tag; 1288 u8 reserved[12]; 1289 }; 1290 1291 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1292 1293 /* Add multicast E-Tag (direct 0x0257) 1294 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1295 * and no external data 1296 */ 1297 struct i40e_aqc_add_remove_mcast_etag { 1298 __le16 pv_seid; 1299 __le16 etag; 1300 u8 num_unicast_etags; 1301 u8 reserved[3]; 1302 __le32 addr_high; /* address of array of 2-byte s-tags */ 1303 __le32 addr_low; 1304 }; 1305 1306 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1307 1308 struct i40e_aqc_add_remove_mcast_etag_completion { 1309 u8 reserved[4]; 1310 __le16 mcast_etags_used; 1311 __le16 mcast_etags_free; 1312 __le32 addr_high; 1313 __le32 addr_low; 1314 1315 }; 1316 1317 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1318 1319 /* Update S/E-Tag (direct 0x0259) */ 1320 struct i40e_aqc_update_tag { 1321 __le16 seid; 1322 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1323 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1324 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1325 __le16 old_tag; 1326 __le16 new_tag; 1327 u8 reserved[10]; 1328 }; 1329 1330 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1331 1332 struct i40e_aqc_update_tag_completion { 1333 u8 reserved[12]; 1334 __le16 tags_used; 1335 __le16 tags_free; 1336 }; 1337 1338 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1339 1340 /* Add Control Packet filter (direct 0x025A) 1341 * Remove Control Packet filter (direct 0x025B) 1342 * uses the i40e_aqc_add_oveb_cloud, 1343 * and the generic direct completion structure 1344 */ 1345 struct i40e_aqc_add_remove_control_packet_filter { 1346 u8 mac[6]; 1347 __le16 etype; 1348 __le16 flags; 1349 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1350 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1351 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1352 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1353 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1354 __le16 seid; 1355 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1356 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1357 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1358 __le16 queue; 1359 u8 reserved[2]; 1360 }; 1361 1362 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1363 1364 struct i40e_aqc_add_remove_control_packet_filter_completion { 1365 __le16 mac_etype_used; 1366 __le16 etype_used; 1367 __le16 mac_etype_free; 1368 __le16 etype_free; 1369 u8 reserved[8]; 1370 }; 1371 1372 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1373 1374 /* Add Cloud filters (indirect 0x025C) 1375 * Remove Cloud filters (indirect 0x025D) 1376 * uses the i40e_aqc_add_remove_cloud_filters, 1377 * and the generic indirect completion structure 1378 */ 1379 struct i40e_aqc_add_remove_cloud_filters { 1380 u8 num_filters; 1381 u8 reserved; 1382 __le16 seid; 1383 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1384 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1385 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1386 u8 big_buffer_flag; 1387 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1 1388 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1389 u8 reserved2[3]; 1390 __le32 addr_high; 1391 __le32 addr_low; 1392 }; 1393 1394 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1395 1396 struct i40e_aqc_cloud_filters_element_data { 1397 u8 outer_mac[6]; 1398 u8 inner_mac[6]; 1399 __le16 inner_vlan; 1400 union { 1401 struct { 1402 u8 reserved[12]; 1403 u8 data[4]; 1404 } v4; 1405 struct { 1406 u8 data[16]; 1407 } v6; 1408 struct { 1409 __le16 data[8]; 1410 } raw_v6; 1411 } ipaddr; 1412 __le16 flags; 1413 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1414 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1415 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1416 /* 0x0000 reserved */ 1417 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1418 /* 0x0002 reserved */ 1419 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1420 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1421 /* 0x0005 reserved */ 1422 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1423 /* 0x0007 reserved */ 1424 /* 0x0008 reserved */ 1425 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1426 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1427 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1428 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1429 #define I40E_AQC_ADD_CLOUD_FILTER_OIP1 0x0010 1430 #define I40E_AQC_ADD_CLOUD_FILTER_OIP2 0x0012 1431 /* 0x000D reserved */ 1432 /* 0x000E reserved */ 1433 /* 0x000F reserved */ 1434 /* 0x0010 to 0x0017 is for custom filters */ 1435 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1436 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1437 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1438 1439 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1440 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1441 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1442 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1443 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1444 1445 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1446 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1447 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1448 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1449 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1450 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1451 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1452 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1453 1454 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1455 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1456 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1457 1458 __le32 tenant_id; 1459 u8 reserved[4]; 1460 __le16 queue_number; 1461 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1462 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1463 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1464 u8 reserved2[14]; 1465 /* response section */ 1466 u8 allocation_result; 1467 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1468 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1469 u8 response_reserved[7]; 1470 }; 1471 1472 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when 1473 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. 1474 */ 1475 struct i40e_aqc_add_rm_cloud_filt_elem_ext { 1476 struct i40e_aqc_cloud_filters_element_data element; 1477 u16 general_fields[32]; 1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1479 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1480 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1481 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1482 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1483 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1484 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1485 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1486 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1487 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1488 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1493 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1494 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1495 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1496 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1497 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1498 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1499 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1500 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1501 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1502 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1503 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1509 }; 1510 1511 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1512 1513 /* i40e_aqc_cloud_filters_element_bb is used when 1514 * I40E_AQC_CLOUD_CMD_BB flag is set. 1515 */ 1516 struct i40e_aqc_cloud_filters_element_bb { 1517 struct i40e_aqc_cloud_filters_element_data element; 1518 u16 general_fields[32]; 1519 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1520 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1521 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1522 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1523 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1524 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1525 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1526 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1527 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1528 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1529 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1530 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1531 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1532 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1533 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1534 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1535 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1536 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1537 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1538 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1539 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1540 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1541 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1542 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1543 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1544 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1545 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1546 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1547 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1548 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1549 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1550 }; 1551 1552 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1553 1554 struct i40e_aqc_remove_cloud_filters_completion { 1555 __le16 perfect_ovlan_used; 1556 __le16 perfect_ovlan_free; 1557 __le16 vlan_used; 1558 __le16 vlan_free; 1559 __le32 addr_high; 1560 __le32 addr_low; 1561 }; 1562 1563 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1564 1565 /* Replace filter Command 0x025F 1566 * uses the i40e_aqc_replace_cloud_filters, 1567 * and the generic indirect completion structure 1568 */ 1569 struct i40e_filter_data { 1570 u8 filter_type; 1571 u8 input[3]; 1572 }; 1573 1574 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1575 1576 struct i40e_aqc_replace_cloud_filters_cmd { 1577 u8 valid_flags; 1578 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1579 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1580 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1581 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1582 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1583 u8 old_filter_type; 1584 u8 new_filter_type; 1585 u8 tr_bit; 1586 u8 tr_bit2; 1587 u8 reserved[3]; 1588 __le32 addr_high; 1589 __le32 addr_low; 1590 }; 1591 1592 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1593 1594 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1595 u8 data[32]; 1596 /* Filter type INPUT codes*/ 1597 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1598 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL) 1599 1600 /* Field Vector offsets */ 1601 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1602 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1603 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1604 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1605 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1606 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1607 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1608 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1609 /* big FLU */ 1610 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1611 /* big FLU */ 1612 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1613 1614 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1615 struct i40e_filter_data filters[8]; 1616 }; 1617 1618 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1619 1620 /* Add Mirror Rule (indirect or direct 0x0260) 1621 * Delete Mirror Rule (indirect or direct 0x0261) 1622 * note: some rule types (4,5) do not use an external buffer. 1623 * take care to set the flags correctly. 1624 */ 1625 struct i40e_aqc_add_delete_mirror_rule { 1626 __le16 seid; 1627 __le16 rule_type; 1628 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1629 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1630 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1631 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1632 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1633 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1634 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1635 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1636 __le16 num_entries; 1637 __le16 destination; /* VSI for add, rule id for delete */ 1638 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1639 __le32 addr_low; 1640 }; 1641 1642 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1643 1644 struct i40e_aqc_add_delete_mirror_rule_completion { 1645 u8 reserved[2]; 1646 __le16 rule_id; /* only used on add */ 1647 __le16 mirror_rules_used; 1648 __le16 mirror_rules_free; 1649 __le32 addr_high; 1650 __le32 addr_low; 1651 }; 1652 1653 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1654 1655 /* Dynamic Device Personalization */ 1656 struct i40e_aqc_write_personalization_profile { 1657 u8 flags; 1658 u8 reserved[3]; 1659 __le32 profile_track_id; 1660 __le32 addr_high; 1661 __le32 addr_low; 1662 }; 1663 1664 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1665 1666 struct i40e_aqc_write_ddp_resp { 1667 __le32 error_offset; 1668 __le32 error_info; 1669 __le32 addr_high; 1670 __le32 addr_low; 1671 }; 1672 1673 struct i40e_aqc_get_applied_profiles { 1674 u8 flags; 1675 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1676 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1677 u8 rsv[3]; 1678 __le32 reserved; 1679 __le32 addr_high; 1680 __le32 addr_low; 1681 }; 1682 1683 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1684 1685 /* DCB 0x03xx*/ 1686 1687 /* PFC Ignore (direct 0x0301) 1688 * the command and response use the same descriptor structure 1689 */ 1690 struct i40e_aqc_pfc_ignore { 1691 u8 tc_bitmap; 1692 u8 command_flags; /* unused on response */ 1693 #define I40E_AQC_PFC_IGNORE_SET 0x80 1694 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1695 u8 reserved[14]; 1696 }; 1697 1698 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1699 1700 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1701 * with no parameters 1702 */ 1703 1704 /* TX scheduler 0x04xx */ 1705 1706 /* Almost all the indirect commands use 1707 * this generic struct to pass the SEID in param0 1708 */ 1709 struct i40e_aqc_tx_sched_ind { 1710 __le16 vsi_seid; 1711 u8 reserved[6]; 1712 __le32 addr_high; 1713 __le32 addr_low; 1714 }; 1715 1716 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1717 1718 /* Several commands respond with a set of queue set handles */ 1719 struct i40e_aqc_qs_handles_resp { 1720 __le16 qs_handles[8]; 1721 }; 1722 1723 /* Configure VSI BW limits (direct 0x0400) */ 1724 struct i40e_aqc_configure_vsi_bw_limit { 1725 __le16 vsi_seid; 1726 u8 reserved[2]; 1727 __le16 credit; 1728 u8 reserved1[2]; 1729 u8 max_credit; /* 0-3, limit = 2^max */ 1730 u8 reserved2[7]; 1731 }; 1732 1733 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1734 1735 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1736 * responds with i40e_aqc_qs_handles_resp 1737 */ 1738 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1739 u8 tc_valid_bits; 1740 u8 reserved[15]; 1741 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1742 1743 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1744 __le16 tc_bw_max[2]; 1745 u8 reserved1[28]; 1746 }; 1747 1748 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1749 1750 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1751 * responds with i40e_aqc_qs_handles_resp 1752 */ 1753 struct i40e_aqc_configure_vsi_tc_bw_data { 1754 u8 tc_valid_bits; 1755 u8 reserved[3]; 1756 u8 tc_bw_credits[8]; 1757 u8 reserved1[4]; 1758 __le16 qs_handles[8]; 1759 }; 1760 1761 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1762 1763 /* Query vsi bw configuration (indirect 0x0408) */ 1764 struct i40e_aqc_query_vsi_bw_config_resp { 1765 u8 tc_valid_bits; 1766 u8 tc_suspended_bits; 1767 u8 reserved[14]; 1768 __le16 qs_handles[8]; 1769 u8 reserved1[4]; 1770 __le16 port_bw_limit; 1771 u8 reserved2[2]; 1772 u8 max_bw; /* 0-3, limit = 2^max */ 1773 u8 reserved3[23]; 1774 }; 1775 1776 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1777 1778 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1779 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1780 u8 tc_valid_bits; 1781 u8 reserved[3]; 1782 u8 share_credits[8]; 1783 __le16 credits[8]; 1784 1785 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1786 __le16 tc_bw_max[2]; 1787 }; 1788 1789 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1790 1791 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1792 struct i40e_aqc_configure_switching_comp_bw_limit { 1793 __le16 seid; 1794 u8 reserved[2]; 1795 __le16 credit; 1796 u8 reserved1[2]; 1797 u8 max_bw; /* 0-3, limit = 2^max */ 1798 u8 reserved2[7]; 1799 }; 1800 1801 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1802 1803 /* Enable Physical Port ETS (indirect 0x0413) 1804 * Modify Physical Port ETS (indirect 0x0414) 1805 * Disable Physical Port ETS (indirect 0x0415) 1806 */ 1807 struct i40e_aqc_configure_switching_comp_ets_data { 1808 u8 reserved[4]; 1809 u8 tc_valid_bits; 1810 u8 seepage; 1811 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1812 u8 tc_strict_priority_flags; 1813 u8 reserved1[17]; 1814 u8 tc_bw_share_credits[8]; 1815 u8 reserved2[96]; 1816 }; 1817 1818 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1819 1820 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1821 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1822 u8 tc_valid_bits; 1823 u8 reserved[15]; 1824 __le16 tc_bw_credit[8]; 1825 1826 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1827 __le16 tc_bw_max[2]; 1828 u8 reserved1[28]; 1829 }; 1830 1831 I40E_CHECK_STRUCT_LEN(0x40, 1832 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1833 1834 /* Configure Switching Component Bandwidth Allocation per Tc 1835 * (indirect 0x0417) 1836 */ 1837 struct i40e_aqc_configure_switching_comp_bw_config_data { 1838 u8 tc_valid_bits; 1839 u8 reserved[2]; 1840 u8 absolute_credits; /* bool */ 1841 u8 tc_bw_share_credits[8]; 1842 u8 reserved1[20]; 1843 }; 1844 1845 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1846 1847 /* Query Switching Component Configuration (indirect 0x0418) */ 1848 struct i40e_aqc_query_switching_comp_ets_config_resp { 1849 u8 tc_valid_bits; 1850 u8 reserved[35]; 1851 __le16 port_bw_limit; 1852 u8 reserved1[2]; 1853 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1854 u8 reserved2[23]; 1855 }; 1856 1857 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1858 1859 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1860 struct i40e_aqc_query_port_ets_config_resp { 1861 u8 reserved[4]; 1862 u8 tc_valid_bits; 1863 u8 reserved1; 1864 u8 tc_strict_priority_bits; 1865 u8 reserved2; 1866 u8 tc_bw_share_credits[8]; 1867 __le16 tc_bw_limits[8]; 1868 1869 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1870 __le16 tc_bw_max[2]; 1871 u8 reserved3[32]; 1872 }; 1873 1874 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1875 1876 /* Query Switching Component Bandwidth Allocation per Traffic Type 1877 * (indirect 0x041A) 1878 */ 1879 struct i40e_aqc_query_switching_comp_bw_config_resp { 1880 u8 tc_valid_bits; 1881 u8 reserved[2]; 1882 u8 absolute_credits_enable; /* bool */ 1883 u8 tc_bw_share_credits[8]; 1884 __le16 tc_bw_limits[8]; 1885 1886 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1887 __le16 tc_bw_max[2]; 1888 }; 1889 1890 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1891 1892 /* Suspend/resume port TX traffic 1893 * (direct 0x041B and 0x041C) uses the generic SEID struct 1894 */ 1895 1896 /* Configure partition BW 1897 * (indirect 0x041D) 1898 */ 1899 struct i40e_aqc_configure_partition_bw_data { 1900 __le16 pf_valid_bits; 1901 u8 min_bw[16]; /* guaranteed bandwidth */ 1902 u8 max_bw[16]; /* bandwidth limit */ 1903 }; 1904 1905 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1906 1907 /* Get and set the active HMC resource profile and status. 1908 * (direct 0x0500) and (direct 0x0501) 1909 */ 1910 struct i40e_aq_get_set_hmc_resource_profile { 1911 u8 pm_profile; 1912 u8 pe_vf_enabled; 1913 u8 reserved[14]; 1914 }; 1915 1916 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1917 1918 enum i40e_aq_hmc_profile { 1919 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1920 I40E_HMC_PROFILE_DEFAULT = 1, 1921 I40E_HMC_PROFILE_FAVOR_VF = 2, 1922 I40E_HMC_PROFILE_EQUAL = 3, 1923 }; 1924 1925 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1926 1927 /* set in param0 for get phy abilities to report qualified modules */ 1928 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1929 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1930 1931 enum i40e_aq_phy_type { 1932 I40E_PHY_TYPE_SGMII = 0x0, 1933 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1934 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1935 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1936 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1937 I40E_PHY_TYPE_XAUI = 0x5, 1938 I40E_PHY_TYPE_XFI = 0x6, 1939 I40E_PHY_TYPE_SFI = 0x7, 1940 I40E_PHY_TYPE_XLAUI = 0x8, 1941 I40E_PHY_TYPE_XLPPI = 0x9, 1942 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1943 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1944 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1945 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1946 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1947 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1948 I40E_PHY_TYPE_100BASE_TX = 0x11, 1949 I40E_PHY_TYPE_1000BASE_T = 0x12, 1950 I40E_PHY_TYPE_10GBASE_T = 0x13, 1951 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1952 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1953 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1954 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1955 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1956 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1957 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1958 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1959 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1960 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1961 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1962 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1963 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1964 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1965 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1966 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1967 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1968 I40E_PHY_TYPE_2_5GBASE_T = 0x26, 1969 I40E_PHY_TYPE_5GBASE_T = 0x27, 1970 I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30, 1971 I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31, 1972 I40E_PHY_TYPE_MAX, 1973 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1974 I40E_PHY_TYPE_EMPTY = 0xFE, 1975 I40E_PHY_TYPE_DEFAULT = 0xFF, 1976 }; 1977 1978 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1979 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1980 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1981 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1982 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1983 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1984 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1985 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1986 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1987 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1988 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1989 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1990 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1991 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1992 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1993 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1994 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1995 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1996 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1997 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1998 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1999 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 2000 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 2001 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 2002 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 2003 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 2004 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 2005 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 2006 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 2007 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 2008 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 2009 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 2010 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 2011 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 2012 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 2013 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 2014 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 2015 BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 2016 2017 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 2018 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 2019 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 2020 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 2021 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 2022 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 2023 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 2024 #define I40E_LINK_SPEED_5GB_SHIFT 0x7 2025 2026 enum i40e_aq_link_speed { 2027 I40E_LINK_SPEED_UNKNOWN = 0, 2028 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 2029 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 2030 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 2031 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 2032 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 2033 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 2034 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 2035 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 2036 }; 2037 2038 enum i40e_prt_mac_pcs_link_speed { 2039 I40E_PRT_MAC_PCS_LINK_SPEED_UNKNOWN = 0, 2040 I40E_PRT_MAC_PCS_LINK_SPEED_100MB, 2041 I40E_PRT_MAC_PCS_LINK_SPEED_1GB, 2042 I40E_PRT_MAC_PCS_LINK_SPEED_10GB, 2043 I40E_PRT_MAC_PCS_LINK_SPEED_40GB, 2044 I40E_PRT_MAC_PCS_LINK_SPEED_20GB 2045 }; 2046 2047 struct i40e_aqc_module_desc { 2048 u8 oui[3]; 2049 u8 reserved1; 2050 u8 part_number[16]; 2051 u8 revision[4]; 2052 u8 reserved2[8]; 2053 }; 2054 2055 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 2056 2057 struct i40e_aq_get_phy_abilities_resp { 2058 __le32 phy_type; /* bitmap using the above enum for offsets */ 2059 u8 link_speed; /* bitmap using the above enum bit patterns */ 2060 u8 abilities; 2061 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 2062 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 2063 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 2064 #define I40E_AQ_PHY_LINK_ENABLED 0x08 2065 #define I40E_AQ_PHY_AN_ENABLED 0x10 2066 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 2067 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 2068 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 2069 __le16 eee_capability; 2070 #define I40E_AQ_EEE_AUTO 0x0001 2071 #define I40E_AQ_EEE_100BASE_TX 0x0002 2072 #define I40E_AQ_EEE_1000BASE_T 0x0004 2073 #define I40E_AQ_EEE_10GBASE_T 0x0008 2074 #define I40E_AQ_EEE_1000BASE_KX 0x0010 2075 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 2076 #define I40E_AQ_EEE_10GBASE_KR 0x0040 2077 #define I40E_AQ_EEE_2_5GBASE_T 0x0100 2078 #define I40E_AQ_EEE_5GBASE_T 0x0200 2079 __le32 eeer_val; 2080 u8 d3_lpan; 2081 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 2082 u8 phy_type_ext; 2083 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 2084 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 2085 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2086 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2087 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 2088 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 2089 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 2090 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 2091 u8 fec_cfg_curr_mod_ext_info; 2092 #define I40E_AQ_ENABLE_FEC_KR 0x01 2093 #define I40E_AQ_ENABLE_FEC_RS 0x02 2094 #define I40E_AQ_REQUEST_FEC_KR 0x04 2095 #define I40E_AQ_REQUEST_FEC_RS 0x08 2096 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 2097 #define I40E_AQ_FEC 2098 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 2099 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 2100 2101 u8 ext_comp_code; 2102 u8 phy_id[4]; 2103 u8 module_type[3]; 2104 u8 qualified_module_count; 2105 #define I40E_AQ_PHY_MAX_QMS 16 2106 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2107 }; 2108 2109 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2110 2111 /* Set PHY Config (direct 0x0601) */ 2112 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2113 __le32 phy_type; 2114 u8 link_speed; 2115 u8 abilities; 2116 /* bits 0-2 use the values from get_phy_abilities_resp */ 2117 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2118 #define I40E_AQ_PHY_ENABLE_AN 0x10 2119 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2120 __le16 eee_capability; 2121 __le32 eeer; 2122 u8 low_power_ctrl; 2123 u8 phy_type_ext; 2124 u8 fec_config; 2125 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2126 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2127 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2128 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2129 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2130 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2131 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2132 u8 reserved; 2133 }; 2134 2135 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2136 2137 /* Set MAC Config command data structure (direct 0x0603) */ 2138 struct i40e_aq_set_mac_config { 2139 __le16 max_frame_size; 2140 u8 params; 2141 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2142 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2143 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2144 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2145 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2146 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2147 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2148 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2149 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2150 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2151 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2152 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2153 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2154 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2155 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80 2156 u8 tx_timer_priority; /* bitmap */ 2157 __le16 tx_timer_value; 2158 __le16 fc_refresh_threshold; 2159 u8 reserved[8]; 2160 }; 2161 2162 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2163 2164 /* Restart Auto-Negotiation (direct 0x605) */ 2165 struct i40e_aqc_set_link_restart_an { 2166 u8 command; 2167 #define I40E_AQ_PHY_RESTART_AN 0x02 2168 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2169 u8 reserved[15]; 2170 }; 2171 2172 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2173 2174 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2175 struct i40e_aqc_get_link_status { 2176 __le16 command_flags; /* only field set on command */ 2177 #define I40E_AQ_LSE_MASK 0x3 2178 #define I40E_AQ_LSE_NOP 0x0 2179 #define I40E_AQ_LSE_DISABLE 0x2 2180 #define I40E_AQ_LSE_ENABLE 0x3 2181 /* only response uses this flag */ 2182 #define I40E_AQ_LSE_IS_ENABLED 0x1 2183 u8 phy_type; /* i40e_aq_phy_type */ 2184 u8 link_speed; /* i40e_aq_link_speed */ 2185 u8 link_info; 2186 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2187 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2188 #define I40E_AQ_LINK_FAULT 0x02 2189 #define I40E_AQ_LINK_FAULT_TX 0x04 2190 #define I40E_AQ_LINK_FAULT_RX 0x08 2191 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2192 #define I40E_AQ_LINK_UP_PORT 0x20 2193 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2194 #define I40E_AQ_SIGNAL_DETECT 0x80 2195 u8 an_info; 2196 #define I40E_AQ_AN_COMPLETED 0x01 2197 #define I40E_AQ_LP_AN_ABILITY 0x02 2198 #define I40E_AQ_PD_FAULT 0x04 2199 #define I40E_AQ_FEC_EN 0x08 2200 #define I40E_AQ_PHY_LOW_POWER 0x10 2201 #define I40E_AQ_LINK_PAUSE_TX 0x20 2202 #define I40E_AQ_LINK_PAUSE_RX 0x40 2203 #define I40E_AQ_QUALIFIED_MODULE 0x80 2204 u8 ext_info; 2205 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2206 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2207 #define I40E_AQ_LINK_TX_SHIFT 0x02 2208 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2209 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2210 #define I40E_AQ_LINK_TX_DRAINED 0x01 2211 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2212 #define I40E_AQ_LINK_FORCED_40G 0x10 2213 /* 25G Error Codes */ 2214 #define I40E_AQ_25G_NO_ERR 0X00 2215 #define I40E_AQ_25G_NOT_PRESENT 0X01 2216 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2217 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2218 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2219 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2220 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2221 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2222 #define I40E_AQ_LOOPBACK_MASK 0x07 2223 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2224 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2225 __le16 max_frame_size; 2226 u8 config; 2227 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2228 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2229 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2230 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2231 union { 2232 struct { 2233 u8 power_desc; 2234 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2235 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2236 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2237 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2238 #define I40E_AQ_PWR_CLASS_MASK 0x03 2239 u8 reserved[4]; 2240 }; 2241 struct { 2242 u8 link_type[4]; 2243 u8 link_type_ext; 2244 }; 2245 }; 2246 }; 2247 2248 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2249 2250 /* Set event mask command (direct 0x613) */ 2251 struct i40e_aqc_set_phy_int_mask { 2252 u8 reserved[8]; 2253 __le16 event_mask; 2254 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2255 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2256 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2257 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2258 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2259 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2260 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2261 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2262 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2263 u8 reserved1[6]; 2264 }; 2265 2266 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2267 2268 /* Get Local AN advt register (direct 0x0614) 2269 * Set Local AN advt register (direct 0x0615) 2270 * Get Link Partner AN advt register (direct 0x0616) 2271 */ 2272 struct i40e_aqc_an_advt_reg { 2273 __le32 local_an_reg0; 2274 __le16 local_an_reg1; 2275 u8 reserved[10]; 2276 }; 2277 2278 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2279 2280 /* Set Loopback mode (0x0618) */ 2281 struct i40e_aqc_set_lb_mode { 2282 __le16 lb_mode; 2283 #define I40E_AQ_LB_PHY_LOCAL 0x01 2284 #define I40E_AQ_LB_PHY_REMOTE 0x02 2285 #define I40E_AQ_LB_MAC_LOCAL 0x04 2286 u8 reserved[14]; 2287 }; 2288 2289 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2290 2291 /* Set PHY Debug command (0x0622) */ 2292 struct i40e_aqc_set_phy_debug { 2293 u8 command_flags; 2294 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2295 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2296 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2297 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2298 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2299 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2300 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2301 /* Disable link manageability on a single port */ 2302 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2303 /* Disable link manageability on all ports needs both bits 4 and 5 */ 2304 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2305 u8 reserved[15]; 2306 }; 2307 2308 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2309 2310 enum i40e_aq_phy_reg_type { 2311 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2312 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2313 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2314 }; 2315 2316 #pragma pack(1) 2317 /* Run PHY Activity (0x0626) */ 2318 struct i40e_aqc_run_phy_activity { 2319 u8 cmd_flags; 2320 __le16 activity_id; 2321 #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10 2322 u8 reserved; 2323 union { 2324 struct { 2325 __le32 dnl_opcode; 2326 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a 2327 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b 2328 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b 2329 __le32 data; 2330 u8 reserved2[4]; 2331 } cmd; 2332 struct { 2333 __le32 cmd_status; 2334 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4 2335 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF 2336 __le32 data0; 2337 __le32 data1; 2338 } resp; 2339 } params; 2340 }; 2341 #pragma pack() 2342 2343 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2344 2345 /* Set PHY Register command (0x0628) */ 2346 /* Get PHY Register command (0x0629) */ 2347 struct i40e_aqc_phy_register_access { 2348 u8 phy_interface; 2349 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2350 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2351 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2352 u8 dev_addres; 2353 u8 cmd_flags; 2354 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01 2355 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02 2356 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2 2357 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \ 2358 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) 2359 u8 reserved1; 2360 __le32 reg_address; 2361 __le32 reg_value; 2362 u8 reserved2[4]; 2363 }; 2364 2365 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2366 2367 /* NVM Read command (indirect 0x0701) 2368 * NVM Erase commands (direct 0x0702) 2369 * NVM Update commands (indirect 0x0703) 2370 */ 2371 struct i40e_aqc_nvm_update { 2372 u8 command_flags; 2373 #define I40E_AQ_NVM_LAST_CMD 0x01 2374 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2375 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2376 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2377 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2378 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2379 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2380 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2381 u8 module_pointer; 2382 __le16 length; 2383 __le32 offset; 2384 __le32 addr_high; 2385 __le32 addr_low; 2386 }; 2387 2388 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2389 2390 /* NVM Config Read (indirect 0x0704) */ 2391 struct i40e_aqc_nvm_config_read { 2392 __le16 cmd_flags; 2393 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2394 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2395 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2396 __le16 element_count; 2397 __le16 element_id; /* Feature/field ID */ 2398 __le16 element_id_msw; /* MSWord of field ID */ 2399 __le32 address_high; 2400 __le32 address_low; 2401 }; 2402 2403 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2404 2405 /* NVM Config Write (indirect 0x0705) */ 2406 struct i40e_aqc_nvm_config_write { 2407 __le16 cmd_flags; 2408 __le16 element_count; 2409 u8 reserved[4]; 2410 __le32 address_high; 2411 __le32 address_low; 2412 }; 2413 2414 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2415 2416 /* Used for 0x0704 as well as for 0x0705 commands */ 2417 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2418 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2419 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2420 #define I40E_AQ_ANVM_FEATURE 0 2421 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2422 struct i40e_aqc_nvm_config_data_feature { 2423 __le16 feature_id; 2424 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2425 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2426 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2427 __le16 feature_options; 2428 __le16 feature_selection; 2429 }; 2430 2431 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2432 2433 /* NVM Update in Process (direct 0x0706) */ 2434 struct i40e_aqc_nvm_update_in_process { 2435 u8 command; 2436 #define I40E_AQ_UPDATE_FLOW_END 0x0 2437 #define I40E_AQ_UPDATE_FLOW_START 0x1 2438 u8 reserved[15]; 2439 }; 2440 2441 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update_in_process); 2442 2443 struct i40e_aqc_nvm_config_data_immediate_field { 2444 __le32 field_id; 2445 __le32 field_value; 2446 __le16 field_options; 2447 __le16 reserved; 2448 }; 2449 2450 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2451 2452 /* Minimal Rollback Revision Update (direct 0x0707) */ 2453 struct i40e_aqc_rollback_revision_update { 2454 u8 optin_mode; /* bool */ 2455 #define I40E_AQ_RREV_OPTION_MODE 0x01 2456 u8 module_selected; 2457 #define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 2458 #define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 2459 #define I40E_AQ_RREV_MODULE_OPTION_ROM 2 2460 #define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 2461 #define I40E_AQ_RREV_MODULE_PE_IMAGE 4 2462 #define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION 5 2463 #define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION 6 2464 #define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION 7 2465 #define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION 8 2466 u8 reserved1[2]; 2467 u32 min_rrev; 2468 u8 reserved2[8]; 2469 }; 2470 2471 I40E_CHECK_CMD_LENGTH(i40e_aqc_rollback_revision_update); 2472 2473 /* OEM Post Update (indirect 0x0720) 2474 * no command data struct used 2475 */ 2476 struct i40e_aqc_nvm_oem_post_update { 2477 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2478 u8 sel_data; 2479 u8 reserved[7]; 2480 }; 2481 2482 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2483 2484 struct i40e_aqc_nvm_oem_post_update_buffer { 2485 u8 str_len; 2486 u8 dev_addr; 2487 __le16 eeprom_addr; 2488 u8 data[36]; 2489 }; 2490 2491 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2492 2493 /* Thermal Sensor (indirect 0x0721) 2494 * read or set thermal sensor configs and values 2495 * takes a sensor and command specific data buffer, not detailed here 2496 */ 2497 struct i40e_aqc_thermal_sensor { 2498 u8 sensor_action; 2499 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2500 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2501 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2502 u8 reserved[7]; 2503 __le32 addr_high; 2504 __le32 addr_low; 2505 }; 2506 2507 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2508 2509 /* Send to PF command (indirect 0x0801) id is only used by PF 2510 * Send to VF command (indirect 0x0802) id is only used by PF 2511 * Send to Peer PF command (indirect 0x0803) 2512 */ 2513 struct i40e_aqc_pf_vf_message { 2514 __le32 id; 2515 u8 reserved[4]; 2516 __le32 addr_high; 2517 __le32 addr_low; 2518 }; 2519 2520 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2521 2522 /* Alternate structure */ 2523 2524 /* Direct write (direct 0x0900) 2525 * Direct read (direct 0x0902) 2526 */ 2527 struct i40e_aqc_alternate_write { 2528 __le32 address0; 2529 __le32 data0; 2530 __le32 address1; 2531 __le32 data1; 2532 }; 2533 2534 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2535 2536 /* Indirect write (indirect 0x0901) 2537 * Indirect read (indirect 0x0903) 2538 */ 2539 2540 struct i40e_aqc_alternate_ind_write { 2541 __le32 address; 2542 __le32 length; 2543 __le32 addr_high; 2544 __le32 addr_low; 2545 }; 2546 2547 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2548 2549 /* Done alternate write (direct 0x0904) 2550 * uses i40e_aq_desc 2551 */ 2552 struct i40e_aqc_alternate_write_done { 2553 __le16 cmd_flags; 2554 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2555 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2556 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2557 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2558 u8 reserved[14]; 2559 }; 2560 2561 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2562 2563 /* Set OEM mode (direct 0x0905) */ 2564 struct i40e_aqc_alternate_set_mode { 2565 __le32 mode; 2566 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2567 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2568 u8 reserved[12]; 2569 }; 2570 2571 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2572 2573 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2574 2575 /* async events 0x10xx */ 2576 2577 /* Lan Queue Overflow Event (direct, 0x1001) */ 2578 struct i40e_aqc_lan_overflow { 2579 __le32 prtdcb_rupto; 2580 __le32 otx_ctl; 2581 u8 reserved[8]; 2582 }; 2583 2584 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2585 2586 /* Get LLDP MIB (indirect 0x0A00) */ 2587 struct i40e_aqc_lldp_get_mib { 2588 u8 type; 2589 u8 reserved1; 2590 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2591 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2592 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2593 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2594 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2595 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2596 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2597 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2598 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2599 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2600 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2601 __le16 local_len; 2602 __le16 remote_len; 2603 u8 reserved2[2]; 2604 __le32 addr_high; 2605 __le32 addr_low; 2606 }; 2607 2608 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2609 2610 /* Configure LLDP MIB Change Event (direct 0x0A01) 2611 * also used for the event (with type in the command field) 2612 */ 2613 struct i40e_aqc_lldp_update_mib { 2614 u8 command; 2615 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2616 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2617 u8 reserved[7]; 2618 __le32 addr_high; 2619 __le32 addr_low; 2620 }; 2621 2622 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2623 2624 /* Add LLDP TLV (indirect 0x0A02) 2625 * Delete LLDP TLV (indirect 0x0A04) 2626 */ 2627 struct i40e_aqc_lldp_add_tlv { 2628 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2629 u8 reserved1[1]; 2630 __le16 len; 2631 u8 reserved2[4]; 2632 __le32 addr_high; 2633 __le32 addr_low; 2634 }; 2635 2636 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2637 2638 /* Update LLDP TLV (indirect 0x0A03) */ 2639 struct i40e_aqc_lldp_update_tlv { 2640 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2641 u8 reserved; 2642 __le16 old_len; 2643 __le16 new_offset; 2644 __le16 new_len; 2645 __le32 addr_high; 2646 __le32 addr_low; 2647 }; 2648 2649 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2650 2651 /* Stop LLDP (direct 0x0A05) */ 2652 struct i40e_aqc_lldp_stop { 2653 u8 command; 2654 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2655 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2656 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2657 u8 reserved[15]; 2658 }; 2659 2660 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2661 2662 /* Start LLDP (direct 0x0A06) */ 2663 2664 struct i40e_aqc_lldp_start { 2665 u8 command; 2666 #define I40E_AQ_LLDP_AGENT_START 0x1 2667 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 2668 u8 reserved[15]; 2669 }; 2670 2671 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2672 2673 /* Set DCB (direct 0x0303) */ 2674 struct i40e_aqc_set_dcb_parameters { 2675 u8 command; 2676 #define I40E_AQ_DCB_SET_AGENT 0x1 2677 #define I40E_DCB_VALID 0x1 2678 u8 valid_flags; 2679 u8 reserved[14]; 2680 }; 2681 2682 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2683 2684 /* Get CEE DCBX Oper Config (0x0A07) 2685 * uses the generic descriptor struct 2686 * returns below as indirect response 2687 */ 2688 2689 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2690 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2691 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2692 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2693 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2694 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2695 2696 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2697 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2698 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2699 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2700 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2701 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2702 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2703 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2704 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2705 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2706 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2707 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2708 2709 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2710 * word boundary layout issues, which the Linux compilers silently deal 2711 * with by adding padding, making the actual struct larger than designed. 2712 * However, the FW compiler for the NIC is less lenient and complains 2713 * about the struct. Hence, the struct defined here has an extra byte in 2714 * fields reserved3 and reserved4 to directly acknowledge that padding, 2715 * and the new length is used in the length check macro. 2716 */ 2717 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2718 u8 reserved1; 2719 u8 oper_num_tc; 2720 u8 oper_prio_tc[4]; 2721 u8 reserved2; 2722 u8 oper_tc_bw[8]; 2723 u8 oper_pfc_en; 2724 u8 reserved3[2]; 2725 __le16 oper_app_prio; 2726 u8 reserved4[2]; 2727 __le16 tlv_status; 2728 }; 2729 2730 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2731 2732 struct i40e_aqc_get_cee_dcb_cfg_resp { 2733 u8 oper_num_tc; 2734 u8 oper_prio_tc[4]; 2735 u8 oper_tc_bw[8]; 2736 u8 oper_pfc_en; 2737 __le16 oper_app_prio; 2738 __le32 tlv_status; 2739 u8 reserved[12]; 2740 }; 2741 2742 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2743 2744 /* Set Local LLDP MIB (indirect 0x0A08) 2745 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2746 */ 2747 struct i40e_aqc_lldp_set_local_mib { 2748 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2749 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2750 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2751 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2752 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2753 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2754 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2755 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2756 u8 type; 2757 u8 reserved0; 2758 __le16 length; 2759 u8 reserved1[4]; 2760 __le32 address_high; 2761 __le32 address_low; 2762 }; 2763 2764 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2765 2766 struct i40e_aqc_lldp_set_local_mib_resp { 2767 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2768 u8 status; 2769 u8 reserved[15]; 2770 }; 2771 2772 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2773 2774 /* Stop/Start LLDP Agent (direct 0x0A09) 2775 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2776 */ 2777 struct i40e_aqc_lldp_stop_start_specific_agent { 2778 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2779 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2780 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2781 u8 command; 2782 u8 reserved[15]; 2783 }; 2784 2785 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2786 2787 /* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2788 struct i40e_aqc_lldp_restore { 2789 u8 command; 2790 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2791 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2792 u8 reserved[15]; 2793 }; 2794 2795 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2796 2797 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2798 struct i40e_aqc_add_udp_tunnel { 2799 __le16 udp_port; 2800 u8 reserved0[3]; 2801 u8 protocol_type; 2802 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2803 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2804 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2805 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2806 u8 reserved1[10]; 2807 }; 2808 2809 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2810 2811 struct i40e_aqc_add_udp_tunnel_completion { 2812 __le16 udp_port; 2813 u8 filter_entry_index; 2814 u8 multiple_pfs; 2815 #define I40E_AQC_SINGLE_PF 0x0 2816 #define I40E_AQC_MULTIPLE_PFS 0x1 2817 u8 total_filters; 2818 u8 reserved[11]; 2819 }; 2820 2821 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2822 2823 /* remove UDP Tunnel command (0x0B01) */ 2824 struct i40e_aqc_remove_udp_tunnel { 2825 u8 reserved[2]; 2826 u8 index; /* 0 to 15 */ 2827 u8 reserved2[13]; 2828 }; 2829 2830 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2831 2832 struct i40e_aqc_del_udp_tunnel_completion { 2833 __le16 udp_port; 2834 u8 index; /* 0 to 15 */ 2835 u8 multiple_pfs; 2836 u8 total_filters_used; 2837 u8 reserved1[11]; 2838 }; 2839 2840 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2841 2842 struct i40e_aqc_get_set_rss_key { 2843 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2844 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2845 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2846 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2847 __le16 vsi_id; 2848 u8 reserved[6]; 2849 __le32 addr_high; 2850 __le32 addr_low; 2851 }; 2852 2853 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2854 2855 struct i40e_aqc_get_set_rss_key_data { 2856 u8 standard_rss_key[0x28]; 2857 u8 extended_hash_key[0xc]; 2858 }; 2859 2860 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2861 2862 struct i40e_aqc_get_set_rss_lut { 2863 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2864 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2865 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2866 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2867 __le16 vsi_id; 2868 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2869 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2870 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2871 2872 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2873 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2874 __le16 flags; 2875 u8 reserved[4]; 2876 __le32 addr_high; 2877 __le32 addr_low; 2878 }; 2879 2880 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2881 2882 /* tunnel key structure 0x0B10 */ 2883 2884 struct i40e_aqc_tunnel_key_structure { 2885 u8 key1_off; 2886 u8 key2_off; 2887 u8 key1_len; /* 0 to 15 */ 2888 u8 key2_len; /* 0 to 15 */ 2889 u8 flags; 2890 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2891 /* response flags */ 2892 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2893 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2894 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2895 u8 network_key_index; 2896 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2897 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2898 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2899 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2900 u8 reserved[10]; 2901 }; 2902 2903 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2904 2905 /* OEM mode commands (direct 0xFE0x) */ 2906 struct i40e_aqc_oem_param_change { 2907 __le32 param_type; 2908 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2909 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2910 #define I40E_AQ_OEM_PARAM_MAC 2 2911 __le32 param_value1; 2912 __le16 param_value2; 2913 u8 reserved[6]; 2914 }; 2915 2916 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2917 2918 struct i40e_aqc_oem_state_change { 2919 __le32 state; 2920 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2921 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2922 u8 reserved[12]; 2923 }; 2924 2925 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2926 2927 /* Initialize OCSD (0xFE02, direct) */ 2928 struct i40e_aqc_opc_oem_ocsd_initialize { 2929 u8 type_status; 2930 u8 reserved1[3]; 2931 __le32 ocsd_memory_block_addr_high; 2932 __le32 ocsd_memory_block_addr_low; 2933 __le32 requested_update_interval; 2934 }; 2935 2936 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2937 2938 /* Initialize OCBB (0xFE03, direct) */ 2939 struct i40e_aqc_opc_oem_ocbb_initialize { 2940 u8 type_status; 2941 u8 reserved1[3]; 2942 __le32 ocbb_memory_block_addr_high; 2943 __le32 ocbb_memory_block_addr_low; 2944 u8 reserved2[4]; 2945 }; 2946 2947 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2948 2949 /* debug commands */ 2950 2951 /* get device id (0xFF00) uses the generic structure */ 2952 2953 /* set test more (0xFF01, internal) */ 2954 2955 struct i40e_acq_set_test_mode { 2956 u8 mode; 2957 #define I40E_AQ_TEST_PARTIAL 0 2958 #define I40E_AQ_TEST_FULL 1 2959 #define I40E_AQ_TEST_NVM 2 2960 u8 reserved[3]; 2961 u8 command; 2962 #define I40E_AQ_TEST_OPEN 0 2963 #define I40E_AQ_TEST_CLOSE 1 2964 #define I40E_AQ_TEST_INC 2 2965 u8 reserved2[3]; 2966 __le32 address_high; 2967 __le32 address_low; 2968 }; 2969 2970 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2971 2972 /* Debug Read Register command (0xFF03) 2973 * Debug Write Register command (0xFF04) 2974 */ 2975 struct i40e_aqc_debug_reg_read_write { 2976 __le32 reserved; 2977 __le32 address; 2978 __le32 value_high; 2979 __le32 value_low; 2980 }; 2981 2982 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2983 2984 /* Scatter/gather Reg Read (indirect 0xFF05) 2985 * Scatter/gather Reg Write (indirect 0xFF06) 2986 */ 2987 2988 /* i40e_aq_desc is used for the command */ 2989 struct i40e_aqc_debug_reg_sg_element_data { 2990 __le32 address; 2991 __le32 value; 2992 }; 2993 2994 /* Debug Modify register (direct 0xFF07) */ 2995 struct i40e_aqc_debug_modify_reg { 2996 __le32 address; 2997 __le32 value; 2998 __le32 clear_mask; 2999 __le32 set_mask; 3000 }; 3001 3002 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 3003 3004 /* dump internal data (0xFF08, indirect) */ 3005 3006 #define I40E_AQ_CLUSTER_ID_AUX 0 3007 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 3008 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 3009 #define I40E_AQ_CLUSTER_ID_HMC 3 3010 #define I40E_AQ_CLUSTER_ID_MAC0 4 3011 #define I40E_AQ_CLUSTER_ID_MAC1 5 3012 #define I40E_AQ_CLUSTER_ID_MAC2 6 3013 #define I40E_AQ_CLUSTER_ID_MAC3 7 3014 #define I40E_AQ_CLUSTER_ID_DCB 8 3015 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 3016 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 3017 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 3018 3019 struct i40e_aqc_debug_dump_internals { 3020 u8 cluster_id; 3021 u8 table_id; 3022 __le16 data_size; 3023 __le32 idx; 3024 __le32 address_high; 3025 __le32 address_low; 3026 }; 3027 3028 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 3029 3030 struct i40e_aqc_debug_modify_internals { 3031 u8 cluster_id; 3032 u8 cluster_specific_params[7]; 3033 __le32 address_high; 3034 __le32 address_low; 3035 }; 3036 3037 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 3038 3039 #endif /* _I40E_ADMINQ_CMD_H_ */ 3040