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Searched refs:sq_attr (Results 1 – 7 of 7) sorted by relevance

/dpdk/drivers/net/mlx5/
H A Dmlx5_txpp.c255 sq_attr.cqn = wq->cq_obj.cq->id; in mlx5_txpp_create_rearm_queue()
430 sq_attr.tis_lst_sz = 1; in mlx5_txpp_create_clock_queue()
431 sq_attr.tis_num = sh->tis[0]->id; in mlx5_txpp_create_clock_queue()
432 sq_attr.non_wire = 0; in mlx5_txpp_create_clock_queue()
433 sq_attr.static_sq_wq = 1; in mlx5_txpp_create_clock_queue()
435 sq_attr.non_wire = 1; in mlx5_txpp_create_clock_queue()
436 sq_attr.static_sq_wq = 1; in mlx5_txpp_create_clock_queue()
438 sq_attr.cqn = wq->cq_obj.cq->id; in mlx5_txpp_create_clock_queue()
440 sq_attr.wq_attr.cd_slave = 1; in mlx5_txpp_create_clock_queue()
443 sq_attr.ts_format = in mlx5_txpp_create_clock_queue()
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H A Dmlx5_trigger.c267 struct mlx5_devx_modify_sq_attr sq_attr = { 0 }; in mlx5_hairpin_auto_bind() local
341 sq_attr.state = MLX5_SQC_STATE_RDY; in mlx5_hairpin_auto_bind()
342 sq_attr.sq_state = MLX5_SQC_STATE_RST; in mlx5_hairpin_auto_bind()
343 sq_attr.hairpin_peer_rq = rq->id; in mlx5_hairpin_auto_bind()
344 sq_attr.hairpin_peer_vhca = in mlx5_hairpin_auto_bind()
346 ret = mlx5_devx_cmd_modify_sq(sq, &sq_attr); in mlx5_hairpin_auto_bind()
553 sq_attr.state = MLX5_SQC_STATE_RDY; in mlx5_hairpin_queue_peer_bind()
554 sq_attr.sq_state = MLX5_SQC_STATE_RST; in mlx5_hairpin_queue_peer_bind()
555 sq_attr.hairpin_peer_rq = peer_info->qp_id; in mlx5_hairpin_queue_peer_bind()
668 sq_attr.state = MLX5_SQC_STATE_RST; in mlx5_hairpin_queue_peer_unbind()
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H A Dmlx5_flow_aso.c199 struct mlx5_devx_create_sq_attr sq_attr = { in mlx5_aso_sq_create() local
221 sq_attr.cqn = sq->cq.cq_obj.cq->id; in mlx5_aso_sq_create()
224 ret = mlx5_devx_sq_create(cdev->ctx, &sq->sq_obj, log_wqbb_n, &sq_attr, in mlx5_aso_sq_create()
H A Dmlx5_devx.c1217 struct mlx5_devx_create_sq_attr sq_attr = { in mlx5_txq_create_devx_sq_resources() local
1235 log_desc_n, &sq_attr, priv->sh->numa_node); in mlx5_txq_create_devx_sq_resources()
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_nicio.c544 struct hinic_sq_attr sq_attr; in hinic_init_qp_ctxts() local
595 sq_attr.ci_dma_base = in hinic_init_qp_ctxts()
598 sq_attr.pending_limit = 1; in hinic_init_qp_ctxts()
599 sq_attr.coalescing_time = 1; in hinic_init_qp_ctxts()
600 sq_attr.intr_en = 0; in hinic_init_qp_ctxts()
601 sq_attr.l2nic_sqn = q_id; in hinic_init_qp_ctxts()
602 sq_attr.dma_attr_off = 0; in hinic_init_qp_ctxts()
603 err = hinic_set_ci_table(hwdev, q_id, &sq_attr); in hinic_init_qp_ctxts()
/dpdk/drivers/common/mlx5/
H A Dmlx5_devx_cmds.c1671 struct mlx5_devx_create_sq_attr *sq_attr) in mlx5_devx_cmd_create_sq() argument
1688 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); in mlx5_devx_cmd_create_sq()
1690 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); in mlx5_devx_cmd_create_sq()
1693 sq_attr->allow_multi_pkt_send_wqe); in mlx5_devx_cmd_create_sq()
1695 sq_attr->min_wqe_inline_mode); in mlx5_devx_cmd_create_sq()
1696 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); in mlx5_devx_cmd_create_sq()
1703 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); in mlx5_devx_cmd_create_sq()
1705 sq_attr->packet_pacing_rate_limit_index); in mlx5_devx_cmd_create_sq()
1710 wq_attr = &sq_attr->wq_attr; in mlx5_devx_cmd_create_sq()
1737 struct mlx5_devx_modify_sq_attr *sq_attr) in mlx5_devx_cmd_modify_sq() argument
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H A Dmlx5_devx_cmds.h629 struct mlx5_devx_create_sq_attr *sq_attr);
632 struct mlx5_devx_modify_sq_attr *sq_attr);