Home
last modified time | relevance | path

Searched refs:shift (Results 1 – 25 of 78) sorted by relevance

1234

/dpdk/drivers/net/bnxt/tf_core/
H A Dtf_sram_mgr.c235 uint8_t shift; in tf_sram_free_slice() local
243 assert(shift < 8); in tf_sram_free_slice()
249 assert(shift < 4); in tf_sram_free_slice()
255 assert(shift < 2); in tf_sram_free_slice()
262 assert(shift < 1); in tf_sram_free_slice()
303 shift = 0; in tf_sram_get_next_slice_in_block()
308 shift = 1; in tf_sram_get_next_slice_in_block()
313 shift = 2; in tf_sram_get_next_slice_in_block()
319 shift = 0; in tf_sram_get_next_slice_in_block()
365 uint8_t shift; in tf_sram_is_slice_allocated_in_block() local
[all …]
H A Dtf_device_p4.c325 uint32_t shift; in tf_dev_p4_map_parif() local
333 shift = 4 * parif; in tf_dev_p4_map_parif()
334 parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift; in tf_dev_p4_map_parif()
335 parif_pf[0] |= pf << shift; in tf_dev_p4_map_parif()
337 shift = 4 * (parif - 8); in tf_dev_p4_map_parif()
338 parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift; in tf_dev_p4_map_parif()
339 parif_pf[1] |= pf << shift; in tf_dev_p4_map_parif()
H A Dtf_device_p58.c543 uint16_t *shift) in tf_dev_p58_get_sram_tbl_info() argument
556 *shift = 0; in tf_dev_p58_get_sram_tbl_info()
563 *shift = 3; in tf_dev_p58_get_sram_tbl_info()
567 *shift = 3; in tf_dev_p58_get_sram_tbl_info()
571 *shift = 3; in tf_dev_p58_get_sram_tbl_info()
575 *shift = 3; in tf_dev_p58_get_sram_tbl_info()
579 *shift = 0; in tf_dev_p58_get_sram_tbl_info()
H A Dtf_tbl.c21 #define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \ argument
22 *(new_idx) = (((idx) + (base)) << (shift)); \
556 uint16_t base = 0, shift = 0; in tf_tbl_get_resc_info() local
599 &shift); in tf_tbl_get_resc_info()
611 shift); in tf_tbl_get_resc_info()
/dpdk/drivers/common/cnxk/
H A Dcnxk_security_ar.h66 uint64_t shift; in cnxk_on_anti_replay_check() local
75 shift = seq - base; in cnxk_on_anti_replay_check()
76 if (shift < winsz) { /* In window */ in cnxk_on_anti_replay_check()
81 wptr = window + (shift >> WORD_SHIFT); in cnxk_on_anti_replay_check()
82 *wptr <<= shift; in cnxk_on_anti_replay_check()
133 shift = seq - base; in cnxk_on_anti_replay_check()
134 if (unlikely(shift >= winsz)) { in cnxk_on_anti_replay_check()
155 ar->wint = ((wint + shift - 1) % ex_winsz) + 1; in cnxk_on_anti_replay_check()
156 ar->winb = ((winb + shift - 1) % ex_winsz) + 1; in cnxk_on_anti_replay_check()
167 shiftwords = ((wint + shift - 1) >> WORD_SHIFT) - in cnxk_on_anti_replay_check()
H A Droc_npa.c323 aura->shift = plt_log2_u32(block_count); in npa_aura_pool_pair_alloc()
324 aura->shift = aura->shift < 8 ? 0 : aura->shift - 8; in npa_aura_pool_pair_alloc()
340 pool->shift = plt_log2_u32(block_count); in npa_aura_pool_pair_alloc()
341 pool->shift = pool->shift < 8 ? 0 : pool->shift - 8; in npa_aura_pool_pair_alloc()
H A Droc_bphy_cgx.c32 int shift = roc_model_is_cn10k() ? 20 : 18; in roc_bphy_cgx_read() local
35 return plt_read64(base + (lmac << shift) + offset); in roc_bphy_cgx_read()
42 int shift = roc_model_is_cn10k() ? 20 : 18; in roc_bphy_cgx_write() local
45 plt_write64(value, base + (lmac << shift) + offset); in roc_bphy_cgx_write()
/dpdk/drivers/net/bnxt/tf_ulp/
H A Dulp_utils.c92 int8_t shift; in ulp_bs_put_msb() local
99 if (shift >= 0) { in ulp_bs_put_msb()
100 tmp &= ~(mask << shift); in ulp_bs_put_msb()
101 tmp |= val << shift; in ulp_bs_put_msb()
105 tmp |= val >> -shift; in ulp_bs_put_msb()
110 tmp |= val << (8 + shift); in ulp_bs_put_msb()
122 uint8_t shift; in ulp_bs_put_lsb() local
126 shift = bitoffs; in ulp_bs_put_lsb()
543 shift = bitoffs; in ulp_bs_get_lsb()
600 int32_t shift; in ulp_bs_get_msb() local
[all …]
/dpdk/app/test/
H A Dtest_common.c60 uint32_t shift, pos; in test_bsf() local
68 for (shift = 0; shift < 63; shift++) { in test_bsf()
72 val64 = 1ULL << shift; in test_bsf()
73 if ((uint32_t)rte_bsf64(val64) != shift) in test_bsf()
77 if (pos != shift) in test_bsf()
80 if (shift > 31) in test_bsf()
83 val32 = 1U << shift; in test_bsf()
84 if ((uint32_t)rte_bsf32(val32) != shift) in test_bsf()
88 if (pos != shift) in test_bsf()
/dpdk/drivers/net/atlantic/
H A Datl_hw_regs.c14 u32 shift, u32 val) in aq_hw_write_reg_bit() argument
20 reg_new = (reg_old & (~msk)) | (val << shift); in aq_hw_write_reg_bit()
29 u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift) in aq_hw_read_reg_bit() argument
31 return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift); in aq_hw_read_reg_bit()
H A Datl_hw_regs.h47 u32 shift, u32 val);
48 u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift);
/dpdk/drivers/net/ngbe/base/
H A Dngbe_regs.h16 #define MS8(shift, mask) (((u8)(mask)) << (shift)) argument
17 #define LS8(val, shift, mask) (((u8)(val) & (u8)(mask)) << (shift)) argument
18 #define RS8(reg, shift, mask) (((u8)(reg) >> (shift)) & (u8)(mask)) argument
20 #define MS16(shift, mask) (((u16)(mask)) << (shift)) argument
21 #define LS16(val, shift, mask) (((u16)(val) & (u16)(mask)) << (shift)) argument
22 #define RS16(reg, shift, mask) (((u16)(reg) >> (shift)) & (u16)(mask)) argument
24 #define MS32(shift, mask) (((u32)(mask)) << (shift)) argument
28 #define MS64(shift, mask) (((u64)(mask)) << (shift)) argument
32 #define MS(shift, mask) MS32(shift, mask) argument
33 #define LS(val, shift, mask) LS32(val, shift, mask) argument
[all …]
/dpdk/drivers/net/hns3/
H A Dhns3_ethdev.h921 #define hns3_set_field(origin, mask, shift, val) \ argument
924 (origin) |= ((val) << (shift)) & (mask); \
926 #define hns3_get_field(origin, mask, shift) \ argument
927 (((origin) & (mask)) >> (shift))
928 #define hns3_set_bit(origin, shift, val) \ argument
929 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
930 #define hns3_get_bit(origin, shift) \ argument
931 hns3_get_field((origin), (0x1UL << (shift)), (shift))
933 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) argument
H A Dhns3_rss.c461 uint16_t idx, shift; in hns3_dev_rss_reta_update() local
476 shift = i % RTE_ETH_RETA_GROUP_SIZE; in hns3_dev_rss_reta_update()
477 if (reta_conf[idx].reta[shift] >= hw->alloc_rss_size) { in hns3_dev_rss_reta_update()
481 reta_conf[idx].reta[shift], in hns3_dev_rss_reta_update()
486 if (reta_conf[idx].mask & (1ULL << shift)) in hns3_dev_rss_reta_update()
487 indirection_tbl[i] = reta_conf[idx].reta[shift]; in hns3_dev_rss_reta_update()
516 uint16_t idx, shift; in hns3_dev_rss_reta_query() local
528 shift = i % RTE_ETH_RETA_GROUP_SIZE; in hns3_dev_rss_reta_query()
529 if (reta_conf[idx].mask & (1ULL << shift)) in hns3_dev_rss_reta_query()
530 reta_conf[idx].reta[shift] = in hns3_dev_rss_reta_query()
/dpdk/drivers/net/ixgbe/
H A Dixgbe_bypass.c163 u32 shift; in ixgbe_bypass_event_show() local
179 shift = BYPASS_WDTIMEOUT_SHIFT; in ixgbe_bypass_event_show()
182 shift = BYPASS_MAIN_ON_SHIFT; in ixgbe_bypass_event_show()
185 shift = BYPASS_MAIN_OFF_SHIFT; in ixgbe_bypass_event_show()
188 shift = BYPASS_AUX_ON_SHIFT; in ixgbe_bypass_event_show()
191 shift = BYPASS_AUX_OFF_SHIFT; in ixgbe_bypass_event_show()
197 *state = (by_ctl >> shift) & 0x3; in ixgbe_bypass_event_show()
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_regs.h16 #define MS8(shift, mask) (((u8)(mask)) << (shift)) argument
17 #define LS8(val, shift, mask) (((u8)(val) & (u8)(mask)) << (shift)) argument
18 #define RS8(reg, shift, mask) (((u8)(reg) >> (shift)) & (u8)(mask)) argument
20 #define MS16(shift, mask) (((u16)(mask)) << (shift)) argument
21 #define LS16(val, shift, mask) (((u16)(val) & (u16)(mask)) << (shift)) argument
22 #define RS16(reg, shift, mask) (((u16)(reg) >> (shift)) & (u16)(mask)) argument
24 #define MS32(shift, mask) (((u32)(mask)) << (shift)) argument
28 #define MS64(shift, mask) (((u64)(mask)) << (shift)) argument
32 #define MS(shift, mask) MS32(shift, mask) argument
33 #define LS(val, shift, mask) LS32(val, shift, mask) argument
[all …]
/dpdk/lib/eal/arm/include/
H A Drte_vect.h161 vshift_bytes_right(uint64x2_t reg, const unsigned int shift) in vshift_bytes_right() argument
166 shift)); in vshift_bytes_right()
175 vshift_bytes_left(uint64x2_t reg, const unsigned int shift) in vshift_bytes_left() argument
180 16 - shift)); in vshift_bytes_left()
/dpdk/drivers/crypto/bcmfs/hw/
H A Dbcmfs_rm_common.c41 rm_build_desc(uint64_t val, uint32_t shift, in rm_build_desc() argument
44 return((val & mask) << shift); in rm_build_desc()
/dpdk/doc/guides/nics/
H A Dcnxk.rst177 parsing custom pre_l2 headers, an offset, mask within the offset and shift
181 shift direction, 0: left shift, 1: right shift.
182 Info format will be "offset/mask/shift direction". All parameters has to be
192 mask 0x7e and right shift will be used to get the size. That is, size will be
193 (pkt[0x2] & 0x7e) >> shift count. Shift count will be calculated based on
194 mask and shift direction. For example, if mask is 0x7c and shift direction is
195 1 (i.e., right shift) then the shift count will be 2, that is, absolute
196 position of the rightmost set bit. If the mask is 0x7c and shift direction
197 is 0 (i.e., left shift) then the shift count will be 1, that is, (8 - n),
/dpdk/drivers/net/atlantic/hw_atl/
H A Dhw_atl_b0.c157 u32 shift = 0; in hw_atl_b0_hw_rss_set() local
161 val |= (u32)(indirection_table[i] % num_rss_queues) << shift; in hw_atl_b0_hw_rss_set()
162 shift += 3; in hw_atl_b0_hw_rss_set()
164 if (shift < 16) in hw_atl_b0_hw_rss_set()
177 shift -= 16; in hw_atl_b0_hw_rss_set()
/dpdk/drivers/net/qede/base/
H A Dmeson.build33 '-Wno-shift-negative-value',
38 '-Wno-shift-negative-value',
/dpdk/drivers/net/nfp/
H A Dnfp_common.c1011 int idx, shift; in nfp_net_rss_reta_write() local
1029 shift = i % RTE_ETH_RETA_GROUP_SIZE; in nfp_net_rss_reta_write()
1030 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF); in nfp_net_rss_reta_write()
1046 reta |= reta_conf[idx].reta[shift + j] << (8 * j); in nfp_net_rss_reta_write()
1048 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift, in nfp_net_rss_reta_write()
1087 int idx, shift; in nfp_net_reta_query() local
1110 shift = i % RTE_ETH_RETA_GROUP_SIZE; in nfp_net_reta_query()
1111 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF); in nfp_net_reta_query()
1117 shift); in nfp_net_reta_query()
1121 reta_conf[idx].reta[shift + j] = in nfp_net_reta_query()
/dpdk/drivers/event/cnxk/
H A Dcnxk_eventdev_stats.c11 const uint8_t shift; member
159 value = (value >> xstat->shift) & xstat->mask; in cnxk_sso_xstats_get()
224 value = (value >> xstat->shift) & xstat->mask; in cnxk_sso_xstats_reset()
/dpdk/drivers/net/cnxk/
H A Dcn10k_tx.h1393 *shift += 3; in cn10k_nix_prep_lmt_mseg_vector()
1458 << *shift; in cn10k_nix_prep_lmt_mseg_vector()
1459 *shift += 3; in cn10k_nix_prep_lmt_mseg_vector()
1491 *shift += 3; in cn10k_nix_prep_lmt_mseg_vector()
1509 *shift = *shift + 3; in cn10k_nix_lmt_next()
1613 uint8_t lnum, shift, loff; in cn10k_nix_xmit_pkts_vector() local
1692 shift = 16; in cn10k_nix_xmit_pkts_vector()
2576 &shift, &wd.data128, &next); in cn10k_nix_xmit_pkts_vector()
2592 &shift, &wd.data128, &next); in cn10k_nix_xmit_pkts_vector()
2608 &shift, &wd.data128, &next); in cn10k_nix_xmit_pkts_vector()
[all …]
/dpdk/drivers/net/mlx5/
H A Dmlx5_flow_flex.c118 uint32_t pos, uint32_t width, uint32_t shift) in mlx5_flex_get_bitfield() argument
125 MLX5_ASSERT(width + shift <= sizeof(uint32_t) * CHAR_BIT); in mlx5_flex_get_bitfield()
142 return rte_bswap32(val <<= shift); in mlx5_flex_get_bitfield()
241 uint32_t def = (RTE_BIT64(map->width) - 1) << map->shift; in mlx5_flex_flow_translate_item()
249 val = mlx5_flex_get_bitfield(spec, pos, map->width, map->shift); in mlx5_flex_flow_translate_item()
250 msk = mlx5_flex_get_bitfield(mask, pos, map->width, map->shift); in mlx5_flex_flow_translate_item()
349 mlx5_flex_hdr_len_mask(uint8_t shift, in mlx5_flex_hdr_len_mask() argument
353 int diff = shift - MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD; in mlx5_flex_hdr_len_mask()
773 trans->shift = 0; in mlx5_flex_map_sample()
810 trans->shift = cov_start - reg_start; in mlx5_flex_map_sample()

1234