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/dpdk/doc/guides/tools/
H A Dhugepages.rst9 As well as checking for current settings.
72 To display current huge page settings::
H A Dproc_info.rst51 The show-tm parameter displays per port traffic manager settings, current
56 settings and stats per node.
/dpdk/doc/guides/linux_gsg/
H A Dnic_perf_intel_platform.rst93 The following are some recommendations on BIOS settings. Different platforms will have different BI…
96 #. Establish the steady state for the system, consider reviewing BIOS settings desired for best per…
98 #. Match the BIOS settings to the needs of the application you are testing.
110 The following are some recommendations on GRUB boot settings:
H A Denable_func.rst73 Consult the relevant BIOS documentation to determine how these settings can be accessed.
113 #. Ensure that HPET is enabled in BIOS settings.
H A Dsys_reqs.rst14 For the majority of platforms, no special BIOS settings are needed to use basic DPDK functionality.
/dpdk/doc/guides/prog_guide/
H A Dbuild-sdk-meson.rst67 Meson will then configure the build based on settings in the project's
118 should be used to change the build settings within the directory, and when
134 As well as those settings taken from ``meson configure``, other options
143 settings, the tools for cross-compilation may be considered. However, for
198 where config/arm/arm64_armv8_linux_gcc contains settings for the compilers
H A Dlink_bonding_poll_mode_drv_lib.rst107 same speed and duplex settings using the selected balance transmit policy
160 Bonding device stores its own version of RSS settings i.e. RETA, RSS hash
209 All settings are managed through the bonding port API and always are propagated
H A Drte_flow.rst2000 Unlike global RSS settings used by other DPDK APIs, unsetting the ``types``
2002 unspecified "best-effort" settings from the underlying PMD, which depending
3962 depending on the global configuration settings of a port.
3988 entered. Likewise, existing flow rules or global configuration settings may
3994 settings.
4004 - Configuring global RSS settings.
4211 For devices exposing multiple ports sharing global settings affected by flow
/dpdk/doc/guides/nics/
H A Daf_packet.rst22 Some of these, in turn, will be used to configure the PACKET_MMAP settings.
46 For the full details behind PACKET_MMAP's structures and settings, consider
H A Dmlx5.rst183 size and ``txq_inline_min`` settings and may be from 2 (worst case forced by maximal
184 inline settings) to 58.
305 - The amount of descriptors in Tx queue may be limited by data inline settings.
308 reduce the requested Tx size or adjust data inline settings with
495 (configurable with ``REAL_TIME_CLOCK_ENABLE`` firmware settings),
696 ``txq_inline_mpw`` below and does not affect ``txq_inline_min`` settings above.
731 settings. This key also may update ``txq_inline_max`` value (default
781 specified and requested inline settings can not be satisfied then error
808 settings can not be satisfied then error will be raised.
1197 information about the settings.
H A Dnetvsc.rst76 Any settings done with driverctl are by default persistent and will be reapplied
H A Dmlx4.rst327 information about the settings.
/dpdk/doc/guides/sample_app_ug/
H A Dflow_filtering.rst114 The Ethernet port is configured with default settings using the
119 :start-after: Ethernet port configured with default settings. 8<
120 :end-before: >8 End of ethernet port configured with default settings.
H A Dflow_classify.rst161 :start-after: Initializing port using global settings. 8<
164 The Ethernet ports are configured with default settings using the
H A Dskeleton.rst108 The Ethernet ports are configured with default settings using the
H A Deventdev_pipeline.rst35 these settings is shown below:
H A Ddma.rst151 ports are configured with local settings using the ``rte_eth_dev_configure()``
/dpdk/drivers/net/i40e/base/
H A Di40e_common.c5670 switch (settings->fcoe_filt_num) { in i40e_validate_filter_settings()
5684 switch (settings->fcoe_cntx_num) { in i40e_validate_filter_settings()
5697 switch (settings->pe_filt_num) { in i40e_validate_filter_settings()
5710 pe_filt_size <<= (u32)settings->pe_filt_num; in i40e_validate_filter_settings()
5716 switch (settings->pe_cntx_num) { in i40e_validate_filter_settings()
5760 if (!settings) in i40e_set_filter_control()
5782 val |= ((u32)settings->fcoe_filt_num << in i40e_set_filter_control()
5787 val |= ((u32)settings->fcoe_cntx_num << in i40e_set_filter_control()
5799 if (settings->enable_fdir) in i40e_set_filter_control()
5801 if (settings->enable_ethtype) in i40e_set_filter_control()
[all …]
H A Di40e_prototype.h565 struct i40e_filter_control_settings *settings);
/dpdk/doc/guides/bbdevs/
H A Dacc100.rst166 queues, priorities, load balance, bandwidth and other settings necessary for the
H A Dfpga_5gnr_fec.rst151 queues, priorities, load balance, bandwidth and other settings necessary for the
H A Dfpga_lte_fec.rst150 queues, priorities, load balance, bandwidth and other settings necessary for the
/dpdk/drivers/net/i40e/
H A Di40e_ethdev.c2578 struct i40e_filter_control_settings settings; in i40e_dev_close() local
2644 memset(&settings, 0, sizeof(settings)); in i40e_dev_close()
2645 ret = i40e_set_filter_control(hw, &settings); in i40e_dev_close()
6188 struct i40e_filter_control_settings settings; in i40e_pf_setup() local
6231 memset(&settings, 0, sizeof(settings)); in i40e_pf_setup()
6233 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128; in i40e_pf_setup()
6235 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512; in i40e_pf_setup()
6246 settings.enable_ethtype = TRUE; in i40e_pf_setup()
6247 settings.enable_macvlan = TRUE; in i40e_pf_setup()
6248 ret = i40e_set_filter_control(hw, &settings); in i40e_pf_setup()
/dpdk/doc/guides/rel_notes/
H A Drelease_21_08.rst141 when used with some compilers settings.
/dpdk/drivers/net/qede/base/
H A Dmcp_public.h628 struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; member

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